rajesh_manjunath_resume
TRANSCRIPT
RAJESH MANJUNATH
720, W 27th Street, Apt 356, Los Angeles, CA – 90007, Ph: (213) 706-9792
[email protected] or [email protected]
EDUCATION
University of Southern California, Los Angeles, CA (GPA 3.56) Expected May 2017
Master of Science, Electrical Engineering (VLSI Design)
Completed Coursework: Computer Systems Organisation, MOS VLSI Design, Solid State Processing and IC Lab, Asynchronous
VLSI, VLSI System Design, System Verification
Ongoing Coursework: Advanced VLSI System Design
DSCE, Bangalore (80.34 %) June 2015
Bachelor of Engineering in Electronics and Communication
PROJECTS
Verification of Traffic Light Controller using UVM – Designed 3 test cases ( stable, random & a custom test) and verified
the functionality of a given traffic light controller Verilog module using UVM. Caught design bugs and eliminated them.
Verification of single clock FIFO using UVM – Designed all the hierarchical components (driver, monitor, scoreboard,
agent, sequencer, and environment) of UVM and verified a single clock FIFO by eliminating bugs and redundant signals.
Verification of Vending Machine using UVM – Implemented driver, monitor and scoreboard classes and verified the
functionality of a given vending machine Verilog module using UVM. Caught design bugs and eliminated them.
Designed a Reversi game in Python with Artificial Intelligence feature using Greedy weight algorithm and features to
save and load game from a previous stored state.
Naïve Bayes Classification using Machine Learning in Python – Performed NB learning on a big data set of (>5000)
sorted SPAM and HAM emails, and built a NB classifier to classify any email as SPAM or HAM using add-one smoothing.
Designed a Sudoku solver in Python using backtracking and DFS algorithms.
FPGA Prototyping of a digital timer design on Altera Cyclone IV FPGA. Used Quartus II and its tools TimeQuest and
PowerPlay to determine the various delays, slacks and power estimates of the design.
Design of a 5 stage pipelined processor using Cadence Virtuoso and Perl – Custom 16 bit RISC processor with
Instruction Fetch & Decode stages using Perl. Designed blocks for Execution, Memory & Writeback stages and designed
layout using Cadence Virtuoso for a given ISA.
Design of a 1k SRAM using Cadence Virtuoso – Physical layout design of a 4 bank, 16 bit wide, 256 bit/ bank SRAM
using Cadence Virtuoso.
Design of a 5 bit signed Baugh Wooley Multiplier – Physical layout designed using Cadence Virtuoso and minimised the
area-delay product.
Design of an asynchronous NoC with Forward Error Correction – Designed a 4x4 asynchronous mesh router using
SystemVerilog. EG-LDPC was used as FEC. A comprehensive testbench was designed to check the corner cases and also
stress test scenarios. The whole design was synthesized using Proteus.
Design of 800 MHz Digital Phase Locked Loop using Cadence Virtuoso – Physical layout design was done using
Cadence Virtuoso, and the area-power-lock time product was minimised.
Fabrication of Electrical Components on a 6” Wafer – Components such as transistor, resistor, diodes and capacitors
were fabricated using process like dry&wet oxidation, etching, diffusion etc and electrical characterisation was done.
RTL Coding of 5 stage pipeline using Verilog.
Implementation of EG-LDPC on FPGA – A communication system was designed using Verilog and synthesized on
Artix-7 for a general code length and a set of manual error pattern.
Designed small RTL modules for various labs.
TECHNICAL & SOFTWARE SKILLS
Verilog, SystemVerilog (Mailboxes, Queues, Virtual Interfaces, Assertions, Semaphores, Randomised Constraints, Covergroups),
Python, UVM, QuestaSim, Cadence Virtuoso, Xilinx ISE, Altera Quartus II, Perl, MATLAB, Formal Verification using LEC and
Model Checking, Machine Learning, FPGA Prototyping, Proteus, SystemVerilogCSP, C, VHDL, Algorithms, ModelSim, NCSim*,
DesignCompiler*, Primetime*, Velocity*, Keil uVision, Conformal*, CCS.
ACADEMIC ACHIEVEMENTS
Grader under Prof. Massoud Pedram Fall 2016
Course 477L – MOS VLSI Circuit Design
3rd Rank among the graduating batch 2011-15 from DSCE in Electronics & Communication Department
Won second prize in Project Exhibition Srishti-15 and best FPGA project.