rectifiers and filters - welcome to channabasaveshwara … · · 2017-09-21rectifiers and filters...

[Electronics Lab : 15 EEL 38] 2017-18

Dept. of EEE, CIT, Gubbi, Tumkur – 572 216 1

Experiment No. : 1 Date: ___/____/_______

Rectifiers and Filters

Aim : To design and testing of Full wave – centre tapped transformer type and Bridge type rectifier circuits

with and without Capacitor filter. Determination of ripple factor, regulation and efficiency

Apparatus Required :

Sl.

No. Particulars Range Quantity

1. Transformer As per design 01

2. Diode (BY 127) - 04

3. Resistors & Capacitors As per design -

4. Multimeter - 01

5. CRO Probes - 2 Set

6. Spring board and connecting wires - -

Theory:

Rectifier is a circuit which converts AC to pulsating DC. Rectifiers are used in construction of

DC power supplies. There are three types of rectifiers namely Half wave rectifier, Center tap full

wave rectifier and bridge rectifier.

In half wave rectification, either the positive or negative half of the AC wave is passed, while

the other half is blocked. Because only one half of the input waveform reaches the output, it is very

inefficient if used for power transfer.

A full-wave rectifier converts the whole of the input waveform to one of constant polarity

(positive or negative) at its output. Full-wave rectification converts both polarities of the input

waveform to DC (direct current), and is more efficient. Fullwave rectification can be obtained either

by using center tap transformer or by using bridge rectifier.

The output of a rectifier is not a smooth DC it consists of ac ripples therefore to convert this

pulsating DC in to smooth DC we use a circuit called filter. There are many types of filters like C

filter, L filter, LC filter, multiple LC filter, filter etc.. of all these C filter is the most fundamental

filter.



VDC

Circuit Diagram:

Full wave rectifier

a) Center tap FWR without filter b) Center tap FWR with „C‟ filter

a) Bridge Rectifier without filter b) Bridge Rectifier with „C‟ filter

Vi

Vm

2 t

Vo without filter

Vm

2 t Vo with „C‟ filter

Vrpp

VDC

2 t

D2

Vm



Design :

a) Center Tap Full Wave Rectifier / Bridge Rectifier Without filter

VDC = 2Vm / for FWR ( both center tap and bridge rectifier )

For the given VDC calculate Vm and Vrms = Vm / 2

Procedure :

1. Components / Equipment are tested for their good working condition

2. Connections are made as shown in the circuit diagram

3. Observe different waveforms on CRO

4. Measure VDC using multimeter in dc mode and Vm on CRO

5. Calculate Vrms from Vm using formula Vrms = Vm / 2 for Half wave rectifier Vrms = Vm /

2 for full wave rectifier

6. Calculate the efficiency, ripple factor and regulation. Compare the results with the theoretic

values.

Result :

Without filter :

Type of rectifier

- theoretical - practical - theoretical - practical

Center tap full

wave rectifier 0.48

81.2 %

Bridge

Rectifier 0.48

81.2 %

With filter :

Type of rectifier

theoretical

practical % Regulation

Center tap full

wave rectifier 0.006

Bridge

Rectifier 0.006



Choose the transformer of rating Vrms – 0 – Vrms / ≥ IDC for Center tap full wave rectifier and 0 –

Vrms / ≥ IDC for Bridge rectifier

The value of load resistance, RL = VDC / IDC, PRL = VDC2 / RL

b) Full Wave Rectifier with „C‟ filter

VDC = Vm – ( IDC / 4fC )

= 1 / ( 4 3 fCRL ) ( f = 50 Hz )

For the given value of VDC and IDC Calculate RL = VDC / IDC, PRL = VDC2 / RL

For the given Calculate the value of capacitor „C‟

For the given value of VDC and IDC Calculate Vm and Vrms = Vm / 2

Choose the transformer of rating,

Vrms – 0 – Vrms / ≥ IDC for Center tap full wave rectifier and 0 – Vrms / ≥ IDC for Bridge rectifier

Choose the capacitor of value C / ≥ Vm

Example - 1: Design an FWR for an output DC voltage of 10 V and load current of

10 mA. (Bridge and Center tap rectifier)

VDC = 10 V

Vm = (VDC X ) / 2 = 15.7 V

Vrms = Vm / 2 = 11.1 V 12 V

Choose a transformer of rating 12V – 0 – 12V / ≥ 10 mA for Center tap full wave rectifier

Choose a transformer of rating 0 – 12V / ≥ 10 mA for Bridge rectifier

RL = VDC / IDC = 1 K

PRL = VDC2 / RL = 0.1 W

Choose RL = 1 K / 0.1 W

Example – 2 : Design a full wave rectifier for VDC = 16 V, IDC = 16mA, = 0.006 (Bridge and

center tap rectifier)

RL = VDC / IDC = 1 K, PRL = VDC2 / RL = 0256 W

From = 1 / ( 4 3 fCRL ), C = 481 f, ( 470f ) ( f = 50 Hz )

From VDC = Vm – ( IDC / 4fC ), Vm = 16.17 V, Vrms = 11.43 V, ( 12 V )

Choose transformer of rating 12V - 0 – 12V / ≥ 16mA for center tap full wave rectifier

and 0 – 12V / ≥ 16mA for bridge rectifier

Choose RL = 1 K / 0.256 W, C = 470 f / ≥ 16.17V



Tabular Column :

Without filter

Circuit VDC Vm Vrms =VDC2

/ Vrms2

= (Vrms2

/ VDC2)-1

Center tap full

wave rectifier

Bridge

Rectifier

Note : Vrms = Vm / 2 for Half wave rectifier Vrms = Vm / 2 for full wave rectifier

With filter :

Circuit VDC

full load Vrpp Vrrms

VDC

no load

%

Regulation = Vrrms / VDC

Center tap full

wave rectifier

Bridge

rectifier

Note : Vrrms = Vrpp / 23

% Regulation = ( VDC no load – VDC full load ) / VDC full load




Simplification and Realization of Boolean Expression using logic gates/Universal

gates

Aim: Simplify and realize the given Boolean expressions using Logic Gates/Universal Gates

Apparatus:

Sl No Particulars Quantity

1 IC 7408,IC 7432 2 each

2 IC 7400,IC 7402 2 each

3 IC 7410 1

Theory:

Canonical Forms (Normal Forms): Any Boolean function can be written in disjunctive

normal form (sum of min-terms) or conjunctive normal form (product of max-terms).A Boolean

function can be represented by a Karnaugh map in which each cell corresponds two minterm. Sum of minterms : Sum Of Product (SOP) Product of maxterms : Product Of Sum (POS)

Procedure: 1. Verify that the gates are working.

2. Construct a truth table for the given problem.

3. Draw a Karnaugh Map corresponding to the given truth table.

4. Simplify the given Boolean expression manually using the Karnaugh Map.

A. Implementation Using Logic Gates 1. Realize the simplified expression using logic gates.

2. Make connections as per the logic gate diagram.

3. Apply the different combinations of input according to the truth tables.

4. Verify that the results are correct.



1) Y1=(A+BC)(B+A C ) using Basic Gates

Simplification:

Y1=(A+BC)(B+A C ) ( Given Expression)

= AB+ A C +BC (Using basic gates)

= BC+ CA +AB

=

Y1= ( A+BC)(B+ A C )

= (A+B)(A+C)(B+A)(B+ C )

= ))()(( CBBACA

=

A B C

Y1

AB . BC . CA (Using NAND Gates)

)( CA + )( BA + ( )CB (Using only NOR gates)



B. Implementation Using Universal Gates

1. Convert the AND-OR logic into NAND-NAND and NOR-NOR logic.

2. Implement the simplified Boolean expressions using only NAND gates, and then using only

NOR gates.

3. Connect the circuits according to the circuit diagrams, apply inputs according to the

truth table and verify the results.

Using Only NAND gates

Using only NOR gates Truth Table

A B C Y1

0 0 0 0

0 0 1 0

0 1 0 0

0 1 1 1

1 0 0 1

1 0 1 0

1 1 0 1

1 1 1 1

A B C

Y

1

1

A B C

Y1



2) Z= A B C +ABC + A B C+ABC

= A B (C+C )+AB(C+C )

= A B +AB (using Basic Gates)

Z=

Z=

Using NAND Gates Only

Using NOR Gates only

A B + AB ( Using only NAND Gates)

(A+ B )+( A +B) ( Using only NOR Gates)

A

B

Z

Z

A B



Circuit Diagram :

A. Series Clippers :

1. To pass positive peak above V level

Vi

V Vm

2 t

Vo

2 t

2. To pass positive peak above some reference level ( VR +V )

Vi

VR+V

Vm

2 t

Vo

2 t

Vi

Vo

V

Vi

Vo

VR +V

10 V p-p

500 Hz

10 V p-p

500 Hz

A K

A K




Testing of diode clipping and Clamping circuits

Aim : To design and study the series and shunt clipping circuits using diodes.


Sl.


1. Diode ( 1N4007 / BY 127 ) - 02

2. Resistor As per design -

3. Multimeter - 01

4. CRO Probes - 3 set

5. Spring Board and Connecting wires - -

Theory:

A clipper is a circuit that removes either positive or negative portion of a waveform. This kind

of processing is useful for signal shaping, circuit protection and communications. The clippers are

usually constructed by using diodes and resistors and some times to adjust the clipping level DC

power supplies are also used. There are two types of clippers namely series clippers and shunt

clippers. If the clipping element (diode) is in series with the source then we call it as series clippers

and if the clipping device is in parallel with the source then we call such circuit as shunt clippers.

Further based on the portion of a waveform clipped the clippers can be classified as positive clippers,

negative clippers and two level clippers (combination clippers).

Procedure:

1. Components / Equipment are tested for their good working condition.


3. Apply a sine wave of amplitude greater than the designed clipping level with frequency 500

Hz.

4. Observe the output wave form on the CRO

5. Observe the transfer characteristic curve on CRO by applying input waveform to channel – X

and output waveform to channel – Y.

6. Measure the clipped voltage and compare with the designed value.



3. To pass negative peak above -V level

Vi

Vm

-V 2 t

Vo

2 t

4. To pass negative peak above some reference level (-VR - V )

Vi

Vm

Vo 2 t

-VR-V

2 t

Vi

Vo

- V

Vi

Vo

- VR - V

10 V p-p

500 Hz

10 V p-p

500 Hz



5. To pass positive peak above some reference level (VR1+V) and negative peak above some

reference level -VR2 - V

Vi

VR1+V Vm

2 t

-VR2-V

Vo

2 t

Result:

A. Series Clippers

Sl.

No. Circuit

Designed

Clipping level

(Theoretical)

Observed

Clipping level in

CRO(Practical)

1. To pass positive peak above V level V = 0.7V

2. To pass positive peak above some

reference level VR +V

VR +V= 2.5+0.7

=3.2V

3. To pass negative peak above -V level -V = -0.7V

4. To pass negative peak above some

reference level -VR - V

-VR -V = -3-0.7

= -3.7V

5.

To pass positive peak above some

reference level (VR1+V) and negative

peak above some reference level -VR2-V

VR1+V = 2+0.7=2.7V

-VR2 - V =-2-0.7

=-2.7V

Vi

Vo

-VR2- V

VR1+ V

10 V p-p

500 Hz



B. Shunt Clippers

6. To remove positive peak above V level

Vi

V Vm

2 t

Vo

V

2 t

7. To remove positive peak above some reference level (VR +V)

Vi

VR+V Vm

2 t

Vo

VR+V

2 t

Vi

Vo

V

Vi

Vo

VR+ V

10 V p-p

500 Hz

10 V p-p

500 Hz



-V

VR- V

8. To remove negative peak above -V level

Vi

Vm

-V 2 t

Vo

-V 2 t

9. To pass positive peak above some reference level (VR-V)

Vi

VR-V Vm

2 t

Vo

VR-V 2 t

Vi

Vo

Vi

Vo

10 V p-p

500 Hz

10 V p-p

500 Hz



VR1+V

-VR2-V

10. To remove positive peak above some reference level (VR1+V) and negative peak above some

reference level (-VR2-V)

Vi

VR1+V Vm

2 t

-VR2-V

Vo

VR1+V

t 2 -VR2-V

Design :

Example – 1 : Design a clipping circuit to pass the positive peak above the reference level 2V

(Circuit 2)

VR + V = 2V Assume the diode to be silicon make then V = 0.6 V

Then VR = 2 – 0.6 = 1.4 V

Assume Rr = 100 K and Rf = 10

Then R = Rr Rf = 1 K

Example – 2 : Design a clipping circuit to remove positive peak above + 3 V negative peak

above – 4 V (Circuit 12)

VR1+V = + 3 V Assume the diode to be silicon make then V = 0.6 V

VR1 = 3 – 0.6 = 2.4 V

-VR2-V = - 4 V

-VR2 = - 4 + 0.6 = - 3.4 V

Vi

Vo

Vo

10 V p-p

500 Hz



VR2 = 3.4 V

Assume Rr = 100 K and Rf = 10

Then R = Rr Rf = 1 K

Result:

B. Shunt Clippers

Sl.

No. Circuit

Designed

Clipping level

(Theoretical)

Observed

Clipping level in

CRO(Practical)

6. To remove positive peak above V level V = 0.7V

7. To remove positive peak above some

reference level (VR +V)

(VR +V)=2+0.7=2.7V

8. To remove negative peak above -V level -V =-0.7V

9. To pass positive peak above some

reference level (VR-V)

VR-V =3-0.7=2.3V

10.

To remove positive peak above some

reference level (VR1+V) and negative

peak above some reference level (-VR2-V)

VR1+V =2+.7=2.7V

-VR2-V =-3-0.7

=-3.7V



Vi

Vo t

V

t

V

Vi

Vo t

V

t

V

Vi

Vo t

V

V

-V

VR-V

Circuit Diagram:

Positive Clampers:

1. Negative peak clamped to -V level

2. Negative peak clamped to positive reference level (VR-V)

3. Negative peak clamped to negative reference level (-VR-V)



Clamping Circuits

Aim : To design a clamping circuit for the given specification.


Sl.


1. Diode ( 1N4007 / BY 127 ) - 01


3. CRO Probes - 3 set

4. Spring board and connecting wires

Theory :

Clamper is a circuit which adds DC level to an AC waveform. There are two types of

clampers namely positive clampers and negative clampers. In positive clampers positive DC level

will be added to the AC waveform or the negative peak will be clamped to some other level. In

Negative peak clampers negative DC level will be added to the AC waveform or the positive peak

will be clamped to some other level.

Clampers are very much used in communication systems for example clampers are used in

analog television receivers for the purpose of restoring the dc component of the video signal prior to

its being fed to the picture tube.

Procedure :



3. Apply a square wave / triangular wave / sine wave input of amplitude 10 V peak to peak and

frequency of 1 kHz

4. Observe the input and output waveform keeping CRO in DC position

5. Measure the clamping level and compare with the designed value

Design :

For a clamper RC T let RC = 10 T

Assume f = 1 KHz, hence T = 1 ms, choose C = 1 f

Then R = 10 K



Vi

Vo t

t

V

V

Vi

Vo t

V

t

V

Vi

Vo t

V

t

V

V

VR+V

-VR+V

Negative Clampers :

4. Positive peak clamped to V level

5. Positive peak clamped to positive reference level (VR+V)

6. Positive peak clamped to negative reference level (-VR+V)



Result:

A. Positive Clampers

Sl.

No. Circuit

Designed

Clipping level

(Theoretical)

Observed

Clipping level in

CRO(Practical)

1. Negative peak clamped to -V level - V =-0.7V

2.

Negative peak clamped to positive

reference level (VR-V)

VR-V =2-0.7

=1.3V

3.

Negative peak clamped to negative

reference level (-VR-V)

-VR-V =-3-0.7

=-3.7V

B. Negative Clampers

4. Positive peak clamped to V level V =0.7V

5.

Positive peak clamped to positive

reference level (VR+V)

VR+V = 4+0.7

=4.7V

6.

Positive peak clamped to negative

reference level (-VR+V)

-VR+V =

-3+0.7=-2.3V

Example – 1 :Design a clamping circuit to clamp the negative peak to +3V ( Circuit 2 )

VR - V = 3 V Let the diode be silicon make then V = 0.6 V

VR = 3 + 0.6 = 3.6 V

2.Negative peak clamped to negative reference level (-2V)

-VR-V= -2,

VR=1.4V



Half Adder:

a) Half Adder using Basic gates

b) Half Adder using NAND Gates

Truth Table

A B SUM

(S)

CARRY

(C)

0 0 0 0

0 1 1 0

1 0 1 0

1 1 0 1

A

B S= AB

C= AB

A

B

S=AB

C=AB




Realization of half/Full adder and Half/Full Subtractors using logic gates

Aim: (i) To realize half/full adder using Logic gates & NAND gates

(ii) To realize half/full Subtractor using Logic gates & NAND gates Components Required:

Theory: Half-Adder: A combinational logic circuit that performs the addition of two data

bits, A and B, is called a half-adder. Addition will result in two output bits; one of

which is the sum bit S, and the other is the carry bit, C. The Boolean functions

describing the half-adder are: S =AB

C = A.B Full-Adder: The half-adder does not take the carry bit from its previous stage into

account. This carry bit from its previous stage is called carry-in bit. A

combinational logic circuit that adds two data bits, A and B, and a carry-in

bit,Cin,is called a full-adder. The Boolean functions describing the full-adder are:

S = A B Cin

C = A.B+ Cin (A B) Half Subtractor: Subtracting a single-bit binary value B from another A (i.e. A -B)

produces a difference bit D and a borrow out bit Br. This operation is called half

subtraction and the circuit to realize it is called a half subtractor. The Boolean functions describing the half-Subtractor are:

D =A B

Br= A’.B Full Subtractor: Subtracting two single-bit binary values, B, Cin from a single-bit

value A produces a difference bit D and a borrow out Br bit. This is called full

subtraction. The Boolean functions describing the full-subtractor are: D = A

B Cin, Br= A’.B + A’.Cin + B.Cin

Procedure: 1. Verify that the gates are working.

Sl no Particulars Quantity

1 IC 7400 3

2 7404,7486,7408,7432 1



2. Make the connections as per the circuit diagram for the half adder circuit,

on the trainer kit.

3. Switch on the VCC power supply and apply the various combinations of the

inputs according to the respective truth tables. 4. Verify that the outputs are according to the expected results.

5. Repeat the procedure for the full adder circuit, the half subtractor and full

subtractor circuits. 6. Verify that the sum/difference and carry/borrow bits are according to the

expected values.

FULL ADDER:

a) Full Adder using Basic Gates

b) Full Adder using NAND Gates only

Truth Table:

B S= ABC

C= AB+C(AB)

A

C

A

B

C

S= ABC

C= AB+C(AB)



SUM= S= ABC

C= AB+C(AB)

Half Subtractor:

a. Half Subtractor using Basic gates

b. Half Subtractor using NAND Gates

A B C Sum Carry

0 0 0 0 0

0 0 1 1 0

0 1 0 1 0

0 1 1 0 1

1 0 0 1 0

1 0 1 0 1

1 1 0 0 1

1 1 1 1 1

A

B

D=AB

A

B D= AB

Bo= AB

C= A B



Truth Table

Full Subtractor:

c. Full Subtractor using Basic Gates

d. Full Subtractor using Nand gates

Truth Table:

Diff= ABC

B0 = A B+C(AB)

A B Diff(D) Borrow

(B)

0 0 0 0

0 1 1 1

1 0 1 0

1 1 0 0

A B C Diff Borrow

0 0 0 0 0

0 0 1 1 1

0 1 0 1 1

0 1 1 0 1

1 0 0 1 0

1 0 1 0 0

1 1 0 0 0

1 1 1 1 1

A

B D= A B C

Bo= A B+C(AB)

C



Circuit Diagram:

RC coupled Single stage BJT amplifier:

Design :

Given, VCE = 5 V and IC = 2 mA Assume = 100

VCC = 2VCE = 2 X 5 = 10 V

Let VRE = 10% VCC = 1 V

RE = VRE / ( IC + IB )

IB = IC / = 2mA / 100 = 20 A

RE = 1 / ( 2m + 20 ) = 495

Choose RE = 470

Apply KVL to collector loop

VCC – IC RC – VCE – VE = 0

RC = (VCC – VCE – VE) / IC = (10 – 5 – 1) / 2 m

RC = 2 K Choose RC = 1.8 K

Let IR1 = 10 IB = 10 X 20 A = 200 A

VR2 = VBE + VE = 0.6 + 1 = 1.6 V ( Since transistor is silicon make VBE = 0.6 V )

R2 = VR2 / ( IR1 – IB ) = 1.6 / ( 200 A - 20 A )

R2 = 8.8 K Choose R2 = 8.2 K

R1 = ( VCC – VR2 ) / IR1 = ( 10 – 1.6 ) / 200 A

R1 = 42 K Choose R1 = 47 K

XCE < < RE

XCE = RE / 10

IR1

VR2

C

B

E

SL100

or

CL100

0.1F

0.1F



Experiment No. : 5(a) Date: ___/____/_______

RC Coupled Single Stage BJT Amplifier

Aim: To conduct an experiment to plot the frequency response of an RC coupled amplifier

and to find the half power points, bandwidth, input impedance, output impedance.

Apparatus Required:

Sl.


1. Transistor SL 100 - 01



4. Multi meter - 01

5. DRB - 01


Theory :

An amplifier is a circuit which increases the voltage, current or power level of i/p signal

where the frequency is maintained constant from o/p to i/p signal. The common emitter amplifier is

basically a current amplifier ( IC = Ib ) where IB is input current and IC is output current and is a

non unity value, in turn it provides voltage amplification. The ratio of collector current to base current

is noted as the current amplification factor and is denoted as „‟i.e.[ = IC/Ib], is very large.

In RC coupled CE amplifier R1, R2 and RC are selected in such a way that transistor operates

in active region and the operating point will be in the middle of active region. RE is used for

stabilization of operating point. Coupling capacitors CC1 and CC2 are used to block dc current flow

through load and the source. The emitter by-pass capacitor CE is connected to avoid negative

feedback. Input signal increases base current and the collector current increases by a factor . [i.e. Ic

= Ib]. Hence output voltage is large compared to input voltage which is known as amplification

An amplifier in which resistance-capacitance coupling is employed between stages and at the

input and an output point of the circuit is known as RC coupled amplifier. A capacitor provides a path

for signal currents between stages, with resistors connected from each side of the capacitor to the

power supply or to ground.

1 / ( 2 f CE ) = 470 / 10 Let f = 100 Hz

CE = 33 F Choose CE = 47 F

Choose CC1 = CC2 = 0.1 F



Tabular Column : Vi = ___________ V

F in Hz Vo in Volt AV = Vo / Vi Gain in dB = 20*log

AV

Procedure :


2. Connections are made as shown in the circuit diagram.

3. By keeping the voltage knobs in minimum position and current knob in maximum position

switch on the power supply.

4. By disconnecting the AC source measure the quiescent point (VCE and IC = VRC / RC)

To find frequency response :

1. Connect the AC source. Keeping the frequency of the AC source in mid band region (say 10

kHz) adjust the amplitude to get the distortion less output. Note down the amplitude of the

input signal.

2. Keeping the input amplitude constant, Vary the frequency in suitable steps and note down the

corresponding output amplitude.

3. Calculate AV and gain in decibels. Plot a graph of frequency Vs gain in dB. From the graph

calculate f L, f H and band width.

4. Calculate figure of merit.

To find the input impedance ( Zi ) :

1. Connections are made as shown in the diagram.

2. Keeping the DRB in its minimum position, apply input signal at mid band frequency (say

10kHz) and adjust the amplitude of the input signal to get distortion less output. Note down

the output amplitude.

3. Vary the DRB until the output amplitude becomes half of its previous value. The

corresponding DRB value gives the input impedance.

To find the output impedance ( Zo ) :




2. Keeping the DRB in its maximum position, apply input signal at mid band frequency (say

10kHz) and adjust the amplitude of the input signal to get distortion less output. Note down

the output amplitude.


corresponding DRB value gives the output impedance.

Circuit to find input impedance ( Zi ) :

Circuit to find output impedance ( Zo ) :

Ideal Graph :

Gain dB

3dB

Band width

f in Hz

f L f H

f L = Lower cutoff frequency f H = Higher cutoff frequency



Result:

1. Quiescent point : VCE = ____ V, IC = _____ mA

2. Voltage Gain ( AV ) = __________ ( in mid band region )

3. Bandwidth (BW) = ___________ Hz

4. figure of merit ( FM = AV * BW ) = ____________ Hz

5. Input impedance (Zi) = ____________, Output Impedance (Zo) = __________

Experiment No. : 5(b) Date: ___/____/_______

RC Coupled Single Stage FET Amplifier

Aim: To conduct an experiment to plot the frequency response of an RC coupled FET amplifier and

to find the half power points, bandwidth, input impedance, output impedance

Apparatus Required:

Sl.


1. FET BFW 10 - 01



4. Multi meter - 01

5. DRB - 01


Theory:

An amplifier is a circuit which increases the voltage, current or power level of i/p signal

where the frequency is maintained constant from o/p to i/p signal. In FET amplifier the output current

(ID) is a function of input voltage VGS. That is as VGS varies the drain current varies. VGS varies as

input signal varies in turn the drain current varies hence amplification takes place.

In RC coupled FET amplifier RD and RS are selected in such a way that FET operates in

active region and the operating point will be in the middle of active region. Coupling capacitors CC1

and CC2 are used to block dc current flow through load and the source. The source by-pass capacitor

CS is connected to avoid negative feedback.

An amplifier in which resistance-capacitance coupling is employed between stages and at the

input and output point of the circuit is known as RC coupled amplifier. A capacitor provides a path

for signal currents between stages, with resistors connected from each side of the capacitor to the

power supply or to ground.



5b) Circuit Diagram :

Design :

Given VDD = 10V, VGS(off) = -4V IDSS (max) = 12mA RG = 2 M

Formulae

ID = IDSS.(1 – VGS / VGS (off))2

-------------------------------------(1)

When VG = 0, Then VS = -VGS Applying KVL to output circuit

But VS = ID . RS VDD = ID . RD + VDS + ID .RS

When VG = 0, ID = IDSS RD = (10 – 5 – 4.6 x 10-3

x 330) / 4.6 x 10-3

VS = IDSS.RS RD = 756

IDSS.RS = -VGS (off) Choose RD = 820

RS = -(-4) / 12mA = 333 XCS < < RS

Choose RS = 330 XCS = RS / 10

From (1) 1 / ( 2 f CS ) = 470 / 10 Let f = 100 Hz

ID = IDSS.(1 – ID.RS / VGS (off))2 CS = 33 F Choose CS = 47 F

ID = IDSS.(1 + ID2.RS

2 / 16 - ID.RS /2) Choose CC1 = CC2 = 0.1 F

ID = 12 x 10-3

x (1 + ID2.330

2 / 16 - ID.330 /2)

81.675ID2 - 2.98ID +12 x 10

-3 = 0

ID = 4.6 mA or ID = 31.9 mA

Since ID cannot be greater than IDSS, Choose ID = 4.6 mA

Assume VDS = 50 % VDD

VDS = 5V

G

D

S

BFW 10

Substrate



Procedure:



3. By keeping the voltage knobs in minimum position and current knob in maximum position

switch on the power supply.

4. By disconnecting the AC source measure the quiescent point (VDS and ID = VRD / RD)

5. Connect the AC source. Keeping the frequency of the AC source in mid band region (say 10

kHz) adjust the amplitude to get the distortion less output. Note down the amplitude of the

input signal.

6. Keeping the input amplitude constant, Vary the frequency in suitable steps and note down the

corresponding output amplitude.

7. Calculate AV and gain in decibels. Plot a graph of frequency Vs gain in dB. From the graph

calculate f L, f H and band width.

8. Calculate figure of merit.

To find the input impedance ( Zi ) :


2. Keeping the DRB in its minimum position, apply input signal at mid band frequency (say 10

kHz) and adjust the amplitude of the input signal to get distortion less output. Note down the

output amplitude.


corresponding DRB value gives the input impedance.

To find the output impedance ( Zo ) :


2. Keeping the DRB in its maximum position, apply input signal at mid band frequency (say 10

kHz) and adjust the amplitude of the input signal to get distortion less output. Note down the

output amplitude.


corresponding DRB value gives the output impedance.



Circuit to find input impedance ( Zi ) :

Circuit to find output impedance ( Zo ) :

Ideal Graph :

Gain dB

3dB

Band width

f in Hz

f L f H

f L = Lower cutoff frequency f H = Higher cutoff frequency

Tabular Column: Vi = ___________ V

F in Hz Vo in Volt AV = Vo / Vi Gain in dB = 20*log

AV



Result:

1. Quiescent point : VDS = ____ V, ID = _____ mA, VGS = ____________ V

2. Voltage Gain ( AV ) = __________ ( in mid band region )

3. Bandwidth (BW) = ___________ Hz

4. figure of merit ( FM = AV * BW ) = ____________ Hz

5. Input impedance (Zi) = ____________, Output Impedance (Zo) = __________



1. 4-BIT BINARY ADDER

Example: 7+2=11 (1001) • 7 is realized at A3 A2 A1 A0 = 0111 • 2 is realized at B3 B2 B1 B0 = 0010

Sum = 1001 Procedure:

1. Check all the components for their working. 2. Insert the appropriate IC into the IC base. 3. Make connections as shown in the circuit diagram. 4. Apply augend and addend bits on A and B and cin=0. 5. Verify the results and observe the output of ADDER CIRCUIT

Circuit :

2. 4-Bit Binary Subtractor.

(i) 4 bit subtraction operation using 7483 for A>B and Cin=1

Example: 8 – 3 = 5 (0101)

• 8 is realized at A3 A2 A1 A0 = 1000

• 3 is realized at B3 B2 B1 B0 through X-OR gates = 0011

• Output of X-OR gate is 1’s complement = 1100

• 2’s Complement can be obtained by adding Cin = 1

Therefore Cin =1

A3 A2 A1 A0 = 1 0 0 0

B3 B2 B1 B0 = 1 1 0 0

S3 S2 S1 S0 = 0 1 0 1 Cout = 1 (Ignored)




Realization of parallel adder/Subtractors using 7483 chip- BCD to Excess-3

code conversion & Vice –Versa, Binary to Gray code conversion and vice-

versa

6 a) parallel adder/Subtractors using 7483

Aim: To design and set up the following circuit using IC 7483.

i) A 4-bit binary parallel adder.

ii) A 4-bit binary parallel subtractor. Components Required: IC 7483, IC 7486, Trainer kit, etc

Theory:

The Full adder can add single-digit binary numbers and carries. The largest

sum that can be obtained using a full adder is 112. Parallel adders can add

multiple-digit numbers. If full adders are placed in parallel, we can add two- or

four-digit numbers or any other size desired. Figure below uses STANDARD

SYMBOLS to show a parallel adder capable of adding two, two-digit binary

numbers The addend would be on A inputs, and the augend on the B inputs.

To add four bits need four full adders arranged in parallel. IC 7483 is a 4- bit

parallel adder is used.

MSB LSB

INPUTS Cin

A3 A2 A1 A0

B3 B2 B1 B0

OUTPUT Cout S3 S2 S1 S0



ii) 4 bit subtraction operation using 7483 for A<B and Cin=1

Example: 14 – 15 = -1 (1111)

• 14 is realized at A3 A2 A1 A0 = 1110

• 15 is realized at B3 B2 B1 B0 through X-OR gates = 1111

• Output of X-OR gate is 1’s complement of 15 = 0000

• 2’s Complement can be obtained by adding Cin = 1

Therefore Cin = 1

A3 A2 A1 A0 = 1 1 1 0

B3 B2 B1 B0 = 0 0 0 0

S3 S2 S1 S0 = 1 1 1 1 since the most significant bit of the result is 1, this is a negative number, so form

the two's complement of (1111)=0001(-1)

Procedure:

1. Check all the components for their working. 2. Insert the appropriate IC into the IC base. 3. Make connections as shown in the circuit diagram. 4. Apply Minuend and subtrahend bits on A and B and cin=1. 5. Verify the results and observe the outputs.

Circuit:



Experiment 6(b): CODE CONVERTERS. Aim: To design and realize the following using IC 7483.

(i) Excess-3 to BCD Code conversion and vice-versa (ii) Realization of Binary to Gray code conversion and vice versa

Components Required: IC 7483, IC 7486, Patch Cords & IC Trainer Kit.

Theory:

Code converter is a combinational circuit that translates the input code

word into a new corresponding word. The excess-3 code digit is obtained by

adding three to the corresponding BCD digit. To Construct a BCD-to-excess-3-

code converter with a 4-bit adder feed BCD code to the 4-bit adder as the first

operand and then feed constant 3 as the second operand. The output is the

corresponding excess-3 code. To make it work as a excess-3 to BCD converter, we feed excess-3 code as the

first operand and then feed 2's complement of 3 as the second operand. The

output is the BCD code.

Excess-3-code to BCD: Truth Table:

Excess-3 inputs BCD outputs

E3 E2 E1 E0 S3 S2 S1 S0

0 0 0 0 0 0 0 0

0 1 0 0 0 0 0 1

0 1 0 1 0 0 1 0

0 1 1 0 0 0 1 1

0 1 1 1 0 1 0 0

1 0 0 0 0 1 0 1

1 0 0 1 0 1 1 0

1 0 1 0 0 1 1 1

1 0 1 1 1 0 0 0

1 1 0 0 1 0 0 1



Procedure: 1. Check all the components for their working.

2. Insert the appropriate IC into the IC base.

3. Make connections as shown in the circuit diagram.

4. Apply Excess-3-code code as first operand (A) and binary 3 as second

operand(B) and Cin=1 for realizing Excess-3-code to BCD.

Circuit:

BCD to Excess-3-code: Truth Table:

BCD inputs Excess-3 outputs

A3 A2 A1 A0 S3 S2 S1 S0

0 0 0 0 0 0 0 0

0 0 0 1 0 1 0 0

0 0 1 0 0 1 0 1

0 0 1 1 0 1 1 0

0 1 0 0 0 1 1 1

0 1 0 1 1 0 0 0

0 1 1 0 1 0 0 1

0 1 1 1 1 0 1 0

1 0 0 0 1 0 1 1

1 0 0 1 1 1 0 0



Procedure: 1. Check all the components for their working. 2. Insert the appropriate IC into the IC base. 3. Make connections as shown in the circuit diagram. 4 Apply BCD code as first operand(A) and binary 3 as second operand(B) and cin=0 for

Realizing BCD-to-Excess-3-code:

Circuit :

RESULT:



Binary to Gray code Realization using Nand Gates



(ii)Binary to Gray code conversion and vice versa Components Required: IC 7486, IC 7400and IC 7408. Theory:

Binary to gray code conversion is a very simple process. There are several

steps to do this types of conversions. Steps given below elaborate on the idea on

this type of conversion. (1) The M.S.B. of the gray code will be exactly equal to the first bit of the given

binary number. (2) Now the second bit of the code will be exclusive-or of the first and second bit of

the given binary number, i.e if both the bits are same the result will be 0 and if

they are different the result will be 1. (3)The third bit of gray code will be equal to the exclusive -or of the second and

third bit of the given binary number. Thus the Binary to gray code conversion

goes on. One example given below can make your idea clear on this type of

conversion.

Gray code to binary conversion is again very simple and easy process. Following steps can make your idea clear on this type of conversions. (1) The M.S.B of the binary number will be equal to the M.S.B of the given gray

code. (2) Now if the second gray bit is 0 the second binary bit will be same as the

previous or the first bit. If the gray bit is 1 the second binary bit will alter. If it was

1 it will be 0 and if it was 0 it will be 1. (3) This step is continued for all the bits to do Gray code to binary conversion.



Karaungh maps: (i)Realization using Basic Gates:



Procedure:

1. Verify that the gates are working.

2. Write the proper truth table for the given Binary to Gray /Gray to binary

converter

3. Draw Karnaugh maps for each bit of output. Simplify the Karnaugh maps to get simplified

Boolean Expressions.

4. Make connections on the trainer kit as shown in the circuit diagram for the Binary to Gray /Gray

to Binary converter.

5. Check the outputs for the corresponding inputs.

BINARY TO GRAY CONVERSION: Truth Table:

Binary inputs Gray outputs

B3 B2 B1 B0 G3 G2 G1 G0

0 0 0 0 0 0 0 0

0 0 0 1 0 0 0 1

0 0 1 0 0 0 1 1

0 0 1 1 0 0 1 0

0 1 0 0 0 1 1 0

0 1 0 1 0 1 1 1

0 1 1 0 0 1 0 1

0 1 1 1 0 1 0 0

1 0 0 0 1 1 0 0

1 0 0 1 1 1 0 1

1 0 1 0 1 1 1 1

1 0 1 1 1 1 1 0

1 1 0 0 1 0 1 0

1 1 0 1 1 0 1 1

1 1 1 0 1 0 0 1

1 1 1 1 1 0 0 0



GRAY TO BINARY CONVERSION : Truth Table:

Gray

inputs Binary outputs

G3 G2 G1 G0 B3 B2 B1 B0

0 0 0 0 0 0 0 0

0 0 0 1 0 0 0 1

0 0 1 1 0 0 1 0

0 0 1 0 0 0 1 1

0 1 1 0 0 1 0 0

0 1 1 1 0 1 0 1

0 1 0 1 0 1 1 0

0 1 0 0 0 1 1 1

1 1 0 0 1 0 0 0

1 1 0 1 1 0 0 1

1 1 1 1 1 0 1 0

1 1 1 0 1 0 1 1

1 0 1 0 1 1 0 0

1 0 1 1 1 1 0 1

1 0 0 1 1 1 1 0

1 0 0 0 1 1 1 1

Karnaugh maps:



(i)Realization using Basic Gates:



d) Realization using Nand Gates:

RESULT:




RC Phase Shift Oscillator

Aim: To design and test an RC phase shift oscillator for the given frequency of oscillations.

Apparatus Required:

Sl.


1. Transistor SL 100 - 01



4. Multi meter - 01

5. DRB - 01


Theory:

An oscillator is an electronic circuit that produces a repetitive electronic signal, often a sine

wave or a square wave. RC-phase shift oscillator is used generally at low frequencies (Audio

frequency). It consists of a CE amplifier as basic amplifier circuit and three identical RC networks for

feed back, each section of RC network introduces a phase shift of 60 and the total phase shift by

feedback network is 180. The CE amplifier introduces 180 phase shift hence the overall phase shift

is 360. The feed back factor for an RC phase shift oscillator is 1/29, hence the gain of amplifier (A)

should be 29 to satisfy Barkhausen criteria.

The Barkhausen criteria states that in a positive feedback amplifier to obtain sustained

oscillations, the overall loop gain must be unity ( 1 ) and the overall phase shift must be 0 or 360.

When the power supply is switched on, due to random motion of electrons in passive

components like resistor, capacitor a noise voltage of different frequencies will be developed at the

collector terminal of transistor, out of these the designed frequency signal is fed back to the amplifier

by the feed back network and the process repeats to give suitable oscillation at output terminal

http://en.wikipedia.org/wiki/Electronic_circuit

http://en.wikipedia.org/wiki/Sine_wave


http://en.wikipedia.org/wiki/Square_wave



Circuit Diagram :

Design :

Given, VCE = 5 V, IC = 2 mA and (Assume = 100)

VCC = 2VCE = 2 X 5 = 10 V



IB = IC / = 2mA / 100 = 20 A

RE = 1 / ( 2m + 20 ) = 495

Choose RE = 470



RC = ( VCC – VCE – VE ) / IC = ( 10 – 5 – 1 ) / 2 m


Let IR1 = 10 IB = 10 X 20 A = 200 A


R2 = VR1 / ( IR1 – IB ) = 1.6 / ( 200 A - 20 A )

R2 = 8.8 K Choose R2 = 8.2 K

R1 = ( VCC – VR2 ) / IR1 = ( 10 – 1.6 ) / 200 A

R1 = 42 K Choose R1 = 47 K

t

Vo

T

fo = 1 / T Hz

C

B

E

SL100

or

CL100

0.1 F

0.1 F

R3 = R-Ri



XCE < < RE

XCE = RE / 10

1 / ( 2 f CE ) = 470 / 10 Let f = 100 Hz



Tank Circuit : Assume fo = 1 kHz

f o = 1/[(2 x x R x C (6+4k)0.5

]

where k = Rc / R, and Ri = R1 || R2 || hie

4k+23+29/k ≤ hfe

Assume hfe = β = 100

Therefore 4k+23+29/k = 100

4k2+23k+29 = 100

4k2 – 77k + 29 = 0

k = 18.865 or 0.385

if k = 18.865 , Rc / R = 18.865

R is very small. Therefore proper oscillations are not obtained

Choosing k = 0.385

Rc = 1.8 k

R = 4.675 k

Choose R = 4.7 k

C =1/[2 x x fo x R (6+4 x 0.385)0.5

]

C = 0.012 µF

Choose C = 0.01 µF

Ri = 8.2K || 47K || 1.1K

Ri = 0.9 k

R3 = R – Ri

R3 = 3.8 k

Procedure :

1. Components / equipment are tested for their good working condition.

2. Connections are made as shown in the diagram

3. The quiescent point of the amplifier is verified for the designed value.

4. Observe the output wave form on CRO and measure the frequency.

5. Verify the frequency with the designed value.



Result:

Q Point: VCE = _____ V, Ic = ______ mA

fo Theoretical = _____________ Hz

fo Practical = _______________ Hz




Design and testing Ring counter/Johnson counter.

Aim: To design and study the operation of a ring counter and a Johnson

Counter.

Components required: IC 7495, IC 7404, Patch Cards & IC Trainer Kit.

Theory:

A ring counter is a circular shift register which is initiated such that

only one of its flip-flops is the state one while others are in their zero states.

A ring counter is a Shift Register with the output of the last one connected to

the input of the first, that is, in a ring. Typically, a pattern consisting of a

single bit is circulated so the state repeats every n clock cycles if n flip-flops are

used. It can be used as a cycle counter of n states.

A Johnson counter (or switchtail ring counter, twisted-ring counter,

walking-ring counter, or Moebius counter) is a modified ring counter, where the

output from the last stage is inverted and fed back as input to the first

stage. The register cycles through a sequence of bit-patterns, whose length is

equal to twice the length of the shift register, continuing indefinitely. These

counters find specialist applications, including those similar to the decade

counter, digital-to-analog conversion, etc. They can be implemented easily

using D- or JK-type flip-flops.

Procedure:

1. Make the connections as shown in the respective circuit diagram.

2. Apply an initial input (1000) at the A, B, C, D pins respectively.

3. Keep Select Mode = HIGH (1) and apply one clock pulse.

4. Next, Select Mode = LOW (0) to switch to serial mode and apply clock pulses.

5. Observe the output after each clock pulse, record the observations and verify

that they match the expected outputs from the truth table.

6. Repeat the same procedure as above for the Johnson Counter circuit and

verify its operation



1.Ring Counter:

Circuit

Truth Table



2.JHONSON COUNTER

Truth Table:

Circuit:




Crystal Oscillator

Aim : To design and test a crystal oscillator.


Sl.


1. Transistor SL 100, Crystal - 1 each



4. Multi meter - 01

5. DCB - 02


Theory :

An oscillator is an electronic circuit that produces a repetitive electronic signal, often a sine

wave or a square wave. A crystal oscillator is an electronic circuit that uses the mechanical

resonance of a vibrating crystal of piezoelectric material to create an electrical signal with a very

precise frequency. This frequency is commonly used to keep track of time (as in quartz

wristwatches), to provide a stable clock signal for digital integrated circuits, and to stabilize

frequencies for radio transmitters and receivers. The most common type of piezoelectric resonator

used is the quartz crystal, so oscillator circuits designed around them were called "crystal oscillators".

Procedure :

1. Components / equipment are tested for their good working condition.

2. Connections are made as shown in the diagram

3. The quiescent point of the amplifier is verified for the designed value.

4. Observe the output wave form on CRO and measure the frequency.

5. Verify the frequency with the crystal frequency.

Result:

Q Point: VCE = _____ V, Ic = ______ mA

fo Crystal = _____________ Hz

fo Practical = _______________ Hz




http://en.wikipedia.org/wiki/Square_wave


http://en.wikipedia.org/wiki/Resonance

http://en.wikipedia.org/wiki/Crystal

http://en.wikipedia.org/wiki/Piezoelectricity#Materials

http://en.wikipedia.org/wiki/Frequency

http://en.wikipedia.org/wiki/Quartz_clock

http://en.wikipedia.org/wiki/Quartz_clock

http://en.wikipedia.org/wiki/Clock_signal

http://en.wikipedia.org/wiki/Digital

http://en.wikipedia.org/wiki/Integrated_circuits

http://en.wikipedia.org/wiki/Radio_transmitter

http://en.wikipedia.org/wiki/Radio_receiver

http://en.wikipedia.org/wiki/Quartz_crystal



Design :

Given, VCE = 5 V and IC = 2 mA Assume = 100

VCC = 2VCE = 2 X 5 = 10 V



IB = IC / = 2mA / 100 = 20 A

RE = 1 / ( 2m + 20 ) = 495, Choose RE = 470



RC = ( VCC – VCE – VE ) / IC = ( 10 – 5 – 1 ) / 2 m


Let IR1 = 10 IB = 10 X 20 A = 200 A


R2 = VR1 / ( IR1 – IB ) = 1.6 / ( 200 A - 20 A ) = 8.8 K Choose R2 = 8.2 K

R1 = ( VCC – VR2 ) / IR1 = ( 10 – 1.6 ) / 200 A = 42 K Choose R1 = 47 K

XCE < < RE, XCE = RE / 10

1 / ( 2 f CE ) = 470 / 10 Let f = 100 Hz





Vo

t

T

fo = 1 / T Hz

C

B

E

SL100

or

CL100




Design and testing of Sequence generator.

Aim: To design and study the operation of a Sequence Generator.

Components required: IC 7495, IC 7486, Patch Cards & IC Trainer Kit.

Procedure:

1. Truth table is constructed for the given sequence, and Karnaugh maps are

drawn in order to obtain a simplified Boolean expression for the circuit.


3. Mode M is set to LOW (0), and clock pulses are fed through Clk 1 (pin 9).

4. Clock pulses are applied at CLK 1 and the output values are noted, and

checked against the expected values from the truth table.

5.The functioning of the circuit as a sequence generator is verified.

Karnaugh Map:



Circuit

Truth Table

Result:




Class B Push Pull Power Amplifier

Aim: To determine the efficiency of class B push pull amplifier and to find the optimum load.

Apparatus Required:

Sl.


1. Transistor AD149 and 2N3055 - 1 each

2. Resistors as per design - -

3. Mili ammeter 0-20 mA 01

4. Multimeter - 01


6. Spring Board and Connecting wires - -

Theory:

To improve the full power efficiency of the Class A type amplifier it is possible to design the

amplifier circuit with two transistors in its output stage producing a "push-pull" type amplifier

configuration. Push-pull operation uses two "complementary" transistors, one an NPN-type and the

other a PNP-type with both power transistors receiving the same input signal together that is equal in

magnitude, but in opposite phase to each other. This results in one transistor only amplifying one half

or 1800 of the input waveform while the other transistor amplifies the other half or remaining 180

0 of

the waveform with the resulting "two-halves" being put back together at the output terminal. This

pushing and pulling of the alternating half cycles by the transistors gives this type of circuit its name

but they are more commonly known as Class B Amplifiers

The transistor base inputs are in "anti-phase" to each other as shown in circuit diagram, thus if

TR1 base goes positive driving the transistor into heavy conduction, its collector current will increase

but at the same time the base current of TR2 will go negative further into cut-off and the collector

current of this transistor decreases by an equal amount and vice versa. Hence negative halves are

amplified by one transistor and positive halves by the other transistor giving this push-pull effect.

Unlike the DC condition, these AC currents are ADDITIVE resulting in the two output half-cycles

being combined to reform the sine-wave which then appears across the load. Class B Amplifiers

have the advantage over Class A amplifier so that no current flows through the transistors when they

are in their quiescent state (ie, with no input signal), therefore no power is dissipated in the output

transistors when there is no signal present

Unlike Class A amplifier stages that require significant base bias thereby dissipating lots of heat -

even with no input signal. So the overall conversion efficiency ( η ) of the amplifier is greater than



that of the equivalent Class A with efficiencies reaching as high as 75% possible resulting in nearly

all modern types of push-pull amplifiers operated in this Class B mode.

While Class B amplifiers have a much high gain than the Class A types, one of the main

disadvantages of class B type push-pull amplifiers is that they suffer from an effect known commonly

as Crossover Distortion. This occurs during the transition when the transistors are switching over

from one to the other as each transistor does not stop or start conducting exactly at the zero crossover

point even if they are specially matched pairs. This is because the output transistors require a base-

emitter voltage greater than 0.7v for the bipolar transistor to start conducting which results in both

transistors being "OFF" at the same time. One way to eliminate this crossover distortion effect would

be to bias both the transistors at a point slightly above their cut-off point. This then would give us

what is commonly called an Class AB Amplifier circuit.

Ideal Graph:

Procedure :

1. Connections are made as shown in circuit diagram

2. Keep RL = 1K, and adjust the amplitude of input signal for distortion less output waveform.

3. RL is varied in convenient steps and corresponding Vo and IC are recorded.

4. Calculate PDC and Pac and calculate efficiency

5. Plot a graph of % versus RL and obtain the optimum load.

Result :

Maximum efficiency = ___________ %, Optimum load, RL opt = __________

%

RL in

max

Optimum load

http://www.electronics-tutorials.ws/amplifier/amp_7.html



Circuit Diagram :

Vo

t

Cross over distortion

Tabular Column:

Vi = ____________ V : VCC = ________ V

Sl.

No. RL in Ic in mA Vo in Volt Pdc = VCC. IC Pac=Vo

2 / 8RL % =Pac / PDC

B E

C

C

2N3055 / OC26

0.1 F 1000 F

TR1

TR2

OC26




Realization of 3 bit counters as a sequential circuit and MOD – N counter design

using 7476,7490, 74192, 74193.

Experiment 12(a): ASYNCHRONOUS COUNTERS

Aim: To design and test 3-bit binary asynchronous up/down counter using flip-fop IC 7476 for the given sequence. Components required: IC 7476,patch cards,trainer kit etc. Theory:

An asynchronous (ripple) counter is a single JK-type flip-flop, with its J (data) input fed from its own inverted output. This circuit can store one bit, and hence can count from zero to one before it overflows (starts over from 0). Notice that this creates a new clock with a 50% duty cycle at exactly half the frequency of the input clock. If this output is then used as the clock signal for a similarly arranged D flip-flop (remembering to invert the output to the input), one will get another 1 bit counter that counts half as fast. Putting them together yields a two-bit counter: We can continue to add additional flip-flops, always inverting the output to its own input, and using the output from the previous flip-flop as the clock signal. The result is called a ripple counter,

which can count to 2n − 1 where n is the number of bits (flip-flop stages) in the counter

PROCEDURE: 1. Check all the components for their working. 2. Make connections as shown in the circuit diagram. 3. Clock pulses are applied one by one at the clock input and output is observed at QA,QB and QC. 4. Verify the Truth Table and observe the outputs.



1. 3 Bit Asynchronous Up Counter

Truth Table: Circuit:

Clock

QC

QB

QA

0

0

0

0

1

0

0

1

2

0

1

0

3

0

1

1

4

1

0

0

5

1

0

1

6

1

1

0

7

1

1

1

8

0

0

0

9

0

0

1

Wave Forms:



2. 3 Bit Asynchronous Down Counter


Wave Forms:

Clock

QC

QB

QA

0

1

1

1

1

1

1

0

2

1

0

1

3

1

0

0

4

0

1

1

5

0

1

0

6

0

0

1

7

0

0

0

8

1

1

1

9

1

1

0



3. Mod 5 Up Counter:

Truth Table Waveforms:

Clock

QC

QB

QA

0

0

0

0

1

0

0

1

2

0

1

0

3

0

1

1

4

1

0

0

5

0

0

0



4. Mod 4 Down Counter:

Truth Table: Wave forms

Clock

QC

QB

QA

0

1

1

1

1

1

1

0

2

1

0

1

3

1

0

0

4

1

1

1



Circuit:

Waveforms:



Experiment 12(b): SYNCHRONOUS COUNTERS Aim: To design and test a 3 bit synchronous counter using 7476

Components required: IC7476,7408,Patch cards,trainer kit ,etc.

Theory:

In synchronous counters, the clock inputs of all the flip-flops are

connected together and are triggered by the input pulses. Thus, all the flip-

flops change state simultaneously (in parallel).

A synchronous binary counter counts from 0 to 2N-1, where N is the number of bits/flip-flops in the counter. Each flip-flop is used to represent one

bit. The flip-flop in the lowest-order position is complemented with every clock

pulse and a flip-flop in any other position is complemented on the next clock

pulse provided all the bits in the lower-order positions are equal to 1.

Procedure:

1. Check all the components for their working.


3. Clock pulses are applied one by one at the clock input and output is

observed at QA,QB and QC.

4. Verify the Truth Table and observe the outputs.

Truth Table:

Clock

QC

QB

QA

0

0

0

0

1

0

0

1

2

0

1

0

3

0

1

1

4

1

0

0

5

1

0

1

6

1

1

0

7

1

1

1



1. MOD 10 Counter: Truth Table: Circuit:

Clock

QD

QC

QB

QA

0

0

0

0

0

1

0

0

0

1

2

0

0

1

0

3

0

0

1

1

4

0

1

0

0

5

0

1

0

1

6

0

1

1

0

7

0

1

1

1

8

1

0

0

0

9

1

0

0

1

10

0

0

0

0



Experiment 12(c): DECADE COUNTERS

Aim: To rig up Mod N counter using IC 7490. Components required: IC7490,Patch-cords,trainer kit ,etc.

Procedure:



3. Clock pulses are applied one by one at the clock input and output is

observed at QA,QB ,QC and QD

4. Verify the Truth Table and observe the outputs.

Wave forms

5 12 9 8 11

14

10 1 2 3 6 7

Mod 2 Mod5

QA

QB

QC

QD

Vcc

I/p A

Clk

I/p B R1 R2 S1 S2



2. MOD 8 Counter:


Clock

QD

QC

QB

QA

0

0

0

0

0

1

0

0

0

1

2

0

0

1

0

3

0

0

1

1

4

0

1

0

0

5

0

1

0

1

6

0

1

1

0

7

0

1

1

1

8

0

0

0

0

Waveforms:

RESULT:



Experiment 12(d): PROGRAMMABLE 4 BIT SYNCHRONOUS

UP/DOWN COUNTERS

Aim: To rig up Mod N Synchronous up/down counter using IC 74193& 74192

Components required: IC74193,7400,7432,74192,Patch cards,trainer kit ,etc.

Procedure:



3. The preset value is made available at the data inputs C,B and A.

4. The load pin is made low so that the preset value appear at QA,QB ,QC andQD.

5. Connect the output of the gate to the load input.

6. Clock pulses are applied and truth table are verified.

1.Count from 3 to 8:

Truth table: Circuit

Clk

QD

QC

QB

QA

0

0

0

1

1

1

0

1

0

0

2

0

1

0

1

3

0

1

1

0

4

0

1

1

1

5

1

0

0

0

6

0

0

1

1



2.Count from 12 to 5

Circuit

Truth table:

Preset value=12, N=8

Result:

Clk

QD

QC

QB

QA

0

1

1

0

0

1

1

0

1

1

2

1

0

1

0

3

1

0

0

1

4

1

0

0

0

5

0

1

1

1

6

0

1

1

0

7

0

1

0

1

8

1

1

0

0



References

1. “Functional Electronics” by K. V. Ramanan, Tata McGraw Hill Publications.

2. “Electronic Devices and Circuits” by David A. Bell, PHI India Publications, New Delhi 4th

edition 2004.

3. “Electronic Devices and Circuit Theory” by Robert L. Boylestad and Louis Nashelsky, PHI

India Publications, New Delhi 8th

edition 2009.

4. “Integrated Electronics” by Jacob Millman and Christos C. Halkias, Tata McGraw Hill

Publications, 1991 edition.

5. “Network Analysis” by M. E. Van Valkenburg, PHI India Publications, 3rd

Edition, 1974.

6. “Network Analysis” by G. K. Mithal, Kanna Publication, 14th

Edition.

7. “Modern Physics” by Kenneth S. Krane, John Wiley and Sons Publications, 2nd

Edition 1998.

8. “Digital Logic Applications and Design”, John Yarbrough, Thomson Learning, 2001.

9. “Digital Principles and Design “, Donald D Givone, Tata McGraw Hill Edition, 2002.

10. “Fundamentals of logic design”, Charles H Roth, Jr; Thomson Learning, 2004.

11. “Logic and computer design Fundamentals”, Mono and Kim, Pearson, Second edition, 2001.

12. “Logic Design”, Sudhakar Samuel, Pearson/Saguine, 2007.



Viva Questions

1. Define rectifier.

2. Compare different type of rectifiers.

3. What are the different types of filters.

4. What are conductors, insulators, and semi-conductors? Give examples.

5. .Define gain of the amplifier

6. What are the functions of the three resistances R1 , R2 , Re?

7. .What are the functions of the capacitances CE and CC ?

8. Which configuration of a transistor is preferred when a transistor is used as a switch and why?

9. What is quiescent point?

10. .What is load line?

11. Compare FET with BJT.

12. 1.Explain the function of the tank circuit.

13. What is Barkhausen‟s criterion and how is it satisfied?

14. .How can the frequency of oscillations be altered

15. What are Analog Systems? Give Examples

16. What are Digital Systems? Give Examples

17. State Demorgans Law?

18. Define MINTERM, MAX TERM

19. Which are the basic gates, universal gates

20. Define combinational network with example

21. Define Sequential Network with example

22. Explain the significance of a Don‟t care function

23. What is a minimal Sum, Minimal product?

24. Define Comparator

25. Define Decoder

26. Define Encoder

27. Define setting and clearing in terms of flip-flop

28. Explain SR Latch

29. Give an application of SR Latch

30. Explain Timing Diagram

31. Explain Propagation Delay in gates



MODEL QUESTIONS

1. a) Design a RC coupled single stage BJT amplifier and determine the Gain-frequency

response, input and output impedances.

b) Realize and verify the truth table of a full adder and half adder using basic gates and

NAND gates only

2. a) Design a RC coupled single stage FET amplifier and determine the Gain-frequency

response, input and output impedances.

b) Realize and verify the truth table of full and half subtractor using basic gates and NAND

gates only

3. a) Design the clipping circuit, which has the following transfer characteristics.

b) Conduct a suitable experiment on 7483 IC to realize the following

Operation on the given 4 bit data i) Addition ii) 2‟s Complement Subtraction

4. a) Design and test the performance of BJT-RC phase shift oscillator for fo = 1kHz.

b) Simplify and realize the given Boolean Expression using Basic Logic gates/universal gates

and verify the truth table

5. a) Rig up and test Center tap full wave rectifier circuit with and without „C‟ filter and

determine ripple factor, efficiency and regulation.

b) Realize a 3-bit binary asynchronous up counter/down counter using IC 7476 (N<=7) and

verify its truth table

6. a) Design the clipping circuits to obtain the following output waveform.



b) Realize using XOR/ NAND gates and verify the truth table of

(i) Binary to gray converter (ii) Gray to Binary Converter

7. a) Design and test the performance of a BJT Crystal oscillator.

b) Conduct an experiment to convert the given BCD data to excess-3 code/excess-3 to BCD

Using minimum number of basic gates

8. a) Design and test clamping circuits to clamp positive peak\ negative peak to ________

reference level

b) Design and realize a Ring counter/Johnson counter.

9. a) Design and test clipping (series) circuits to pass positive peak above ___________

Reference level

b) Design and realize a sequence generator for the sequence……………………….

10. a) Rig up and test Bridge rectifier circuit with and without „C‟ filter and determine ripple

factor, efficiency and regulation

b) Realize a Mod N binary synchronous counter using 7476 and verify the truth table

11. a) Rig up and test a class B push pull amplifier and determine its conversion

efficiency.

b) Realize and verify the truth table of full and half subtractor using basic gates and NAND

gates only

12. a) Design and test clipping (shunt) circuit to remove positive peak above ________

Reference level

b) Realize a Modulo N counter using 74192/ 74193 with a given preset value and

verify its truth table.

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