register file using vhdl
DESCRIPTION
This document contains vhdl code for 32 bit register fileTRANSCRIPT
STRUCTURAL VHDL CODE FOR D FLIP FLOP
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
ENTITY Dff_struct IS
PORT(D:IN STD_LOGIC;
CLK:IN STD_LOGIC;
Q,QBAR:OUT STD_LOGIC
);
END Dff_struct;
ARCHITECTURE Dff_struct OF Dff_struct IS
SIGNAL S:STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL X,Y:STD_LOGIC;
COMPONENT NAND2 IS
PORT(A,B:IN STD_LOGIC;
C :OUT STD_LOGIC
);
END COMPONENT;
COMPONENT NAND3 IS
PORT(A,B,C:IN STD_LOGIC;
D :OUT STD_LOGIC
);
END COMPONENT;
BEGIN
Q<=Y;
QBAR<=X;
M01:NAND2 PORT MAP(D,S(1),S(0));
M02:NAND3 PORT MAP(CLK,S(2),S(0),S(1));
M03:NAND2 PORT MAP(CLK,S(3),S(2));
M04:NAND2 PORT MAP(S(0),S(2),S(3));
M05:NAND2 PORT MAP(S(2),X,Y);
M06:NAND2 PORT MAP(S(1),Y,X);
END Dff_struct;
STRUCTURAL CODE FOR D FLIP FLOP WITH ENABLE INPUT
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
ENTITY DFF_ENB IS
PORT(DIN:IN STD_LOGIC;
ENB:IN STD_LOGIC;
CLK:IN STD_LOGIC;
Q,QBAR:OUT STD_LOGIC
);
END;
ARCHITECTURE RTL OF DFF_ENB IS
SIGNAL S:STD_LOGIC;
COMPONENT Dff_STRUCT IS
PORT(D:IN STD_LOGIC;
CLK:IN STD_LOGIC;
Q,QBAR:OUT STD_LOGIC
);
END COMPONENT;
COMPONENT MUX2_1 IS
PORT(A,B:IN STD_LOGIC;
SEL:IN STD_LOGIC;
MOUT:OUT STD_LOGIC
);
END COMPONENT;
BEGIN
M01:MUX2_1 PORT MAP(DIN,'0',ENB,S);
M02:DFF_STRUCT PORT MAP(S,CLK,Q,QBAR);
END RTL;
STRUCTURAL CODE FOR 32 BIT REGISTER
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
ENTITY REG_32BIT IS
PORT(I:IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ENB:IN STD_LOGIC;
CLK:IN STD_LOGIC;
O:OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
OBAR:OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END REG_32BIT;
ARCHITECTURE RTL OF REG_32BIT IS
COMPONENT Dff_struct IS
PORT(D,CLK:IN STD_LOGIC;
Q,QBAR:OUT STD_LOGIC
);
END COMPONENT;
COMPONENT DFF_ENB IS
PORT(DIN:IN STD_LOGIC;
ENB:IN STD_LOGIC;
CLK:IN STD_LOGIC;
Q,QBAR:OUT STD_LOGIC
);
END COMPONENT;
BEGIN
D0:DFF_ENB PORT MAP(I(0),ENB,CLK,O(0),OBAR(0));
D1:DFF_ENB PORT MAP(I(1),ENB,CLK,O(1),OBAR(1));
D2:DFF_ENB PORT MAP(I(2),ENB,CLK,O(2),OBAR(2));
D3:DFF_ENB PORT MAP(I(3),ENB,CLK,O(3),OBAR(3));
D4:DFF_ENB PORT MAP(I(4),ENB,CLK,O(4),OBAR(4));
D5:DFF_ENB PORT MAP(I(5),ENB,CLK,O(5),OBAR(5));
D6:DFF_ENB PORT MAP(I(6),ENB,CLK,O(6),OBAR(6));
D7:DFF_ENB PORT MAP(I(7),ENB,CLK,O(7),OBAR(7));
D8:DFF_ENB PORT MAP(I(8),ENB,CLK,O(8),OBAR(8));
D9:DFF_ENB PORT MAP(I(9),ENB,CLK,O(9),OBAR(9));
D10:DFF_ENB PORT MAP(I(10),ENB,CLK,O(10),OBAR(10));
D11:DFF_ENB PORT MAP(I(11),ENB,CLK,O(11),OBAR(11));
D12:DFF_ENB PORT MAP(I(12),ENB,CLK,O(12),OBAR(12));
D13:DFF_ENB PORT MAP(I(13),ENB,CLK,O(13),OBAR(13));
D14:DFF_ENB PORT MAP(I(14),ENB,CLK,O(14),OBAR(14));
D15:DFF_ENB PORT MAP(I(15),ENB,CLK,O(15),OBAR(15));
D16:DFF_ENB PORT MAP(I(16),ENB,CLK,O(16),OBAR(16));
D17:DFF_ENB PORT MAP(I(17),ENB,CLK,O(17),OBAR(17));
D18:DFF_ENB PORT MAP(I(18),ENB,CLK,O(18),OBAR(18));
D19:DFF_ENB PORT MAP(I(19),ENB,CLK,O(19),OBAR(19));
D20:DFF_ENB PORT MAP(I(20),ENB,CLK,O(20),OBAR(20));
D21:DFF_ENB PORT MAP(I(21),ENB,CLK,O(21),OBAR(21));
D22:DFF_ENB PORT MAP(I(22),ENB,CLK,O(22),OBAR(22));
D23:DFF_ENB PORT MAP(I(23),ENB,CLK,O(23),OBAR(23));
D24:DFF_ENB PORT MAP(I(24),ENB,CLK,O(24),OBAR(24));
D25:DFF_ENB PORT MAP(I(25),ENB,CLK,O(25),OBAR(25));
D26:DFF_ENB PORT MAP(I(26),ENB,CLK,O(26),OBAR(26));
D27:DFF_ENB PORT MAP(I(27),ENB,CLK,O(27),OBAR(27));
D28:DFF_ENB PORT MAP(I(28),ENB,CLK,O(28),OBAR(28));
D29:DFF_ENB PORT MAP(I(29),ENB,CLK,O(29),OBAR(29));
D30:DFF_ENB PORT MAP(I(30),ENB,CLK,O(30),OBAR(30));
D31:DFF_ENB PORT MAP(I(31),ENB,CLK,O(31),OBAR(31));
END RTL;
BEHAVIORAL CODE FOR 32 BIT 16 TO 1 MULTIPLEXER
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY MUX32_16_TO_1 IS
PORT ( A: in STD_LOGIC_VECTOR(31 downto 0);
B: in STD_LOGIC_VECTOR(31 downto 0);
C: in STD_LOGIC_VECTOR(31 downto 0);
D: in STD_LOGIC_VECTOR(31 downto 0);
E: in STD_LOGIC_VECTOR(31 downto 0);
F: in STD_LOGIC_VECTOR(31 downto 0);
G: in STD_LOGIC_VECTOR(31 downto 0);
H: in STD_LOGIC_VECTOR(31 downto 0);
I: in STD_LOGIC_VECTOR(31 downto 0);
J: in STD_LOGIC_VECTOR(31 downto 0);
K: in STD_LOGIC_VECTOR(31 downto 0);
L: in STD_LOGIC_VECTOR(31 downto 0);
M: in STD_LOGIC_VECTOR(31 downto 0);
N: in STD_LOGIC_VECTOR(31 downto 0);
O: in STD_LOGIC_VECTOR(31 downto 0);
P: in STD_LOGIC_VECTOR(31 downto 0);
RSEL:IN STD_LOGIC_VECTOR(3 DOWNTO 0);
ROUT:OUT STD_LOGIC_VECTOR(31 downto 0)
);
END MUX32_16_TO_1;
ARCHITECTURE BEHAVIORAL OF MUX32_16_TO_1 IS
BEGIN
PROCESS(RSEL,A,B,C,D,E,F,G,H,I,J,K,L,M,N,O,P)
BEGIN
CASE RSEL IS
WHEN "0000" => ROUT<=A;
WHEN "0001" => ROUT<=B;
WHEN "0010" => ROUT<=C;
WHEN "0011" => ROUT<=D;
WHEN "0100" => ROUT<=E;
WHEN "0101" => ROUT<=F;
WHEN "0110" => ROUT<=G;
WHEN "0111" => ROUT<=H;
WHEN "1000" => ROUT<=I;
WHEN "1001" => ROUT<=J;
WHEN "1010" => ROUT<=K;
WHEN "1011" => ROUT<=L;
WHEN "1100" => ROUT<=M;
WHEN "1101" => ROUT<=N;
WHEN "1110" => ROUT<=O;
WHEN OTHERS => ROUT<=P;
END CASE;
END PROCESS;
END BEHAVIORAL;
BEHAVIORAL CODE FOR 2 T0 1 MULTIPLEXER
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity mux2_1 is
port(A,B:IN STD_LOGIC;
SEL:IN STD_LOGIC;
MOUT:OUT STD_LOGIC
);
end mux2_1;
architecture Behavioral of mux2_1 is
begin
PROCESS(A,B,SEL)
BEGIN
IF SEL='1'THEN
MOUT<=A;
ELSE
MOUT<=B;
END IF;
END PROCESS;
end Behavioral;
BEHAVIORAL CODE FOR NOT GATE
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
ENTITY NOT2 IS
PORT(A:IN STD_LOGIC;
C :OUT STD_LOGIC
);
END NOT2;
ARCHITECTURE NOT2 OF NOT2 IS
BEGIN
C<= NOT A;
END NOT2;
BEHAVIORAL CODE FOR 3 INPUT NAND GATE
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
ENTITY NAND3 IS
PORT(A,B,C:IN STD_LOGIC;
D :OUT STD_LOGIC
);
END NAND3;
ARCHITECTURE NAND3 OF NAND3 IS
BEGIN
D<=NOT(A AND B AND C);
END NAND3;
BEHAVIORAL CODE FOR 2 INPUT NAND GATE
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
ENTITY NAND2 IS
PORT(A,B:IN STD_LOGIC;
C :OUT STD_LOGIC
);
END NAND2;
ARCHITECTURE NAND2 OF NAND2 IS
BEGIN
C<=NOT(A AND B);
END NAND2;
STRUCTURAL CODE FOR 4 TO 16 DECODER
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
ENTITY DECODER IS
PORT(S0,S1,S2,S3 :IN STD_LOGIC;
EN:IN STD_LOGIC;
D:OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
);
END ;
ARCHITECTURE RTL OF DECODER IS
SIGNAL A,B,C,F,E:STD_LOGIC;
COMPONENT NOT2 IS
PORT(A:IN STD_LOGIC;
C :OUT STD_LOGIC
);
END COMPONENT;
COMPONENT AND_REDUCE5 IS
PORT(A,B,C,D,E:IN STD_LOGIC;
F :OUT STD_LOGIC
);
END COMPONENT;
BEGIN
N01:NOT2 PORT MAP (S0,A);
N02:NOT2 PORT MAP (S1,B);
N03:NOT2 PORT MAP (S2,C);
N04:NOT2 PORT MAP (S3,F);
N05:NOT2 PORT MAP (EN,E);
M01:AND_REDUCE5 PORT MAP (A,B,C,F,E,D(0));
M02:AND_REDUCE5 PORT MAP (s0,B,C,F,E,D(1));
M03:AND_REDUCE5 PORT MAP (A,S1,C,F,E,D(2));
M04:AND_REDUCE5 PORT MAP (S0,S1,C,F,E,D(3));
M05:AND_REDUCE5 PORT MAP (A,B,S2,F,E,D(4));
M06:AND_REDUCE5 PORT MAP (S0,B,S2,F,E,D(5));
M07:AND_REDUCE5 PORT MAP (A,S1,S2,F,E,D(6));
M08:AND_REDUCE5 PORT MAP (S0,S1,S2,F,E,D(7));
M09:AND_REDUCE5 PORT MAP (A,B,C,S3,E,D(8));
M10:AND_REDUCE5 PORT MAP (S0,B,C,S3,E,D(9));
M11:AND_REDUCE5 PORT MAP (A,S1,C,S3,E,D(10));
M12:AND_REDUCE5 PORT MAP (S0,S1,C,S3,E,D(11));
M13:AND_REDUCE5 PORT MAP (A,B,S2,S3,E,D(12));
M14:AND_REDUCE5 PORT MAP (S0,B,S2,S3,E,D(13));
M15:AND_REDUCE5 PORT MAP (A,S1,S2,S3,E,D(14));
M16:AND_REDUCE5 PORT MAP (S0,S1,S2,S3,E,D(15));
END RTL;
STRUCTURAL CODE FOR THE 16 32 BIT REGISTER FILE
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY REGISTERFILE IS
PORT( ADDR0:IN STD_LOGIC;
ADDR1:IN STD_LOGIC;
ADDR2:IN STD_LOGIC;
ADDR3:IN STD_LOGIC;
WRITE_DATA:IN STD_LOGIC_VECTOR(31 DOWNTO 0);
WRITENB:IN STD_LOGIC;
WRITER15:IN STD_LOGIC_VECTOR(31 DOWNTO 0);
RSEL1,RSEL2,RSEL3,RSEL4:IN STD_LOGIC_VECTOR(3 DOWNTO 0);
DATARN:OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
DATARSRD:OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
DATARMR15:OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
READR15:OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
CLK:IN STD_LOGIC
);
END;
ARCHITECTURE RTL OF REGISTERFILE IS
SIGNAL I0,I1,I2,I3,I4,I5,I6,I7,I8,I9,I10,I11,I12,I13,I14,I15:STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL P0,P1,P2,P3,P4,P5,P6,P7,P8,P9,P10,P11,P12,P13,P14,P15:STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL ENB:STD_LOGIC;
SIGNAL D:STD_LOGIC_VECTOR(15 DOWNTO 0);
COMPONENT DFF_ENABLE IS
PORT(DIN:IN STD_LOGIC;
ENB:IN STD_LOGIC;
CLK:IN STD_LOGIC;
Q,QBAR:OUT STD_LOGIC
);
END COMPONENT;
COMPONENT DECODER IS
PORT(S0,S1,S2,S3 :IN STD_LOGIC;
EN:IN STD_LOGIC;
D:OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
);
END COMPONENT;
COMPONENT REG_32BIT IS
PORT(I:IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ENB:IN STD_LOGIC;
CLK:IN STD_LOGIC;
O:OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
OBAR:OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT;
COMPONENT MUX32_16_TO_1 IS
PORT ( A: in STD_LOGIC_VECTOR(31 downto 0);
B: in STD_LOGIC_VECTOR(31 downto 0);
C: in STD_LOGIC_VECTOR(31 downto 0);
D: in STD_LOGIC_VECTOR(31 downto 0);
E: in STD_LOGIC_VECTOR(31 downto 0);
F: in STD_LOGIC_VECTOR(31 downto 0);
G: in STD_LOGIC_VECTOR(31 downto 0);
H: in STD_LOGIC_VECTOR(31 downto 0);
I: in STD_LOGIC_VECTOR(31 downto 0);
J: in STD_LOGIC_VECTOR(31 downto 0);
K: in STD_LOGIC_VECTOR(31 downto 0);
L: in STD_LOGIC_VECTOR(31 downto 0);
M: in STD_LOGIC_VECTOR(31 downto 0);
N: in STD_LOGIC_VECTOR(31 downto 0);
O: in STD_LOGIC_VECTOR(31 downto 0);
P: in STD_LOGIC_VECTOR(31 downto 0);
RSEL:IN STD_LOGIC_VECTOR(3 DOWNTO 0);
ROUT:OUT STD_LOGIC_VECTOR(31 downto 0)
);
END COMPONENT;
COMPONENT NOT2 IS
PORT(A:IN STD_LOGIC;
C :OUT STD_LOGIC
);
END COMPONENT;
BEGIN
N01:NOT2 PORT MAP(WRITENB,ENB);
D01:DECODER PORT MAP(ADDR0,ADDR1,ADDR2,ADDR3,WRITENB,D);
R00:REG_32BIT PORT MAP(WRITE_DATA,D(0),CLK,I0,P0);
R01:REG_32BIT PORT MAP(WRITE_DATA,D(1),CLK,I1,P1);
R02:REG_32BIT PORT MAP(WRITE_DATA,D(2),CLK,I2,P2);
R03:REG_32BIT PORT MAP(WRITE_DATA,D(3),CLK,I3,P3);
R04:REG_32BIT PORT MAP(WRITE_DATA,D(4),CLK,I4,P4);
R05:REG_32BIT PORT MAP(WRITE_DATA,D(5),CLK,I5,P5);
R06:REG_32BIT PORT MAP(WRITE_DATA,D(6),CLK,I6,P6);
R07:REG_32BIT PORT MAP(WRITE_DATA,D(7),CLK,I7,P7);
R08:REG_32BIT PORT MAP(WRITE_DATA,D(8),CLK,I8,P8);
R09:REG_32BIT PORT MAP(WRITE_DATA,D(9),CLK,I9,P9);
R10:REG_32BIT PORT MAP(WRITE_DATA,D(10),CLK,I10,P10);
R11:REG_32BIT PORT MAP(WRITE_DATA,D(11),CLK,I11,P11);
R12:REG_32BIT PORT MAP(WRITE_DATA,D(12),CLK,I12,P12);
R13:REG_32BIT PORT MAP(WRITE_DATA,D(13),CLK,I13,P13);
R14:REG_32BIT PORT MAP(WRITE_DATA,D(14),CLK,I14,P14);
R15:REG_32BIT PORT MAP(WRITER15,ENB,CLK,I15,P15);
M01:MUX32_16_TO_1 PORT MAP(I0,I1,I2,I3,I4,I5,I6,I7,I8,I9,I10,I11,I12,I13,I14,I15,RSEL1,DATARN);
M02:MUX32_16_TO_1 PORT MAP(I0,I1,I2,I3,I4,I5,I6,I7,I8,I9,I10,I11,I12,I13,I14,I15,RSEL2,DATARSRD);
M03:MUX32_16_TO_1 PORT MAP(I0,I1,I2,I3,I4,I5,I6,I7,I8,I9,I10,I11,I12,I13,I14,I15,RSEL3,DATARMR15);
M04:MUX32_16_TO_1 PORT MAP(I0,I1,I2,I3,I4,I5,I6,I7,I8,I9,I10,I11,I12,I13,I14,I15,RSEL4,READR15);
END RTL;