rf2ttc review may 2006

Sophie BARON, PH-ESS TTC meeting, 2nd of May 2006 1

RF2TTC Review May 2006

text

text

FPGA

MAIN BC CLOCK

BC2 CLOCK

BC1 CLOCK

text

VME BACKPLANE

FROM RF OPTICALRECEIVERS

INTERNAL CLOCK

Sine2Square

PhaseAdjust

Sine2Square

Sine2Square

PLL&VCXO

PLL&VCXO

ECL Driver

Sine2Square

Sine2Square

Stretcher

Stretcher

FineDelay

FineDelay

PLL&VCXO

BC1

BC2

BC ref

PECL2NIM

PLL&VCXO

PhaseAdjust

PhaseAdjust

PhaseAdjust

ORBIT1

ORBIT2

VME BUS

MUX2:1

MUX2:1

MUX2:1

FAN1:4

FAN1:4

INTERNALCNT

ECL Driver

ECL2NIM

CoarseDelay

MAIN BC

I2C interface

BC1 ECL/OUT

BC1 NIM/OUT

BC2 ECL/OUT

BC2 NIM/OUT

BCrefECL/OUT

BCrefNIM/OUT

MAIN BCECL/OUT

MAIN BCNIM/OUT

ORBIT1NECL/OUT

ORBIT1NIM/OUT

ORBIT2NECL/OUT

ORBIT2NIM/OUT

MAIN ORBITNECL/OUT

MAIN ORBITNIM/OUT

Sine pulse1V peak (0-1V)

5ns width

Sinusoidal frequencies40.07XX MHz

varying0.6V pk-pk /8

or 0.6V pk-pk (CMS)

Sinusoidal frequency40.07XX MHz

fixed0.6V pk-pk / 8

or 0.6V pk-pk (CMS)

5nssquarepulse

40 ns LVPECL

ECLcomparator

AD96685

DELAY25

QPLL

BC & ORBIT SOURCESSELECTION, DACsadjustment for Orbit

comparators

BST decoder

VME INTERFACE

BSTSIGNAL

OPTICALTTC

FRAMES

MACHINE MODES

RE

MO

TE

CO

NT

RO

L

S1

S4

D

C2C1 ENB

Multiplexer

MACHINE MODES

FIN

E D

EL

AY

S C

ON

TR

OL

MAIN BC

INTERNALCLOCK

INTERNALCLOCK

TTCrx

BC1 lock

BC2 lock

BCref lock

MAIN BC lock

BCsel[1..0]

BOARD STATUS

Lock, TTCready, ...

Orbit sel

Orbit sel

BC1 lockBC2 lock

BCref lockMAIN BC lock

Orbit1Orbit2

Machine Mode Run/No

VME accessVME_Berr

BST_ready

MAIN BC int/BC1BC2/Bcref

MAIN ORBIT Or1/Or2/Int

STATUS REGISTERS

BC1sel

BC2sel

BCref sel

I2C

Orbitdetect

Orbitdetect

Orb2 det

MAIN BCsel[1..0]

RF2TTC BOARDBLOCK DIAGRAM V1.7

28/04/2006

LVPECL2LVDS

LVPECL2LVDS

LVPECL2LVDS

LVDS2ECL

LVDS2ECL

LVDS2ECL

DELAY25

DELAY25

DELAY25

QPLLMUX4:1

LVPECL2LVDS

Adjust.Stretch

er

2.5VCMOS

2.5VCMOS

2.5VCMOS

2.5VCMOS

DiffNECL

LVDS

LVDS

LVDS

LVDS

Orb1 det

Step 500ps, range 25ns

LVPECL QUARTZ80.158MHz

DiffNECL

DiffNECL

ACCOUPLING

ACCOUPLING

ACCOUPLING

Diff LVPECL

Diff LVPECL

Diff LVPECL

Diff LVPECL

ACCOUPLING

Diff LVPECL

CAPACITIVECOUPLING +THEVENIN

TERMINATION FORDC LEVEL OF 1.2V

Diff LVPECL

Diff LVPECL

Diff LVPECL

Diff LVPECL

LVDS800mV swing

LVDS800mV swing

LVDS800mV swing

LVDS800mV swing

LVDS

LVDS

LVDS

LVDS

MC10EP89 ECLcoax cable

drivers

ECL2NIMCONVERSION

USING BSR17ATRANSISTORS

74AHC123

PECL

PECL

PECL

PECL

DACs& Ref

Voltage

V_comp5

5nssquarepulse

40 ns LVPECL

ECL2NIMCONVERSION


v

Q

QSET

CLR

D

Sync

Q

QSET

CLR

D

Sync

FineDelay

FineDelay

FineDelay

S1

S4

D

C2C1 ENB

Multiplexer

CoarseDelay

Adjust.Stretch

er

S1

S4

D

C2C1 ENB

Multiplexer

Q

QSET

CLR

D

Sync

INTERNALCNT

Q

QSET

CLR

D

Sync

INTERNALCNT

CoarseDelay

Adjust.Stretch

er

PLL&VCXO

ECLcomparator

AD96685

V_comp3

V_comp1

V_comp4

V_comp2

FAN1:4

LVDS2ECL

BC1_CLOCK

FAN1:4

LVDS2ECL

BC2_CLOCK

FAN1:4

LVDS2ECL

BCref_CLOCK


driversBC1_clock

BC2_clock

LVDS2ECL

NECL

ECL Driver

PECL2NIM

ECL Driver

PECL2NIM

ECL Driver

PECL2NIM

ECL Driver

ECL2NIM

ECL Driver

ECL2NIM


Receiver Crate Functionalities Design AOB


RECEIVER CRATE [Overview]


RECEIVER CRATE [Location]

TTClab (build 4)

Magnetic field: <100gaussRadiations:Total dose: 1.4 rad/10yrsCh Hadrons >20MeV fluency: 1.5 106/10yrs/cm-2

Neutrons>20MeV: 3.1 106/10yrs/cm-2


RECEIVER CRATE [Crates]

ATLAS, CMS, LHCb:o 1 LHC standard 6U VME crate per experiment

o Power supply type OP06.0710 (+3.3V/100A, +5V/100A, +-12V/10A, 48V/12A)

ALICE:o 1 ALICE Trigger standard 6U VME crate (water cooled)

o Power supply type changed from 0P17.0711 to 0P17.0701 (+3.3V/100A, +5V/100A, +/-12V/10A)

TTC lab:o 1 LHC standard 6U VME crate per experiment

o Power supply type OP06.0710 (+3.3V/100A, +5V/100A, +-12V/10A, 48V/12A)

RF:o Use VME64 crates (no P3V3).

RF2TTC and fanout modules use +3V3, +5V and +-12V RF_Tx and RF_Rx use only +5V and +-12V


RECEIVER CRATE [Crate Controllers]

ALICE:o Standard VP315/317 from CCT

ATLAS:o Standard VP110 from CCT

CMS:o CAEN PCI-controller card A2818 + V2718 VME-PCI optical bridge

LHCb:o CAEN V1718 VME-USB bridge

All these modules are POOL items. One of each will be reserved as from August 06.

The TTClab is equipped with a VP110.


RECEIVER CRATE [RF Analog Links]

Analog Modules o Transmitter module: RF_Tx_A (EDA-01331)o Receiver module: RF_Rx_A (EDA-

01332)

Miteq links validated• Specs:

– Freq max: 3GHz (typ)– Vin: 10dBm (max)– Vout: 10dBm (max)

• Measured Phase Noise:– 400MHz -> 0.4ps (pkpk)– 40MHz -> 0.4ps (pkpk)– 10MHz -> 13ps (pkpk)More results in the evaluation report

• Typical output levels:– Bunch Clock = 0dBm continuous sinewave– Orbit = 1Vpk pulse on 50 Ohms

• Quantities:– 10 links have been ordered in November05– 10 to be ordered soon=> Enough to work until 2007



6U 4TE VME (VME 64x and VME 64 compatible)o 3 internal registers

• Power warning led threshold (RW)• CH1Power monitoring (Read Only)• CH2 Power monitoring (Read Only)

o Manual or geographical addresses

o Emi Filters on each laser power pin

o FPGA programmed using VHDL/ Visual Elite to match the AB/RF requirements

o Heat sink required to keep the Miteq Rx and Tx at about 35 C Deg.



Power consumption:+5V +12V -12V

Tx 0.7A 0.7A 0.2A

Rx 0.7A 0.7A 0

Component price/ dual moduleMITEQ Others Total

Tx 3174 178 6 527 CHF

Rx 5079 190 10 348 CHF

•Some layout changes on-going following the review done with AB/RF•PCB manufacture to begin this week


RECEIVER CRATE [RF Digital Links]

Digital Modules (RF_Tx_D and RF_Rx_D)o First test boards made with PHOTON 155Mbps/TRR-1B43 pair

• Performance evaluated on the same setup than the analog links• Results available in the test report• AB/RF agreed that this could be a cheaper solution for 70% of the links, including

the TTC• If the final results are as good as expected, they will use this solution for these 70%

and maintain the boards the same way.

o Optical components identified and ordered• Photon getting obsolete• AMS components pin compatible components• Price:

– Orbit, 10MHz, 40MHz: 156Mbps links

– 400MHz: 1.2Gbps

o Design on-going (PH/ESS). • Close to the analog boards, but higher density.

Tx Rx

156Mbps PHOTON 197 97

156Mbps AMS 313 227

1.2Gbps AMS 635 295


RECEIVER CRATE [Client modules]

Custom modules:o ATLAS CTPo TTCcio ..

Standard TTC modules:

Coupling Termination

TTCex

BC in AC 50 to vbb

A in DC NECL120/82 (=-2.1VDC)

B in DC NECL120/82 (=-2.1VDC)

BC out AC 120/82 (=-2.1VDC)

TTCvi

L1a_in AC 240/62 (=-1.1VDC)

BC_in AC 240/62 (=-1.1VDC)

Orbit_in AC 240/62 (=-1.1VDC)

ECL_out DC NECL 560 to -5V2

TTCvx

BC in AC 240/62 (=-1.1VDC)

A_in DC NECL120/82 (=-2.1VDC)

B_in DC NECL120/82 (=-2.1VDC)

TTCClkGen

BC_in AC 120/82 (=-2.1VDC)

BC_out AC 120/82 (=-2.1VDC)

TTCFanout

Sig_in AC 120/82 (=-2.1VDC)

Sig_out AC 150 to GND (PECL)

To have a full compatibility with all the client modules, •The BC_out signals can be ECL AC coupled•The Orbit_out signals need to be NECL DC coupled


RECEIVER CRATE [TTC Clock fanout]

TTC Clock fanout (EDA-01240-V1, PH/MIC) o Dual 1:18 ECL fanouto 4 NIM outputs per input (ALICE requirement)o 1 status led per input (presence of clock). o Maximum densityo The 2 dual modules can be daisy chained.o Fully AC coupled

Prototype produced

Power: 5V-5A, Jitter: In/Out skew=8ps rms, Cy2Cy=11ps rms Skew between outputs: a few ps

Design needs to be adjusted to be ‘orbit-compliant’ (AC -> DC coupling)


BC ring1

BC ring2

BC REF

BC INPUTS

Orb ring1

Orb ring2

ORBIT INPUTS

BC OUTPUTS

ORBIT OUTPUTS

BC1/ecl BC1/nim

BC2/ecl BC2/nim

BC/ecl BC/nim

Or1/ecl Or1/nim

Or2/ecl Or2/nim

VMEBC1 lockBC2 lockBCref lockOrbit1Orbit2

Or2/ecl Or2/nim

BC/ecl BC/nim

MAIN

MAIN

RF2TTC

1 2 Ref IntBC

BST

Orb

LHC Mode

FUNCTIONALITIES [Inputs/Outputs]

VME 6U module 1 slot if possible Inputs

o 3 BC inputs (SMA or Lemo00) (RF signals)o 2 Orbit inputs (RF signals)o 1 Optical input for the BST signals

Outputs (can be discussed)o 4 ECL BC outputs (BC1, BC2, BCref, MainBC)

• AC coupled

o 4 NIM copieso 3 NECL Orbit outputs (Orb1, Orb2, MainOrb)

• DC coupled• Synchronised respectively to BC1, BC2, MainBC

o 3 NIM copies Status leds


text

text

FPGA

MAIN BC CLOCK

BC2 CLOCK

BC1 CLOCK

text

VME BACKPLANE


INTERNAL CLOCK

Sine2Square

PhaseAdjust

Sine2Square

Sine2Square

PLL&VCXO

PLL&VCXO

ECL Driver

Sine2Square

Sine2Square

Stretcher

Stretcher

FineDelay

FineDelay

PLL&VCXO

BC1

BC2

BC ref

PECL2NIM

PLL&VCXO

PhaseAdjust

PhaseAdjust

PhaseAdjust

ORBIT1

ORBIT2

VME BUS

MUX2:1

MUX2:1

MUX2:1

FAN1:4

FAN1:4

INTERNALCNT

ECL Driver

ECL2NIM

CoarseDelay

MAIN BC

I2C interface

BC1 ECL/OUT

BC1 NIM/OUT

BC2 ECL/OUT

BC2 NIM/OUT

BCrefECL/OUT

BCrefNIM/OUT

MAIN BCECL/OUT

MAIN BCNIM/OUT

ORBIT1NECL/OUT

ORBIT1NIM/OUT

ORBIT2NECL/OUT

ORBIT2NIM/OUT

MAIN ORBITNECL/OUT

MAIN ORBITNIM/OUT


5ns width



or 0.6V pk-pk (CMS)


fixed0.6V pk-pk / 8

or 0.6V pk-pk (CMS)

5nssquarepulse

40 ns LVPECL

ECLcomparator

AD96685

DELAY25

QPLL


comparators

BST decoder

VME INTERFACE

BSTSIGNAL

OPTICALTTC

FRAMES

MACHINE MODES

RE

MO

TE

CO

NT

RO

L

S1

S4

D

C2C1 ENB

Multiplexer

MACHINE MODES

FIN

E D

EL

AY

S C

ON

TR

OL

MAIN BC

INTERNALCLOCK

INTERNALCLOCK

TTCrx

BC1 lock

BC2 lock

BCref lock

MAIN BC lock

BCsel[1..0]

BOARD STATUS

Lock, TTCready, ...

Orbit sel

Orbit sel

BC1 lockBC2 lock


Orbit1Orbit2

Machine Mode Run/No

VME accessVME_Berr

BST_ready



STATUS REGISTERS

BC1sel

BC2sel

BCref sel

I2C

Orbitdetect

Orbitdetect

Orb2 det

MAIN BCsel[1..0]


28/04/2006

LVPECL2LVDS

LVPECL2LVDS

LVPECL2LVDS

LVDS2ECL

LVDS2ECL

LVDS2ECL

DELAY25

DELAY25

DELAY25

QPLLMUX4:1

LVPECL2LVDS

Adjust.Stretch

er

2.5VCMOS

2.5VCMOS

2.5VCMOS

2.5VCMOS

DiffNECL

LVDS

LVDS

LVDS

LVDS

Orb1 det



DiffNECL

DiffNECL

ACCOUPLING

ACCOUPLING

ACCOUPLING

Diff LVPECL

Diff LVPECL

Diff LVPECL

Diff LVPECL

ACCOUPLING

Diff LVPECL



Diff LVPECL

Diff LVPECL

Diff LVPECL

Diff LVPECL

LVDS800mV swing

LVDS800mV swing

LVDS800mV swing

LVDS800mV swing

LVDS

LVDS

LVDS

LVDS


drivers

ECL2NIMCONVERSION


74AHC123

PECL

PECL

PECL

PECL

DACs& Ref

Voltage

V_comp5

5nssquarepulse

40 ns LVPECL

ECL2NIMCONVERSION


v

Q

QSET

CLR

D

Sync

Q

QSET

CLR

D

Sync

FineDelay

FineDelay

FineDelay

S1

S4

D

C2C1 ENB

Multiplexer

CoarseDelay

Adjust.Stretch

er

S1

S4

D

C2C1 ENB

Multiplexer

Q

QSET

CLR

D

Sync

INTERNALCNT

Q

QSET

CLR

D

Sync

INTERNALCNT

CoarseDelay

Adjust.Stretch

er

PLL&VCXO

ECLcomparator

AD96685

V_comp3

V_comp1

V_comp4

V_comp2

FAN1:4

LVDS2ECL

BC1_CLOCK

FAN1:4

LVDS2ECL

BC2_CLOCK

FAN1:4

LVDS2ECL

BCref_CLOCK


driversBC1_clock

BC2_clock

LVDS2ECL

NECL

ECL Driver

PECL2NIM

ECL Driver

PECL2NIM

ECL Driver

PECL2NIM

ECL Driver

ECL2NIM

ECL Driver

ECL2NIM

FUNCTIONALITIES [Block Diagram]

Adjustable

Reset possible

Monitored via a VME register

Status Led


FUNCTIONALITIES [VME Interface]

VME Interfaceo D32/A32 access mode (AM 0x09)o 8 bits of board address (A31-A24) (2 rotary switches). o Geographical addresses usable if the manual address is 0x00

(reloaded at power up or by sysreset)o Interrupts are possible, but have to remain optional. They may not be

handled by every types of VME controllers.


FUNCTIONALITIES [Signal Adjustments]

Adjustable parameters (via VME registers)o BC1, BC2, BCref

• Adjustable level on the comparator input• Multiplexing between each input and the internal 40.078MHz clock• Adjustable phase shift (steps of 0.5ns)

o Main BC• Multiplexing between BC1, BC2, BCref and internal clock• Adjustable phase shift (steps of 0.5ns)

o Orbit1 and Orbit2• Adjustable level on the comparator input to match various types of signals• Adjustable phase shift before the latching with the corresponding BC• Multiplexing between each input and an internal counter• Adjustable length• Adjustable coarse delay (steps of 25ns)• Adjustable phase shift (steps of 0.5ns) before the output

o Main Orbit• Multiplexing between the two orbit sources and an internal counter• Adjustable length• Adjustable coarse delay (steps of 25ns)• Adjustable phase shift (steps of 0.5ns) before the output


FUNCTIONALITIES [Status & Remote Control]

Board status datao Read only registers: Orbit available, QPLL lock, TTC ready, machine

modeo Leds: selected signals, QPLL lock, available orbit, VME access, VME

berr, BST signal ready...

Remote control of the adjustmentso Orbit comparator level/ orbit dephasing: FIFO containing the 128 last

BC counts between two consecutive Orbit signals (ideally 3564 each). The content of this FIFO can indicate a bad level on the comparator, a dephasing, a wrong synchronisation. This FIFO is filled at reception of a VME command.

o Clock status: QPLL status indicates if the clock is absent or if the comparator level is wrong. Would some other ways being required?

o Orbit counter, 32 bits (106 hours). Could be reset, either manually, or at the beginning of a run if required


FUNCTIONALITIES [Working modes]

Manual and automatic modes for signal selectiono Manual mode: the source of each output signal is manually selectedo Automatic mode:

• Change the selected sources according to the machine mode• 2 types of parameters must be configured:

– Which machine mode is considered to be ‘run’ (ex: ramping, adjust, collide..) or ‘no run’ (beam dump, no beam, …)

– Which source for each signal must be selected during ‘run’ or ‘no run’. Example for the Main BC: Internal clock during ‘no run’ periods, and BCref during run periods

• 3 different configurations can be defined for the signal selection.

o Which means: • 1 register to define in which mode we are (manual, auto1, auto2, auto3)• 1 register to define which machine mode corresponds to which state• 1 register to define the sources set when ‘no run’…………………• 3 registers to define the sources set when ‘run’ (1 per auto mode)…

timeinjection~15 min

ramping~28 min

squeeze~15 min

physics~10-20 H

Beam Dump

E(45

0GeV

->

7TeV

)

Beam Dump

E(45

0GeV

->

7TeV

)

Run/no run

Automode1Automode2Automode3


FUNCTIONALITIES [State Machine]

timeinjection~15 min

ramping~28 min

squeeze~15 min

physics~10-20 H

Beam Dump

E(45

0GeV

->

7T

eV)

Beam Dump

E(45

0GeV

->

7T

eV)

Run/no run

Automode1Automode2Automode3

Manual

AUTO MODE

NO RUN[no_run]

MANUAL

RUN[auto1]

RUN[auto2]

RUN[auto3]


FUNCTIONALITIES [register map -1]

Bunch Clocks registers

BC#

BC1_COMP_Vref R/W 8 bits Voltage reference to be compared to the BC1 input

BC1_QPLL_STATUS R 2 bits Locked, error

BC1_QPLL_MODE R/W 1 bit autorestart or manual restart mode

BC1_FINE_DELAY R/W 7 bits enable the line, and delay adjustment (steps of 0.5ps)

BC1_SOURCE_SEL R/W 1 bitBC source can be chosen between the internal 40.078MHz and the LHC BC1 when the selection mode is

manual

BC1_RESERVED_# R/W 16 bits

MainBC

MainBC_QPLL_STATUS R Locked, error

MainBC_QPLL_MODE R/W 1 bit autorestart or manual restart mode

MainBC_FINE_DELAY R/W 7 bits enable the line, and delay adjustment (steps of 0.5ps)

MainBC_SOURCE_SEL R/W 2 bitsMainBC source can be chosen between the internal 40.078MHz and the LHC

BC1, BC2 and BCref

MainBC_RESERVED_# R/W 16 bits



ORBIT#

Orb1_COMP_Vref R/W 8 bits set the threshold value used to latch the Orb signal

Orb1_SOURCE_SEL R/W 1 bit Orb1 source can be chosen between the Orb1 Internal counter and the LHC

Orb1

Orb1_DETECTED R 1 bit shows if the orbit signal is available

Orb1_DETECTED_PERIOD R 12 bits

Each read access gives the last number of BCs between 2 Orbit signals stored in a 128 words FIFO (to check the Orbit dephasing). The 4 upper bits give the status of the fifo when the word is read (full, empty, almost full..)

Orb1_FINE_IN_DELAY R/W 7 bitsenable the line, and delay adjustment (steps of 0.5ps) to adjust the phase of the

input signal vs the latching BC

Orb1_COARSE_DELAY R/W 12 bits delay adjustment of the Orbit signal in 3564 steps of 25ns (0 to 88.924us)

Orb1_WIDTH R/W 12 bits orbit pulse width adjustment in 3564 steps of 25ns (0 to 88.924us)

Orb1_FINE_OUT_DELAY R/W 7 bitsenable the line, and delay adjustment (steps of 0.5ps) to adjust the phase of the

output signal vs the BC used by the experiments

Orb1_Int_PERIOD R/W 12 bits set the period of the internal orbit (from 0 to 102us in steps of 25ns, sync to BC1)

Orb1_Int_COUNTER R 12 bitsResult of the Orbit1_int counter (counts the BC between 2 orbits). Reset by each

new orbit.

Orb1_COUNTER R 32 bitsResult of the Orbit1 counter (counts the Orbit signal, up to 106 hours). Manually

reset or by the beginning of a run ? (how?)

Orb1_RESERVED_# R/W 16 bits

Orbit registers



MainORBIT

MainOrb_SOURCE_SEL R/W 2 bits MainOrb source can be chosen between the internal MainOrb counter,

the LHC Orb1 and the LHC orb2

MainOrb_COARSE_DELAY R/W 12 bitsdelay adjustment of the Orbit signal in 3564 steps of 25ns (0 to

88.924us)

MainOrb_WIDTH R/W 12 bits orbit pulse width adjustment in 3564 steps of 25ns (0 to 88.924us)

MainOrb_FINE_OUT_DELAY R/W 7 bitsenable the line, and delay adjustment (steps of 0.5ps) to adjust the

phase of the output signal vs the BC used by the experiments

MainOrb_Int_PERIOD R/W 12 bitsset the period of the internal orbit (from 0 to 102us in steps of 25ns,

sync to MainBC)

MainOrb_Int_COUNTER R 12 bitsResult of the MainOrbit_int counter (counts the BC between 2 orbits).

Reset by each new orbit.

MainOrb_COUNTER 32 bitsResult of the MainOrbit counter (counts the Orbit signal, up to 106

hours). Manually reset or by the beginning of a run ? (how?)

MainOrb_RESERVED_# R/W 16 bits

Orbit registers



TTCrx

TTCrx_CONFIG1 R/W

TTCrx_CONFIG2 R/W

TTCrx_CONFIG3 R/W

TTCrx_STATUS R

TTCrx_RESERVED_1 R/W 16 bits

BST MESSAGE

MACHINE_MODE R 8 bits decode the LHC Machine Mode transmitted by the BST

BST _RESERVED_1 R/W 32 bits

BST registers



GENERAL REGISTERS

BOARD ID R/W 8 bits

FIRMWARE VERSION R/W 8 bits

BC_Delay25_GCTRL R/W 8 bits general parameters of the delay 25 chip in charge of all the BC fine delay adjustment

Orb_In_Delay25_GCTRL R/W 8 bits general parameters of the delay 25 chip in charge of all the Orb in fine delay adjustment

Orb_Out_Delay25_GCTRL R/W 8 bits general parameters of the delay 25 chip in charge of all the Orb out fine delay adjustment

Working Modes R/W 4 bits

0: manual mode1: automatic mode 12: automatic mode 23: automatic mode 3

Automatic_config_no_run R/W 9 bitsDescribes the state of the selection of the signals in automatic modes, out of the run periods.

Automatic_config_run_1 R/W 9 bits Describes the state of the selection of the signals in automatic mode 1, during the run.



Machine_states_config R/W 32 bitsOne bit per machine mode. Use automatic_config_0 when bit#=0, use one of the automatic_config1 to 3 when bit#=1.

GNAL_RESERVED_1 R/W 32 bits

General registers



RESET

BC1_QPLL_RESET

BC2_QPLL_RESET

BCref_QPLL_RESET

MainBC_QPLL_RESET

Delay25_RESET

Orb1_counter_fifos_reset

Orb_counters_reset

BOARD_RESET

Commands

COMMANDS

Orb1_fifo_fill trig the filling of the FIFO with the periods of 128 consecutive orbit1 signals

Orb2_fifo_fill trig the filling of the FIFO with the periods of 128 consecutive orbit1 signals

CMD_RESERVED_#


text

text

FPGA

MAIN BC CLOCK

BC2 CLOCK

BC1 CLOCK

text

VME BACKPLANE


INTERNAL CLOCK

Sine2Square

PhaseAdjust

Sine2Square

Sine2Square

PLL&VCXO

PLL&VCXO

ECL Driver

Sine2Square

Sine2Square

Stretcher

Stretcher

FineDelay

FineDelay

PLL&VCXO

BC1

BC2

BC ref

PECL2NIM

PLL&VCXO

PhaseAdjust

PhaseAdjust

PhaseAdjust

ORBIT1

ORBIT2

VME BUS

MUX2:1

MUX2:1

MUX2:1

FAN1:4

FAN1:4

INTERNALCNT

ECL Driver

ECL2NIM

CoarseDelay

MAIN BC

I2C interface

BC1 ECL/OUT

BC1 NIM/OUT

BC2 ECL/OUT

BC2 NIM/OUT

BCrefECL/OUT

BCrefNIM/OUT

MAIN BCECL/OUT

MAIN BCNIM/OUT

ORBIT1NECL/OUT

ORBIT1NIM/OUT

ORBIT2NECL/OUT

ORBIT2NIM/OUT

MAIN ORBITNECL/OUT

MAIN ORBITNIM/OUT


5ns width



or 0.6V pk-pk (CMS)


fixed0.6V pk-pk / 8

or 0.6V pk-pk (CMS)

5nssquarepulse

40 ns LVPECL

ECLcomparator

AD96685

DELAY25

QPLL


comparators

BST decoder

VME INTERFACE

BSTSIGNAL

OPTICALTTC

FRAMES

MACHINE MODES

RE

MO

TE

CO

NT

RO

L

S1

S4

D

C2C1 ENB

Multiplexer

MACHINE MODES

FIN

E D

EL

AY

S C

ON

TR

OL

MAIN BC

INTERNALCLOCK

INTERNALCLOCK

TTCrx

BC1 lock

BC2 lock

BCref lock

MAIN BC lock

BCsel[1..0]

BOARD STATUS

Lock, TTCready, ...

Orbit sel

Orbit sel

BC1 lockBC2 lock


Orbit1Orbit2

Machine Mode Run/No

VME accessVME_Berr

BST_ready



STATUS REGISTERS

BC1sel

BC2sel

BCref sel

I2C

Orbitdetect

Orbitdetect

Orb2 det

MAIN BCsel[1..0]


28/04/2006

LVPECL2LVDS

LVPECL2LVDS

LVPECL2LVDS

ECL2LVDS

ECL2LVDS

CMOS2ECL

CMOS2ECL

CMOS2ECL

DELAY25

DELAY25

DELAY25

QPLLMUX4:1

LVPECL2LVDS

Adjust.Stretch

er

CMOS

CMOS

LVDS

LVDS

DiffNECL

LVDS

LVDS

LVDS

LVDS

Orb1 det



DiffNECL

DiffNECL

ACCOUPLING

ACCOUPLING

ACCOUPLING

Diff LVPECL

Diff LVPECL

Diff LVPECL

Diff LVPECL

ACCOUPLING

Diff LVPECL



Diff LVPECL

Diff LVPECL

Diff LVPECL

Diff LVPECL

LVDS800mV swing

LVDS800mV swing

LVDS800mV swing

LVDS800mV swing

LVDS

LVDS

LVDS

LVDS


drivers

ECL2NIMCONVERSION


74AHC123

PECL

PECL

PECL

PECL

DACs& Ref

Voltage

V_comp5

5nssquarepulse

40 ns LVPECL

ECL2NIMCONVERSION


v

Q

QSET

CLR

D

Sync

Q

QSET

CLR

D

Sync

FineDelay

FineDelay

FineDelay

S1

S4

D

C2C1 ENB

Multiplexer

CoarseDelay

Adjust.Stretch

er

S1

S4

D

C2C1 ENB

Multiplexer

Q

QSET

CLR

D

Sync

INTERNALCNT

Q

QSET

CLR

D

Sync

INTERNALCNT

CoarseDelay

Adjust.Stretch

er

PLL&VCXO

ECLcomparator

AD96685

V_comp3

V_comp1

V_comp4

V_comp2

FAN1:4

LVDS2ECL

BC1_CLOCK

FAN1:4

LVDS2ECL

BC2_CLOCK

FAN1:4

LVDS2ECL

BCref_CLOCK


driversBC1_clock

BC2_clock

LVDS2ECL

NECL

ECL Driver

PECL2NIM

ECL Driver

PECL2NIM

ECL Driver

PECL2NIM

ECL Driver

ECL2NIM

ECL Driver

ECL2NIM

DESIGN [Block Diagram]


DESIGN [Technology choices]

ECL/LVDS components LVDS 2 ECL conversion application note

text

text

FPGA

MAIN BC CLOCK

BC2 CLOCK

BC1 CLOCK

text

VME BACKPLANE


INTERNAL CLOCK

Sine2Square

PhaseAdjust

Sine2Square

Sine2Square

PLL&VCXO

PLL&VCXO

ECL Driver

Sine2Square

Sine2Square

Stretcher

Stretcher

FineDelay

FineDelay

PLL&VCXO

BC1

BC2

BC ref

PECL2NIM

PLL&VCXO

PhaseAdjust

PhaseAdjust

PhaseAdjust

ORBIT1

ORBIT2

VME BUS

MUX2:1

MUX2:1

MUX2:1

FAN1:4

FAN1:4

INTERNALCNT

ECL Driver

ECL2NIM

CoarseDelay

MAIN BC

I2C interface

BC1 ECL/OUT

BC1 NIM/OUT

BC2 ECL/OUT

BC2 NIM/OUT

BCrefECL/OUT

BCrefNIM/OUT

MAIN BCECL/OUT

MAIN BCNIM/OUT

ORBIT1NECL/OUT

ORBIT1NIM/OUT

ORBIT2NECL/OUT

ORBIT2NIM/OUT

MAIN ORBITNECL/OUT

MAIN ORBITNIM/OUT


5ns width



or 0.6V pk-pk (CMS)


fixed0.6V pk-pk / 8

or 0.6V pk-pk (CMS)

5nssquarepulse

40 ns LVPECL

ECLcomparator

AD96685

DELAY25

QPLL


comparators

BST decoder

VME INTERFACE

BSTSIGNAL

OPTICALTTC

FRAMES

MACHINE MODES

RE

MO

TE

CO

NT

RO

L

S1

S4

D

C2C1 ENB

Multiplexer

MACHINE MODES

FIN

E D

EL

AY

S C

ON

TR

OL

MAIN BC

INTERNALCLOCK

INTERNALCLOCK

TTCrx

BC1 lock

BC2 lock

BCref lock

MAIN BC lock

BCsel[1..0]

BOARD STATUS

Lock, TTCready, ...

Orbit sel

Orbit sel

BC1 lockBC2 lock


Orbit1Orbit2

Machine Mode Run/No

VME accessVME_Berr

BST_ready



STATUS REGISTERS

BC1sel

BC2sel

BCref sel

I2C

Orbitdetect

Orbitdetect

Orb2 det

MAIN BCsel[1..0]


28/04/2006

LVPECL2LVDS

LVPECL2LVDS

LVPECL2LVDS

LVDS2ECL

LVDS2ECL

LVDS2ECL

DELAY25

DELAY25

DELAY25

QPLLMUX4:1

LVPECL2LVDS

Adjust.Stretch

er

2.5VCMOS

2.5VCMOS

2.5VCMOS

2.5VCMOS

DiffNECL

LVDS

LVDS

LVDS

LVDS

Orb1 det



DiffNECL

DiffNECL

ACCOUPLING

ACCOUPLING

ACCOUPLING

Diff LVPECL

Diff LVPECL

Diff LVPECL

Diff LVPECL

ACCOUPLING

Diff LVPECL



Diff LVPECL

Diff LVPECL

Diff LVPECL

Diff LVPECL

LVDS800mV swing

LVDS800mV swing

LVDS800mV swing

LVDS800mV swing

LVDS

LVDS

LVDS

LVDS


drivers

ECL2NIMCONVERSION


74AHC123

PECL

PECL

PECL

PECL

DACs& Ref

Voltage

V_comp5

5nssquarepulse

40 ns LVPECL

ECL2NIMCONVERSION


v

Q

QSET

CLR

D

Sync

Q

QSET

CLR

D

Sync

FineDelay

FineDelay

FineDelay

S1

S4

D

C2C1 ENB

Multiplexer

CoarseDelay

Adjust.Stretch

er

S1

S4

D

C2C1 ENB

Multiplexer

Q

QSET

CLR

D

Sync

INTERNALCNT

Q

QSET

CLR

D

Sync

INTERNALCNT

CoarseDelay

Adjust.Stretch

er

PLL&VCXO

ECLcomparator

AD96685

V_comp3

V_comp1

V_comp4

V_comp2

FAN1:4

LVDS2ECL

BC1_CLOCK

FAN1:4

LVDS2ECL

BC2_CLOCK

FAN1:4

LVDS2ECL

BCref_CLOCK


driversBC1_clock

BC2_clock

LVDS2ECL

NECL

ECL Driver

PECL2NIM

ECL Driver

PECL2NIM

ECL Driver

PECL2NIM

ECL Driver

ECL2NIM

ECL Driver

ECL2NIM

ECL (NECL, PECL, LVPECL)

LVDS (2.5V)

LVCMOS-LVTTL (3.3V)

LVCMOS (2.5V)


DESIGN [Schematics & Features]

See schematics Coupling considerations Conversions

o ECL2LVDSo LVDS2PECLo PECL2NIMo NECL2NIMo ECL2CMOS

BC & Orbit inputso Couplingo Comparator choiceo Voltage reference adjustment

Internal clocko Fixed oscillatoro ECL differential clock lines

Orbit synchronisation processo Pulse lengthening



See schematics Use of CERN ASICS

o Delay25

o QPLL

FPGA o Device choice

o Programming modes

o Signal levels

o Pinout and I/o Banks

o Firmware consideration• VME interface => implemented in the ATLAS TRT-TTC board• Triple logic necessary for critical registers? (working modes, auto_config)

Internal communication busseso I2C

ECL output driverso MC100EL89 coax cable drivers



See schematics Power considerations

o Estimationo Solutions

Debugging facilitieso Test pointso Spare connectoro Signal tap

Bugs to be correctedo Missing pull-up resistors

PCB designo Front Panelo Layout

Prototypingo Price estimation: components about 830 $o Quantitieso Component procuremento Schedules

rf2ttc review may 2006

Documents

pkpksinusoidal frequency40

board statuslock

orb det

0rf2ttc boardblock diagram

pllvc detectvme busfpga40

ttc meeting

rf2ttc review