samsung advanced institute of technology 2nd asian im user group meeting in japan samsung 2001.09.13

SAMSUNG Advanced Institute of Technology

2nd Asian IM User Group Meeting in Japan

SAMSUNG 2001.09.13.


This TRIZ application case was done by researchers of SAIT(Samsung Advanced Institute of Technology),not by TRIZ specialist, although there was help from TRIZ specialist. They had 40 hours TRIZ lesson at company, so they just knew the concept of Contradiction and could use Techoptimizer

As in #9 slide, as soon as they encountered problem, they recognized it as physical contradiction. But with that contradiction expression they could not adopt 4 principles of solving physical contradiction. At that time, TRIZ specialist helped them and converted physical contradiction in another expression : TRIZ specialist thought earlier expression was the result of mental inertial of professional of specific area which had deep relationship with process of manufacturing, dry etching process. As soon as converting physical contradiction, they could solve it by "Separation by Space Principles".

As in #15, 16, the typical process of solving problem could be shown. In generally, although they could solve one problem, frequently, another problem occur after solving one problem. As in this presentation, researchers regarded it as Technical Contradiction. So they used Contradiction Table in Techoptimizer. In this case, they could find exactly the same example of principle named "self-aligned process". Besides solving current loss problem by uniform shape of p-metal, they could additionally remove the most critical and difficult process, so they achieved quantum increase in yield. In this case, some guy could say they are too lucky. But it is the more difficult to deny the powerfulness of contradiction table and Principle module of Techoptimizer.

In summary, from the first case, SAIT TRIZ specialist (Hyo June Kim, Nikolai Shpakovsky) learned the importance of expression of Contradiction and role of mental inertia at expression. From the second case, also learned how to formulate the technical contradiction from typical problem solving process.

Short SummaryShort Summary


6 Process for GaN Laser Diode GaN Laser Diode

Process Mapping

- Selecting

Essential steps

for CTQ

Ridge shape

change by TRIZ

p-metal process

Improvement

by TRIZ

Oxidation Process

optimization

by DOE

Strategy

- Reducing Ith by

Ridge shape change

- Reducing

variance of Ith by

p-metal process

improvement and

optimization of

oxide process

Project definition

- Technology

Roadmap

- Voice of customer

CTQ selecting

- Threshold

Current (Ith)

- Variance of Ith

Property

evaluation

Verification of

variance of Ith

MMeasureeasureDDefineefine AAnalyzenalyze DDesignesign VVerifyerify

<Strategy><Strategy>

- Reducing Ith Ridge shape change TRIZ - Reducing variance of Ith p-metal process improvement TRIZ

- Reducing variance of Ith optimization of oxide process DOE


Group Ith, Jth, Vth Substrate Lasing time Date Issued

Nichia 40mA, 6V ELOG >10,000h ... ... ... ...

Sony 160mA, 9V Sapphire 300h '99 October

Fujitsu 60mA, 8.3V 4H-SiC 57h '99 May

NEC 36mA, 7.5V n:GaN >1h (?) '99 July

SAIT 90mA, 6.7V Sapphire 1.7h '99 November

Xerox 107mA, 6.5V Sapphire 1h (15oC) '99 July

Cree 107mA, 15.7V 6H-SiC < 1m '99 July

Matsushita 440mA, 11.4V Sapphire < 1m '99 July

BeforeBefore TRIZTRIZ in 6 sigma in 6 sigma DD A VM

40 mA, 6V

200mA, 6.7V


Project DefinitionProject Definition

Problem Statement

- Life time of GaN Laser Diode

present : 1.7 hr (at CW 1mW, 20oC)

- Threshold Current (Ith)

present : 200 mA

variance of Ith : 105 mA

Objectives

- Life time of GaN Laser Diode > 1000 hr

- Reducing of Ith : Ith >200 mA → Ith ≤ 50 mA

- Improvement of Ith variance : (Ith) = 105 mA → (Ith)≤ 10 mA

CTQ SelectionCTQ Selection

DD A VM

0 20 40 60 80 1000

100

200

300

Cu

rre

nt(

mA

)

Time(min)

Operating

Current: 140mA

Life time: 1.7 hr

Time (min)Time (min)

Cu

rren

t C

urre

nt

(mA

)(m

A)


Process MappingProcess Mapping

Fabrication ProcessFabrication Process1st. HIGH TEMP. PROCESS

·Activation of GaN wafer

1st. VACUUM DEPO. PROCESS

·Protective layer deposition

1st. DRY ETCHING PROCESS

·Dry etching for ridge formation

2st. DRY ETCHING PROCESS

·Dry etching for mesa formation

2nd. VACUUM DEPO. PROCESS

·Passivation layer deposition

3nd. VACUUM DEPO. PROCESS

·n-metal layer deposition

2nd. HIGH TEMP. PROCESS

·n-metal alloy

4th. VACUUM DEPO. PROCESS

·p-metal layer deposition

3rd. HIGH TEMP. PROCESS

·p-metal alloy


·Bonding metal layer deposition

4th. HIGH TEMP. PROCESS

·Bonding metal alloy


·Mirror coating layer deposition

3rd. DRY ETCHING PROCESS

·Dry etching for pad open

Critical step for CTQ

Ith


variance of Ith


variance of Ith

1

2

3

4

5

6

7

8

9

10

11

12

13

DD A VM


Preparing strategyPreparing strategy

Strategy for each critical process stepStrategy for each critical process step Ith

dry etching for ridge formation

- present : 0.2 m etching depth

from active layer

Variance of Ith

p-metal layer deposition

- present : formation of 1.5 m width

p-metal on the 2 m ridge

passivation layer deposition

- present : BOE time < 40 sec

TRIZTRIZ

TRIZTRIZ

DOEDOE

DD A VM


DD A VMDry Etching for Ridge Formation:TRIZ Dry Etching for Ridge Formation:TRIZ

Initial situation

Device Fabrication Ridge wave guide etching

Facet Etching

Passivation layer deposition

Formation of n-electrode

Formation of p-electrode

Bonding metal & mirror coating

Ridge wave guide part :Critical effect to electricproperty of LD.Especially depending ondepth of ridge.

(0001) Sapphire Substrate

n-GaN

GaN/n-Al0.14 Ga0.86 N

n-GaN

p-Al0.2 Ga0.8N

InGaN/ InGaN MQW

p-GaNGaN/p-Al0.14 Ga0.86 N

p-electrode

n-electrode

SiO2

MD-SLSCladding layer

Ridge wave guide


Problem refinementProblem refinement

Shallow ridge etching depth Current spreading problem

Threshold current Increase

Physical Contradiction :Ridge etching depthmust deep and must not deep

Deep ridge etching depth Optical Loss

Threshold current Increase

Sapphire Substrate


n- GaN

Sapphire Substrate


n- GaN

Optical loss



DD A VM

Solution of ContradictionSolution of Contradiction

Dry Etching for Ridge Formation:TRIZ Dry Etching for Ridge Formation:TRIZ


Separation by TimeSeparation by Space…

Must DeepMust Deep Must Not DeepMust Not Deep


DD A VM




Physical Contradiction :Ridge etching depthmust wide and must not wide

Must WideMust WideMust Not WideMust Not Wide




Physical Contradiction :Ridge etching depthmust wide and must not wide

Principle ofSeparation by Space

Upper part : narrow ridgeUpper part : narrow ridgeprevent current spreadingprevent current spreading

Lower part : wide ridgeLower part : wide ridgeprevent optical lossprevent optical loss


DD A VM




DD A VM

0.0

0.5

1.0

1.5

2.0

0 50 100 150 200 250

Current (mA)

Outp

ut

Pow

er

(mW

)

S a p p h i r e S u b s t r a t e

G a N / n - A l0 .1 4 G a 0 .8 6 N

n - G a N

S a p p h i r e S u b s t r a t e

G a N / n - A l0 .1 4 G a 0 .8 6 N

n - G a N

Previous RidgePrevious RidgeIth > 200 mAIth > 200 mA

Improved RidgeImproved RidgeIth < 50 mAIth < 50 mA

Breakthrough !Breakthrough !

Result



P-metal Layer Deposition : TRIZ P-metal Layer Deposition : TRIZ DD A VM

Initial Situation

Ridge Etching Passivation Contact hole

Sapphire Substrate


n-GaN

Sapphire Substrate


n-GaN

Sapphire Substrate


n-GaN

PR or SiO2

n-GaN

Sapphire Substrate


n-GaN

Narrow P-metal

Ridge

p-metal Passivation

layer

Old structure Old structure of P-metal : of P-metal : Narrow P-metalNarrow P-metal

Demerit :Demerit :1. Not enough removal of 1. Not enough removal of heat generated in GaN.heat generated in GaN.Critical effect to life timeCritical effect to life time

2. Too narrow P-metal2. Too narrow P-metalmake process difficultmake process difficult


P-metal Layer Deposition : TRIZ P-metal Layer Deposition : TRIZ DD A VM

Initial Situation

New structure New structure of P-metal : of P-metal : Wide P-metalWide P-metal

Merit :Merit :Enough removal of Enough removal of heat generated in GaN.heat generated in GaN.Good effect to life timeGood effect to life time

Another problem appear :Another problem appear :Loss of current Loss of current

Typical process ofTypical process ofProblem solving.Problem solving.

Ridge Etching Passivation Contact hole

Sapphire Substrate


n-GaN

Sapphire Substrate


n-GaN

Sapphire Substrate


n-GaN

PR or SiO2

Sapphire Substrate


n-GaN

Wide P-metalP-metal photo


P-metal Layer Deposition : TRIZ P-metal Layer Deposition : TRIZ

Initial Situation

DD A VM

(0001) Sapphire Substrate

n-GaN


n-GaN

p-Al0.2 Ga0.8 N

InGaN/ InGaN MQW

p-GaNGaN/p-Al0.14 Ga0.86 N

p-electrode

n-electrode

SiO2

MD-SLSCladding layer

1.5 m (Contact hole width)

2 m (Ridge Width) Device Fabrication

Ridge & Mesa Etching

Passivation layer deposition

Formation of n-electrode

Formation of contact hole

Formation of p-electrode

Bonding metal & mirror coating

1 Fine contact hole patterning (1.5m x 500m)Too fine 1.5m width etching unstable process large variance of IthLoss of current appear2


DD A VMP-metal Layer Deposition : TRIZ P-metal Layer Deposition : TRIZ

Problem refinementProblem refinement Length of stationary object Loss of energy

6. Multifunctionality 28.Mechanical interaction substitution

TechnicalTechnicalContradictionContradiction

Improving feature : increase P-metal width.

Worsening feature

: current loss at P-metal

at outside of ridge




Ridge Etching

with PR/SiO2 mask

Sapphire Substrate


n-GaN

SiO2

PR

Reused PR mask (Multifunction)Oxide passivation layer

Self-alignedSelf-alignedContact holeContact hole

Sapphire Substrate


n-GaN

Sapphire Substrate


n-GaN

Reused SiO2 mask (Multifunction)Oxidation of etching surface

1.5m width etching,contact hole patterning

process was disappeared.



않고

Contact hole formation with self-aligned process.Contact hole formation with self-aligned process.Removing of most difficult process.Removing of most difficult process.No current loss by uniform shape of p-metal.No current loss by uniform shape of p-metal.


Saving of process time.Saving of process time.Improved reliability of process (yield)Improved reliability of process (yield)Improved reliability of product (variance of Ith)Improved reliability of product (variance of Ith)


Passivation Layer Deposition : DOEPassivation Layer Deposition : DOE DD A VM

Needs of DOE

Results of DOE

Not enough PECVD condition for SiO2 passivation layer. Optimization need Not enough PECVD condition for SiO2 passivation layer. Optimization need

1st DOE : 2(4) + 2 , selecting meaning factor : N2Ogas and Temperature.1st DOE : 2(4) + 2 , selecting meaning factor : N2Ogas and Temperature. No corelationship between factors.No corelationship between factors.2nd DOE : 2(2) + 1.2nd DOE : 2(2) + 1.3rd DOE : 2(2) + 2(2) + center point, another meaning factor3rd DOE : 2(2) + 2(2) + center point, another meaning factor SiH4/N2O ratio.SiH4/N2O ratio.4th Response Surface Analysis4th Response Surface Analysis


DD A VMAfterAfter TRIZTRIZ in 6 sigma in 6 sigma

산포105 mA 16 mA

Before After

260 mA

42 mA

임계

전류

(It

h)

Variance of Ith : From 105mA to 16mAVariance of Ith : From 105mA to 16mA


Group Ith, / Vth / P Substrate Lasing time Date Issued

Nichia 45mA, 5V, 5mW ELOG 10,000 h ''99 Sep

Sony 33.3mA, 5.4V, 5mW ELOG 2000 h '00 Sep

SAIT 30mA, 5.8V, 3mW ELOG 2500 h '00 Nov

Fujitsu 60mA, 8.3V 4H-SiC 57 h '99 May

NEC 36mA, 7.5V n:GaN 1 h '99 July

Xerox 107mA, 6.5V Sapphire 10 h '99 July

Cree 107mA, 15.7V, 1mW 6H-SiC 100 h '00 Nov

Matsushita 440mA, 11.4V Sapphire < 1 min '99 July

45 mA, 5V, 5mW

30 mA, 5.8V, 3mW

DD A VMAfterAfter TRIZTRIZ in 6 sigma in 6 sigma

samsung advanced institute of technology 2nd asian im user group meeting in japan samsung 2001.09.13

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