scan-through-tap: combining scan chain and boundary scan features in soc

Z. Stamenković1, M. Giles2, and F. Russi21IHP GmbH, Frankfurt (Oder), GERMANY2Synopsys Inc., Mountain View, CA, USA

13th IEEE European Test Symposium, Verbania, ITALY, May 25-29, 2008

Scan-Through-TAP: Combining Scan Chain and Boundary Scan Features in SOC


Introduction

• What is Scan-through-TAP?

Use of IEEE Standard 1149.1 user instruction to concatenate the internal scan chain with the BSR chain to perform a single chain operation

• What do we achieve implementing Scan-through-TAP?

Reduction of the scan pins number

Accessibility of the internal scan chains through the TAP controller

Single shift path through for burn-in and diagnostics

• What kind of EDA tools do we need?

Standard synthesis, DFT, BSD, and ATPG tools


DFT/BSD in SOC Design Flow

yes

ApplicationsApplications

SystemSpecification

SystemSpecification

Library DatabaseLibrary Database

New ModulesCustomisable Modules

(synthesisable RTL code)

Configurable Modules(synthesisable RTL code)

Predefined Modules(synthesised net-list, SDF

and/or LEF)

Predefined Modules(memory and custom blocks)

Simulation OK?Simulation OK?

HDL Model DefinitionHDL Top Module Definition

Logic Synthesis


Layout Synthesis

no

yes

no


Final ChipLayout

yes

no

Test BenchesTest BenchesLayout

Re-synthesisSufficient? yes

LogicRe-synthesisSufficient? yes

no

no

New Modules

ATPG

DFT/BSD


Scan Insertion Flow

• Read in synthesized design

• Define clock constraints

• Define scan chain

• Insert scan chains

• Write out scan test protocol and netlist for TetraMAX

Read Design

Create Test Protocol

Specify Scan Architecture

Insert Scan Paths

Handoff Design

DFT DRC

Preview

DFT DRCCoverage


Boundary Scan Insertion Flow

Set BSD STT specifications

Preview BSD

Insert BSD logic(Synthesis integrated)

BSD Gate LevelNetlist

Read Pin Map

Check IEEE 1149.1 Stdcompliance

BSDL File

BSD PatternsBSDL File

BSD Patterns

1149.1 BSD Inserted design

Lib

Read design netlist

Lib

• Preview your JTAG design• Insert your JTAG logic• Write out final netlist• Write BSDL file and patterns (optional)• Check compliance to IEEE 1149.1 STD• Write BSDL file and BSD patterns• Write the STIL protocol file for ATPG

• Read technology synthesis libraries• Read scanned ready netlist with IOs• Set TAP FSM specification• Set STT specification• Read pin map for die package BSR order


Scan-Through-TAP Register


Netlist & SPF

TetraMAXTetraMAX® ATPG ATPG

ATPG Patterns

RTL

Design Compiler

BSD CompilerBSD CompilerJTAG InsertionJTAG Insertion

DFT CompilerDFT CompilerTest SynthesisTest Synthesis

Functional Patterns

STT Test Patterns


Implementation Results (1)

• SOC features0.25 µm CMOS technology23 mm2 of silicon area

2.5 mm2 occupied by memory~ 1 million transistors104 functional ports

12 inputs44 outputs48 bidirectional

5 TAP portsTRSTTCKTMSTDITDO


Implementation Results (2)

• Single scan register made of around 15000 scan flip-flops• Boundary scan register of 151 cell• 5 TAP instructions

BYPASSEXTESTPRELOADSAMPLESTT

• 32000 BSD functional test patterns• 1151 ATPG test patterns• Chip area overhead below 7%

Caused by insertion of scan flip-flops and boundary scan logic• Combined fault coverage is slightly above 94%


Summary

• Scan-Through-TAP methodology provides the infrastructure for both testing of system’s internal nodes and testing of system’s boundary circuitry

A good solution for pin limited SOC designs

• A middle-size processor-based SOC used for implementation

Results show small chip area overhead, acceptable number of test patterns, and high fault coverage

scan-through-tap: combining scan chain and boundary scan features in soc

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