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Design and control of a direct drive wind turbine equipped with

multilevel converters

Mohamed Abbes a, Jamel Belhadj a,b,*, Afef Ben Abdelghani Bennani a,c

a LSE-ENIT, P.O Box 37, Belvedere, 1002 Tunis, Tunisiab ESSTT, P.O. Box 56, Monfleury, 1008 Tunis, Tunisiac INSAT, P.O. Box 676, North Urban Centre, 1080 Tunis, Tunisia

a r t i c l e i n f o

Article history:

Received 10 September 2008

Accepted 18 October 2009

Available online 20 November 2009

Keywords:

Direct drive wind turbine

NPC

Multilevel converters

Phase locked loop

Voltage dips

G.C.R

a b s t r a c t

This paper concentrates on the design and control of a three-level grid side converter (GSC) for direct

drive high power wind turbines. The three-level, neutral point clamped (NPC) topology was investigated.

The proposed control scheme, based on vector current control, offers very satisfying performances

regarding to structure stability and grid connection requirements (GCR). In order to have an accurate

evaluation of grid voltage source, two grid synchronization methods are developed and their perfor-

mances are compared. The GSC performances are evaluated under both normal and grid fault conditions.

Simulation results show that stability is maintained during voltage dips and that the proposed direct

drive wind turbine satisfies completely GCR.

Ó 2009 Elsevier Ltd. All rights reserved.

1. Introduction

Wind power is one of the most attractive renewable energy

sources since it does not emit pollutant and many countries have

a high level of wind potential. As a consequence, wind turbine

generator systems are coming into wide use in electricity genera-

tion. Today, there are many wind turbine manufacturers worldwide

and different generator and power electronics configurations are

used. The most commonly used concepts are the fixed speed

squirrel-cage induction generator, the doubly fed induction

generator (DFIG) and the direct drive topology using a permanent

magnet synchronous generator (PMSG). For the latter concept, the

gearbox is removed and replaced by a multi-poles permanent

magnet synchronous generator. Gearbox removal saves the costs of

lubrication, maintenance, and installation [1]. In addition, the

direct drive structure can operate without any reactive power

consumption and its performances agree perfectly with grid

interconnection guidelines for wind power plants [2]. Up to now,

major technological developments in the wind turbine industry

focus on cost reduction and operational reliability. In addition to

these basic targets, the principal concern of manufacturers at

present is to increase wind turbine production capacity. However,

design of more powerful wind turbines often leads to high values of

the DC bus voltage. These values could exceed voltage blocking

capacities of currently available power devices, and particularly for

direct drive structure since this topology is based on full-sized

power converters. Even if high power semiconductors can be used

in some cases, these components are characterized by high

conduction and commutation losses. Therefore, utilization of

multilevel converters in large sized wind turbines seems to be very

interesting. As for all other applications, integration of multilevel

topologies withinwind turbines would also reduce output harmonic

distortion and consequentlyoutputfilter size,reduce dV/dt and then

improve the whole structure electromagnetic compatibility

characteristics.

In this paper, a three-level grid side converter design for a 2MW

direct drive wind turbine fully satisfying GCR is presented (Fig. 3). A

three-level NPC converter model and simulation is discussed in

section II. The general control scheme of the multilevel Grid Side

Converter is given in section III. This scheme should particularly

control the produced power at the point of common connection

and minimize DC bus voltage ripple. To achieve these perfor-

mances, control method uses an inner grid current controller

combined with an outer DC bus voltage controller based on

instantaneous active and reactive powers. Section _V deals with the

grid synchronization issue. Two methods are described and their

performances under distorted utility conditions are evaluated.* Corresponding author. ESSTT, Electrical (GE), BP 56, Bab Menera, Tunis 1008,

Tunisia. Tel.: þ216 98 560 665; fax: þ216 71 391 166.

E-mail address: [email protected] (J. Belhadj).

Contents lists available at ScienceDirect

Renewable Energy

j o u r n a l h o m e p a g e : w w w . e l s e v i e r . c o m / l o c a t e / r e n e n e

0960-1481/$ – see front matter Ó 2009 Elsevier Ltd. All rights reserved.

doi:10.1016/j.renene.2009.10.021

Renewable Energy 35 (2010) 936–945

mailto:[email protected]

http://www.sciencedirect.com/science/journal/09601481

http://www.elsevier.com/locate/renene

http://www.elsevier.com/locate/renene

http://www.sciencedirect.com/science/journal/09601481

mailto:[email protected]

7/31/2019 Science 32


Section V focuses on the proposed structure behaviour under

voltage dips conditions: Performances are then evaluated taking

into account stability and compliance with GCR.

2. Three-level NPC inverter topology and modeling

Multilevel converters offer many advantages for high powerelectronics applications. In particular, they permit operation at

higher DC voltage using series connected power semiconductors.

Today, many topologies of multilevel converters are available.

The diode-clamped was one of the first developed [3]. It provides

more than two voltage levels by connecting the output voltage to

series connected DC bus capacitors. This is achieved by clamping

diodes. Fig. 1 depicts the three-level NPC inverter topology: Each

of the three legs can provide one additional output voltage level

to that of the classical two-level inverter. The neutral point

voltage, corresponding to one half of the DC bus voltage, is

available at the output of each phase when appropriate diodes

are clamped.

For phase «a» for example, Table 1 gives for each state S a, the

switching signals T a1, T a2 and the output voltage V ag . Current iadc1 isthe a-phase component to the junction current idc 1.

According to table I, output voltages V (a,b,c ) g can be expressed as:

V ag ¼Xi ¼ 2

i ¼ 1

T ai Â V ci (1)

In the case of a three phase balanced load, expressions of phase

voltages are:0@V an

V bnV cn

1A ¼1

3Â

0@ 1 0 À1À1 1 00 À1 1

1AÂ

0@V abV bc V ca

1A (2)

0@V abV bc V ca

1A ¼0@ 1 À1 0

0 1 À1À1 0 1

1AÂ0@V ag

V bg V cg

1A (3)

Equations (2) and (3) give:

0@V anV bn

V cn

1A ¼ 13

Â0@ 2 À1 À1À1 2 À1À1 À1 2

1AÂ0@V ag V bg

V cg

1A (4)

Then, inverter phase to line voltages are related to the switching

signals by:

0@V an

V bnV cn

1A ¼1

3Â

0@ 2 À1 À1À1 2 À1À1 À1 2

1AÂ

0BBBBBBBB@

Pi ¼ 2

i ¼ 1

T ai Â V ciPi ¼ 2

i ¼ 1

T bi Â V ciPi ¼ 2

i ¼ 1

T ci Â V ci

1CCCCCCCCA(5)

Moreover, neutral point current idc 1 expression can be written as

(Table 1):

idc 1 ¼ ðT a1 À T a2Þ Â ia þ ðT b1 À T b2Þ Â ib þ ðT c 1 À T c 2Þ Â ic

¼ ic 1 À ic 2 ð6Þ

Voltage ripples of the two DC bus capacitors are calculated as follows

(Herein, DC bus voltage is assumed constant and C 1 ¼ C 2 ¼ C ):

ic 1 ¼ C ÂdV c 1

dt ¼ C Â

dðU dc À V c 2Þ

dt ¼ ÀC Â

dV c 2

dt ¼ Àic 2 (7)

Then:

dV c 1

dt ¼

1

C Â

idc 1

2(8)

dV c 2

dt ¼ À1

C Â idc 1

2(9)

Simulation results, carried on with a sine triangle modulation, are

given in Fig. 2. The voltage balance between DC bus capacitors is

>

>

ic2

ic1

d0

d2

d1

g

cb

aidc1

idc2

+

- Udc

Vc2

Vc1

Ta1

T'a2

T'a1

Ta2

Tc1

T'c2

T'c1

Tc2Tb2

T'b1

T'b2

Tb1

a b c

ia ib ic

C1

C2

Fig. 1. Three-level NPC inverter topology.

Table 1

Three-level inverter states (phase a).

S a T a2 T a1 V ag iadc1

0 0 0 0 0

1 0 1 V c1 ia

2 1 1 V c1 þ V c2 0

M. Abbes et al. / Renewable Energy 35 (2010) 936–945 937

7/31/2019 Science 32


maintained (Fig. 2b). The simulation parameters are: U dc ¼ 3KV ,

C 1 ¼ C 2 ¼ 2.5 mF for the DC bus and R ¼ 10U, L ¼ 0.1H , for the load.

3. Control strategy of the three-level grid side converter

The main attention of this paper is the design and control of the

GSC, so the power chain was simplified by replacing the turbine

generator-rectifier group by an equivalent current source (Fig. 3).

The proposed control strategy aims to keep DC bus voltage constant

and impose PQ (active and reactive) powers injected to the grid.

Connection to the grid is achieved through an inductor filter and

a transformer. A PI-regulator was implemented to control DC bus

voltage. Output of this first controller is taken as the active power

reference at the point of common connexion. Reference grid

currents, i2d_ref and i2q_ref , are calculated through active and reactive

power references, and grid voltages V 2d, V 2q. Then, an appropriate

control loop for these grid currents is used to provide reference

voltages, V 1d_ref and V 1q_ref , for the three-level PWM-inverter.

3.1. Vector current controller

GSC is connected to the grid through an inductor filter and

a transformer (Fig. 4). This connection is described by equations

(10), and (11):

V 1ðt Þ ¼ r T 1$i1ðt Þ þ

lT 1 þL f

$

di1ðt Þ

dt þLm$

dði1ðt Þ À m$i2ðt ÞÞ

dt (10)

V 2ðt Þ ¼ Àr T 2$i2ðt Þ À lT 2$di2ðt Þ

dt þ e02ðt Þ (11)

with:

e02ðt Þ ¼ m$e01ðt Þ ¼ m$Lm$dði1ðt Þ À m

$i2ðt ÞÞ

dt

This gives:

V 1ðt Þ ¼ r T 1$i1ðt Þ þ L1$di1ðt Þ

dt À M $

dði2ðt ÞÞ

dt (12)

V 2ðt Þ ¼ Àr T 2$i2ðt Þ À L2$di2ðt Þ

dt þ M $

dði1ðt ÞÞ

dt (13)

With:

L2 ¼ m2$Lm þ lT 2: Secondary cyclic inductance, M ¼ m$Lm:

transformer mutual inductance, L1 ¼ lT 1 þ L f þ Lm(L f : filter induc-

tance). In the synchronous reference frame «dq» equations (12) and

(13) are written as:

0 0.005 0.01 0.015 0.02 0.025 0.03 0.035 0.04

-2

-1

1

2

0

1.45

1.50

1.55

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1

1.45

1.50

1.55

Vc1

Vc2

0 0.005 0.01 0.015 0.02 0.025 0.03 0.035 0.04

-50

0

50

Time [s]

Time [s]

Time [s]

×103

×103

a

b

c

Fig. 2. a) a-phase line to neutral voltage (V). b) Capacitors voltages (V). c) Load Currents (A).

M. Abbes et al. / Renewable Energy 35 (2010) 936–945938

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V 1d ¼ r T 1$i1d þ L1$di1d

dt À L1uS $i1q À M $

di2d

dt þ M uS $i2q (14)

V 1q ¼ r T 1$i1q þ L1$di1q

dt þ L1uS $i1d À M $

di2q

dt À M uS $i2d (15)

V 2d ¼ Àr T 2$i2d À L2$di2d

dt þ L2uS $i2q þ M $

di1d

dt À M uS $i1q (16)

V 2q ¼ Àr T 2$i2q À L2$di2q

dt À L2uS $i2d þ M $

di1q

dt þ M uS $i1d (17)

Introducing (16) into (14) and (17) into (15), the control system is

expressed as:

V 1d;q ¼L1$r T 2

M $i2d;q þ

L1

M $

L2 À

M 2

L1

!$

di2d;q

dt þ

L1

M $V 2d;q

ÀL1

M $

L2 À

M 2

L1

!uS $i2q;d þ r T 1$i1d;q ð18Þ

Considering the termsecdand ecqdefined as:

ecd;q ¼L1

M $V 2d;q À

L1

M $

L2 À

M 2

L1

!uS $i2q;d þ r T 1$i1d;q (_),(__)

And assuming that:

V bd;q ¼L1$r T 2

M $i2d;q þ

L1

M $

L2 À

M 2

L1

!$

di2d;q

dt

The block diagram modeling the grid connection can be described

as illustrated in Fig. 5:

With: K ¼M

L1 Â r T 2and sS ¼

ðL2 À M 2

L1Þ

r T 2.

V1d_c V1q_c

3L_Inverter

V2a V2b V2c

C C P

L_filter IGBT

TR d i r G

I rec

V1a_ref

i1c

V1dq_ref

V2d

3

2

s

Pulse WidthModulation

i1bi1a

i1d i1q

3

2s

ecd ecq+ +

i2a i2

3

2

i2c

V2q

+-

PI

PI

+

-

LP

Udc

i2dq_ref

referencecurrent’s

generation

Q ref P ref

Udc_ref

PI

Pcond ref ic_ref

-+

-

Pred = Udc×Irec

+ +

+

i2d i2q

PLL

Fig. 3. Grid Side Converter structure and block scheme of control algorithm.

Fig. 4. Inverter connection to the grid. Fig. 5. Grid connection block diagram.


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The above diagram shows that control voltages V 1dand V 1q affect

both grid current components i2d and i2q. Therefore, d and q axes

need to be decoupled to achieve grid currents control. This will be

done by introducing two new control inputsV 1d_c andV 1q_c . Control

voltages V 1dandV 1qare then derived from these control inputs and

compensation terms ecd,qas shown in Fig. 6:

Hence, the grid connection model is simplified to the new

system depicted by Fig. 7:

In this way, axes «d» and «q» are decoupled. Grid currents

control is achieved simply by deriving PI-regulators gains for eachof the above independent first order transfer functions. This is

performed by placing the zero of the PI controller over the pole of

the system:

TF OL ¼K I Â ð1 þ si Â sÞ

sÂ

K

1 þ ss Â s(19)

Consequently, system closed loop transfer function will be:

TF CL ¼i2d

i2d ref ¼

1

1 þ sc Â s(20)

sc is the closed loop time constant. Its expression is given by:

s

c ¼

1

K Â K I (21)

3.2. Generation of grid current references

Reference currents, i2d,q_ref , are deduced through the point of

common connection voltages and power references as follows:

i2d ref ¼P ref $V 2d þ Q ref $V 2q

V 22d

þ V 22q

(22)

i2q ref ¼P ref $V 2q À Q ref $V 2d

V 22d

þ V 22q

(23)

3.3. DC bus voltage controller

The DC bus model for the back to back NPC converters is

described by Fig. 8:In Fig. 8, R1 and R2 stand for the capacitors leakage resistances.

Assuming thatR1 ¼ R2 ¼ R, and C 1 ¼ C 2 ¼ C , DC bus voltage ripple is

given by:

C dU dc

dt ¼ C

dV c 1

dt þ C

dV c 2

dt ¼ ic 1 þ ic 2 (24)

According to the model represented in Fig. 8, equations (25) and

(26) can be deduced:

I red À I ond ¼ ic 2 þ ir 2 (25)

ic 2 þ ir 2 ¼ ic 1 þ ir 1 þ idc 1 (26)

Introducing (25) and (26) into (24) the model is simplified to:

Fig. 6. Control voltages reconstruction.

Fig. 7. Decoupled control of grid current components.

Irec

ir1

R2

R1 C1

C2

ir2

ic1

ic2

Iond

Idc1

Ib

Fig. 8. Simplified diagram of the NPC back to back converters.

PI

Udc_ref

UdcUdc

ib_ref

+-

+_

1

2

dci

2

1

R

RCs

Fig. 9. DC bus control.

V2a

V2b

V2c

RF

V2α

V2β

32

2

( )SV

arctgV

β

βαα

θ

θ

=S

~

Fig. 10. ab filter algorithm block scheme.

+

V2d

-PI+

v2d_ref = 0 1

s

nω

Δ

ˆsθ

V2q

V2a

V2b

V2c

αβ

αβ

αβ

αβ

αβ

dq

3~

2

1

V

2Vn

2V

+

ω

Fig. 11. dq Phase Locked Loop synchronization method.


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C dU dc

dt ¼ 2ðI red À I ondÞ À ðir 2 þ ir 1Þ À idc 1 (27)

Thus, DC bus voltage is calculated as:

C dU dc

dt ¼ 2ðI red À I ondÞ À

V c 1

Rþ

V c 2

R

À idc 1 (28)

As U dc ¼ V c 1 þ V c 2, (28) gives:

C dU dc

dt þ

U dc

R¼ 2ðI rec À I invÞ À idc 1 (29)

Introducing PI-regulator, the DC bus voltage control loop is

described by Fig. 9 (With ib ¼ Irec ÀIinv). The neutral point current is

seen as a constant perturbation, so the zero of the PI controller is

placed over the system pole and the closed loop transfer function is

obtained (eq. 30).

TF CL ¼1

1

K I Â 2Rs þ 1

(30)

The DC bus voltage controller is the outer loop, whereas the two

current loops are the inner ones. These are designed to reachsettling times very quickly. On the other hand, the outer controller

aims are stability and optimal regulation, and therefore it is

designed to have a biggersettling time, at least 10 times bigger than

for the inner loops. So, the inner and the outer loops can be

considered independent, and therefore, the current transfer func-

tion is not considered when the DC bus controller is designed.

4. Wind turbine grid synchronization

In order to calculate and control the «PQ» power flow to the

electrical grid and avoid wind turbines tripping, the phase angle of

utility voltage must be accurately detected. Several grid synchroni-

zation methods are proposed in [4]. In this section two synchroni-

zation algorithms will be analysed: the filtering in the ab stationary

frame and the phase locked loop (PLL). The last one is implemented

in the dq synchronous rotating reference frame (called also dqPLL).

4.1. ab filter algorithm

The phase angle of the utility grid can be obtained by filtering

input voltage signals as depicted in Fig. 10. The two voltage

components obtained from three phase transformation are filtered

in order to avoid angle detection errors due to voltage harmonics.

However, filtering will introduce signal delay which is unaccept-

able for angle detection accuracy. Therefore a proper filter design

has to be made. A resonance filter is used to filter the ab voltages

(Resonance frequency is equal to the grid frequency). Then, grid

angle is obtained by using the arctg function.

4.2. dq Phase locked loop

PLL technique is based on the synchronism between the utility

voltage vector and the synchronous reference frame «dq» (Fig. 11).

After transformation of grid voltages to the ab frame, voltage

components are normalized to the magnitude of the grid voltage

vector

kV 2abk ¼ ffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi

V 22a þ V 22b

q .

Then, Park transformation is applied to the normalized

components to obtain dq voltages in the synchronous rotating

reference frame. The lock is realized by settling V 2d_ref to zero. A PI-

regulator is used to control error between V 2d and V 2d_ref . Thisregulator output is the grid angular frequency variationDus and it

is added to the nominal grid angular frequency un. The grid angle

estimation bqs is obtained by integrating this summation. This angle

detection method can be directly implemented. However, for

Fig. 12. dq reference frame and grid voltage vector synchronisation.

Fig. 13. Voltage dips classification [5].


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Time [s]

×10

0.2 0.21 0.22 0.23 0.24 0.25 0.26 0.27 0.28

-2

0

2 ] V [ e g a t l o v d i r G

0.2 0.21 0.22 0.23 0.24 0.25 0.26 0.27 0.28

0

2

4

6

] s / d a r [

0.2 0.21 0.22 0.23 0.24 0.25 0.26 0.27 0.28

0

2

4

6

] s / d a r [

a

b

c

Fig. 14. Behaviour of the synchronization algorithm in the case of 50% unbalanced voltage dip (Type C). (a) Grid voltages. (b) ab filter algorithm signal (c) dqPLL signal.

0.2 0.21 0.22 0.23 0.24 0.25 0.26 0.27 0.28

-2

0

2 ] V [ e g a t l o v d i r G

a

0.2 0.21 0.22 0.23 0.24 0.25 0.26 0.27 0.28

0

2

4

6

] s / d a r [

b

0.2 0.21 0.22 0.23 0.24 0.25 0.26 0.27 0.28

0

2

4

6

] s / d a r [

c

Time [s]

×10

estimated angle

grid angle

estimated angle

grid angle

Fig. 15. Synchronization algorithms behaviour during frequency variation ( f ¼

47Hz ). (a) Grid voltages. (b) ab filter algorithm signal. (c) dqPLL signal.

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deriving PI-regulator parameters, a linear model for this structure

needs to be developed.A linear model is developed as follows: After normalization, ab

grid voltage components expressions become:

V n2a ¼V 2a

kV 2abk¼

V 2a ffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiV 22a þ V 2

2b

q ¼ cosðqsÞ (31)

V n2b ¼V 2b

kV 2abk¼

V 2b ffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiV 22a þ V 2

2b

q ¼ sinðqsÞ (32)

With:qs the grid angle as depicted in Fig. 12.

Considering that

bqs ¼

bqdq þ

Q2

, Park transformation applied to

the normalized voltage components gives:

V 2d ¼ cos bqs ÀQ2V n2a þ sin bqs ÀQ2V n

2b

(33)

V 2q ¼ Àsin

bqs À

Q2

V n2a þ cos

bqs À

Q2

V n2b (34)

Introducing (31) and (32) into (33) and (34), expressions of grid

voltages in the synchronous reference frame dq are:

V 2d ¼ sin bqs

V n2a À cos

bqs

V n2b ¼ sin

bqs À qs

(35)

V 2q ¼ cos bqs

V n2a þ sin

bqs

V n2b ¼ cos

bqs À qs

(36)

Assuming that the difference

bqs À qs remains close to zero, voltage

direct component can be written as follows:

Time [s]

Order of Harmonic

0.26 0.27 0.28 0.29 0.3

-40

-20

20

40 ] A [ t n e r r u C d i

r G

0 20 40 60 80 100

0

20

40

e d u t i n g a M c i n o m r a H

THD = 1.2%

a

0 20 40 60 80 100

0

1

2

e d u t i n g a M c i n o m r a H

THD = 2.7%

Time [s]

Order of Harmonic

0.26 0.27 0.28 0.29 0.3

-2

0

2 ] V [ e g a t l o V d i r G

×103b

0

Fig. 16. Grid current and voltage spectrum analysis. a) Grid current b) Grid voltage.


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V 2dz bqs À qs (37)

Consequently, the linear model transfer function of the dqPLL

structure is given by:

H ðsÞ ¼ bqs

qs¼

K pS þ K I

s2 þ K pS þ K I (38)

4.3. Evaluation of the studied synchronization algorithms

In order to test angle estimation precision, several types of grid

voltage dips have to be considered. Voltage dips are defined as

a drop in voltage magnitude which is a consequence of short-circuit

fault on the grid. Fig. 13 gives six of the most common voltage sags

as defined by Bollen [5].

Simulation results presented below show synchronization

algorithms behaviour under a 50% unbalanced voltage dip, type C

(Fig 14) andin thecaseof grid frequency variation,a commonfaultin

the power system(Fig.15). Fig.14b shows that during type C voltage

dip, ab filter algorithm fails to provide correct angle estimation. The

100 Hz frequency negative sequence due to the unbalanced fault is

filtered by theresonance filter butdifferencein amplitudes of theab

Fig. 17. Proposed low voltage ride through requirement (E. ON Netz) [7].

Fig. 18. GSC response during type C voltage dip. a) DC bus capacitor voltages, b) DC bus voltage. c) Produced power PQ. d) Produced power PQ (different time scale).


7/31/2019 Science 32


voltage components produces perturbation in synchronization

signal. In addition, for the frequency variation fault, a time lag is

introduced between the estimated angle and the grid phase angle.

This is a natural consequence of delay causedby the resonancefilter.

On the other hand, dqPLL algorithm is able totrack grid phase angle

in both fault cases (Figs. 14c and 15c). In consequence of these

results, dqPLL is selected to achieve GSC control.

5. Performances of the NPC-GSC under grid disturbance

5.1. Power quality

The system power quality is analysed in comparison with the

IEEE 519 standards [6]. These codes define harmonic distortion

limits for distributed power systems such as wind turbines, PV or

fuel cells systems. Spectrum analysis of grid currents and voltages

at the point of common connection has shown that the total

harmonic distortion (THD) is about 1.2% for current and 2.7% for

voltage. This is less than the 5% rate recommended by the IEEE

standards for both current and voltage. Thus, the produced power

complies with IEEE recommendations (Fig. 16).

5.2. Low voltage ride through (LVRT) capability of the wind turbinebased on NPC-GSC

In this section, the behaviourof the proposedNPC-GSC structure

under voltage dips is investigated. In this work, structure perfor-

mances are evaluated in comparison with the requirements of the

Germanic system operator E. ON Netz [7]. According to these

standards, wind turbines must withstand all types of voltage dips.

Dips magnitude is described based on a time diagram which

specifies voltage drop limits (Fig. 17).

The GSC model was subjected to several network disturbances

to analyse its performances. As an example, Fig.18 shows operation

when an unbalanced, type C, voltage dip occurs at the point of

common connection. At the fault beginning, voltage falls to 20% of

the grid nominal voltage then it starts to recover after a 150 mstime delay as depicted by Fig. 17. Fig. 18a shows DC bus capacitor

voltages, which are disturbed by the voltage dip. Nevertheless, they

come back to their rated value after the fault is cleared. Thus,

capacitor voltage balance is kept. Also, DC bus voltage ripple does

not exceed 5% of its rated value (Fig. 18b). This ripple decreases

gradually and it is eliminated after the end of voltage disturbance.

According to these results, it is concluded that the PWM-GSC

equipped with an NPC three-level converter keeps its stability and

can stay connected to the grid during the total period of the low

voltage fault.

6. Conclusion

In this paper, a three-level NPC Grid Side Converter for directdrive wind turbine was investigated. A general control scheme for

this GSC was defined and a-Phase Locked Loop algorithm is

developed to ensure its synchronization with grid voltage. The

designed dqPLL has overcome all test conditions and estimated

angle bqs tracks exactly the real grid angleqs. Transient operation of

the multilevel PWM-GSC under unbalanced voltage conditions is

analysed. The importance of ride through capability is increasing,

because the amount of wind power connected to the grid is in

constant growth. To test the robustness of the GSC control algo-

rithm during unbalanced voltage conditions, different voltage dips

were applied to this structure. Simulation results show that

stability is maintained during voltage dips and DC bus voltages

return totheir rated value after the end of the fault. This means that

generation is not lost because of temporary excursions of voltage.The Produced power has an acceptable quality since grid current

and voltage distortion is under standard harmonic limits. In

conclusion, this structure satisfies completely GCR and it provides

all advantages of multilevel converters to direct drive wind

turbines.

References

[1] Akhmatov V. Modelling and ride-through capabilities of variable speed windturbines with permanent magnet generators. Wiley Interscience 2005;1:1–14.

[2] Hansen LH, Blaajberg F, Sorensen P, Bak-Jensen B. Conceptual survey of generators and power electronics for wind turbines. Risø-R-1205(EN). Roskilde,Denmark: Risø National Laboratory; 2001.

[3] Nabae A, Takahashi I, Akagi H. A new neutral point clamped PWM inverter. OnIndustry applications. IEEE Trans 1981;1:518–23.

[4] Timbus A, Teodorescu R, Blaabjerg F, Liserre M. Synchronization methods forthree phase distributed power generation systems: an overview and evalua-tion. On Industry applications. IEEE Trans 2005;4:2474–81.

[5] Bollen J, Olguin G, Martins M. Voltage dips at the terminals of wind powerinstallations. Nordic wind power conference. Sweden; March 2004.

[6] IEEE Recommended practices and requirements for harmonic control in elec-trical power systems. IEEE Standards 519; 1992.

[7] ON Netz GmbH E. Grid code. High and extra high voltage. Bayreuth, www.eon-netz.com> August 2003.


http://www.eon-netz.com/




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