sdr principles

Pentek, Inc. One Park Way, Upper Saddle River, NJ 07458 Tel: (201) 818-5900 Fax: (201) 818-5904 Email: [email protected] http://www.pentek.com

1

Software Defined Radio Handbook

Eighth Edition

Pentek, Inc.One Park Way, Upper Saddle River, New Jersey 07458

Tel: (201) 818-5900 Fax: (201) 818-5904

Email: [email protected] http://www.pentek.com

Copyright 1998, 2001, 2003, 2006, 2008, 2009, 2010 Pentek Inc.

Last updated: January 2010

All rights reserved.

Contents of this publication may not be reproduced in any form without written permission.

Specifications are subject to change without notice.

Pentek, GateFlow, ReadyFow and VIM are registered trademarks of Pentek, Inc.

Sampling

Principles of SDR

Technology

Products

Applications

Summary

Links

by

Rodger H. HoskingVice-President & Cofounder of Pentek, Inc.


2


Preface

SDR (Software Defined Radio) has revolutionized electronic systems for avariety of applications including communications, data acquisition and signal processing.

This handbook shows how DDCs (Digital Downconverters) and DUCs (Digital Upconverters),the fundamental building blocks of SDR, can replace conventional analog receiver designs,

offering significant benefits in performance, density and cost.

In order to fully appreciate the benefits of SDR, a conventional analog receiversystem will be compared to its digital receiver counterpart, highlighting similarities and differences.

The inner workings of the SDR will be explored with an in-depth description of the internalstructure and the devices used. Finally, some actual board- and system-level implementations and available

off-the-shelf SDR products for embedded systems will be described.


3


Before we look at SDR and its various implementa-tions in embedded systems, well review a theoremfundamental to sampled data systems such as thoseencountered in software defined radios.

Nyquists Theorem:

Any signal can be represented by discretesamples if the sampling frequency is at least twice

the bandwidth of the signal.

Notice that we highlighted the word bandwidthrather than frequency. In what follows, well attempt toshow the implications of this theorem and the correctinterpretation of sampling frequency, also known assampling rate.

Sampling

A Simple Technique to Visualize Sampling

To visualize what happens in sampling, imaginethat you are using transparent fan-fold computerpaper. Use the horizontal edge of the paper as thefrequency axis and scale it so that the paper folds lineup with integer multiples of one-half of the samplingfrequency s. Each sheet of paper now represent what wewill call a Nyquist Zone, as shown in Figure 1.

Figure 1

Nyquists Theorem and Sampling

fs/2 fs 3fs/2 2fs 5fs/2 3fs 7fs/20

Zone 1 Zone 2 Zone 3 Zone 4 Zone 5 Zone 6 Zone 7

Frequency


4


Sampling

Figure 3

Baseband Sampling

Figure 4

A baseband signal has frequency components thatstart at = 0 and extend up to some maximum frequency.

To prevent data destruction when sampling a basebandsignal, make sure that all the signal energy falls ONY inthe 1st Nyquist band, as shown in Figure 4.

There are two ways to do this:1. Insert a lowpass filter to eliminate all signals

above s/2, or2. Increase the sampling frequency so all signals

present fall below s/2.

Note that s/2 is also known as the folding frequency.

Sampling Bandpass Signals

Figure 2

Use the vertical axis of the fan-fold paper for signalenergy and plot the frequency spectrum of the signal tobe sampled, as shown in Figure 2. To see the effects ofsampling, collapse the transparent fan-fold paper into astack.

Sampling Basics

The resulting spectrum can be seen by holding thetransparent stack up to a light and looking through it.You can see that signals on all of the sheets or zones arefolded or aliased on top of each other and theycan no longer be separated.

Once this folding or aliasing occurs during sampling,the resulting sampled data is corrupted and can never berecovered. The term aliasing is appropriate becauseafter sampling, a signal from one of the higher zonesnow appears to be at a different frequency.

Lets consider bandpass signals like the IF frequencyof a communications receiver that might have a 70 MHzcenter frequency and 10 MHz bandwidth. In this case,the IF signal contains signal energery from 65 to 75 MHz.

If we follow the baseband sampling rules above, wemust sample this signal at twice the highest signalfrequency, meaning a sample rate of at least 150 MHz.

However, by taking advantage of a technique calledundersampling, we can use a much lower sampling rate.



Ener

gy



No Signal Energy

fs/20Folded SignalsFall On Top of

Each Other


5


fs/20

Folded signalsstill fall on top ofeach other - but

now there isenergy in

only one sheet !

Undersampling

Figure 5

Sampling

Figure 6



No Signal EnergyNo Signal Energy

Undersampling allows us to use aliasing to ouradvantage, providing we follow the strict rules of theNyquist Theorem.

In our previous IF signal example, suppose we try asampling rate of 40 MHz.

Figure 5 shows a fan-fold paper plot with Fs = 40 MHz.You can see that zone 4 extends from 60 MHz to 80 MHz,nicely containing the entire IF signal band of 65 to 75 MHz.

Now when you collapse the fan fold sheets as shownin Figure 6, you can see that the IF signal is preservedafter sampling because we have no signal energy in anyother zone.

Also note that the odd zones fold with the lowerfrequency at the left (normal spectrum) and the evenzones fold with the lower frequency at the right (reversedspectrum).

In this case, the signals from zone 4 are frequencyreversed. This is usually very easy to accommodate inthe following stages of SDR systems.

Summary

Baseband sampling requires the sample frequency tobe at least twice the signal bandwidth. This is the sameas saying that all of the signals fall within the firstNyquist zone.

In real life, a good rule of thumb is to use the 80%relationship:

Bandwidth = 0.8 x s/2

Undersampling allows a lower sample rate even thoughsignal frequencies are high, PROVIDED all of thesignal energy falls within one Nyquist zone.

To repeat the Nyquist theorem: The sampling frequencymust be at least twice the signal bandwidth not thesignal frequency.

The major rule to follow for successful undersamplingis to make sure all of the energy falls entirely in oneNyquist zone.

There two ways to do this:1. Insert a bandpass filter to eliminate all signals

outside the one Nyquist zone.2. Increase the sampling frequency so all signals

fall entirely within one Nyquist zone.


6


Figure 7

The conventional heterodyne radio receiver shownin Figure 7, has been in use for nearly a century. Letsreview the structure of the analog receiver so comparisonto a digital receiver becomes apparent.

First the RF signal from the antenna is amplified,typically with a tuned RF stage that amplifies a regionof the frequency band of interest.

This amplified RF signal is then fed into a mixerstage. The other input to the mixer comes from the localoscillator whose frequency is determined by the tuningcontrol of the radio.

The mixer translates the desired input signal to theIF (Intermediate Frequency) as shown in Figure 8.

The IF stage is a bandpass amplifier that only letsone signal or radio station through. Common centerfrequencies for IF stages are 455 kHz and 10.7 MHzfor commercial AM and FM broadcasts.

The demodulator recovers the original modulatingsignal from the IF output using one of several differentschemes.

For example, AM uses an envelope detector and FMuses a frequency discriminator. In a typical home radio,the demodulated output is fed to an audio poweramplifier which drives a speaker.

Figure 8

Analog Radio Receiver Block Diagram Analog Radio Receiver Mixer

The mixer performs an analog multiplication of thetwo inputs and generates a difference frequency signal.

The frequency of the local oscillator is set so thatthe difference between the local oscillator frequency andthe desired input signal (the radio station you want toreceive) equals the IF.

For example, if you wanted to receive an FMstation at 100.7 MHz and the IF is 10.7 MHz, you wouldtune the local oscillator to:

100.7 - 10.7 = 90 MHz

This is called downconversion or translationbecause a signal at a high frequency is shifted down to alower frequency by the mixer.

The IF stage acts as a narrowband filter which onlypasses a slice of the translated RF input. The band-width of the IF stage is equal to the bandwidth of thesignal (or the radio station) that you are trying toreceive.

For commercial FM, the bandwidth is about100 kHz and for AM it is about 5 kHz. This is consis-tent with channel spacings of 200 kHz and 10 kHz,respectively.

Principles of SDR

ANALOGLOCAL

OSCILLATOR

IF AMP(FILTER)

SPEAKERANTENNA

DEMODULATOR(Detector)

ANALOGMIXER

AUDIOAMP

RFAMP

0

RF INPUT SIGNALFROM ANTENNA

MIXER TRANSLATESINPUT SIGNAL BAND

to IF FREQUENCY

ANALOG LOCALOSCILLATOR

FRFFIF

Signal


7


0 FSIG

MIXER TRANSLATESINPUT SIGNAL

BAND to DC

DIGITAL LOCALOSCILLATORFLO = FSIG

CHANNELBANDWIDTH

IF BWSignal

DIGITALMIXER

DIGITALLOCALOSC

DSP

DDCDigital Downconverter

RFTUNER

AnalogIF Signal

AnalogRF Signal A/D

CONV

Digital IFSamples LOWPASS

FILTER

DigitalBasebandSamples

SDR Receiver Block Diagram

Figure 9

Principles of SDR

Figure 10

SDR Receiver MixerFigure 9 shows a block diagram of a softwaredefined radio receiver. The RF tuner converts analog RFsignals to analog IF frequencies, the same as the first threestages of the analog receiver.

The A/D converter that follows digitizes the IF signalthereby converting it into digital samples. These samplesare fed to the next stage which is the digital downconverter(DDC) shown within the dotted lines.

The digital downconverter is typically a singlemonolithic chip or FPGA IP, and it is a key part of theSDR system.

A conventional DDC has three major sections:

A digital mixer

A digital local oscillator

An FIR lowpass filter

The digital mixer and local oscillator translate thedigital IF samples down to baseband. The FIR lowpassfilter limits the signal bandwidth and acts as a decimat-ing lowpass filter. The digital downconverter includes alot of hardware multipliers, adders and shift registermemories to get the job done.

The digital baseband samples are then fed to a blocklabeled DSP which performs tasks such as demodulation,decoding and other processing tasks.

Traditionally, these needs have been handled withdedicated application specific ICs (ASICs), and program-mable DSPs.

At the output of the mixer, the high frequencywideband signals from the A/D input (shown in Figure10 above) have been translated down to DC as complex Iand Q components with a frequency shift equal to thelocal oscillator frequency.

This is similar to the analog receiver mixer exceptthere, the mixing was done down to an IF frequency.Here, the complex representation of the signal allows usto go right down to DC.

By tuning the local oscillator over its range, anyportion of the RF input signal can be mixed down to DC.

In effect, the wideband RF signal spectrum can beslid around 0 Hz, left and right, simply by tuning thelocal oscillator. Note that upper and lower sidebands arepreserved.


8


DIGITALMIXER

DIGITALLOCAL

OSC

A/DCONV

Digital IFSamples LOWPASS

FILTER


Translation Filtering

Tuning Freq Decimation

DDC Signal Processing

Figure 12

Principles of SDR

Figure 11A Local Oscillator Frequency Switching

DDC Local Oscillator and Decimation

F1 F2 F3

90O

A/D Sample Rate(before decimation)

Sample Rate: Fs

DecimatedFilter Output

Sample Rate: Fs/N

Figure 11B FIR Filter Decimation

Because the local oscillator uses a digital phaseaccumulator, it has some very nice features. It switchesbetween frequencies with phase continuity, so you cangenerate FSK signals or sweeps very precisely with notransients as shown in Figure 11A.

The frequency accuracy and stability are determinedentirely by the A/D clock so its inherently synchronousto the sampling frequency. There is no aging, drift orcalibration since its implemented entirely with digital logic.

Since the output of the FIR filter is band limited, theNyquist theorem allows us to lower the sample rate. Ifwe are keeping only one out of every N samples, as shownin Figure 11B above, we have dropped the sampling rateby a factor of N.

This process is called decimation and it means keepingone out of every N signal samples. If the decimatedoutput sample rate is kept higher than twice the outputbandwidth, no information is lost.

The clear benefit is that decimated signals can beprocessed easier, can be transmitted at a lower rate, orstored in less memory. As a result, decimation candramatically reduce system costs!

As shown in Figure 12, the DDC performs twosignal processing operations:

1. Frequency translation with the tuning controlledby the local oscillator.

2. Lowpass filtering with the bandwidth controlledby the decimation setting.

We will next turn our attention to the SoftwareDefined Radio Transmitter.


9


DUC Signal Processing

Figure 14

Principles of SDR

SDR Transmitter Block Diagram

Figure 13

The input to the transmit side of an SDR system isa digital baseband signal, typically generated by a DSPstage as shown in Figure 13 above.

The digital hardware block in the dotted lines is aDUC (digital upconverter) that translates the basebandsignal to the IF frequency.

The D/A converter that follows converts the digitalIF samples into the analog IF signal.

Next, the RF upconverter converts the analog IFsignal to RF frequencies.

Finally, the power amplifier boosts signal energy tothe antenna.

Inside the DUC shown in Figure 14, the digitalmixer and local oscillator at the right translate basebandsamples up to the IF frequency. The IF translationfrequency is determined by the local oscillator.

The mixer generates one output sample for each ofits two input samples. And, the sample frequency atthe mixer output must be equal to the D/A samplefrequency s.

Therefore, the local oscillator sample rate and thebaseband sample rate must be equal to the D/A samplefrequency s.

The local oscillator already operates at a sample rateof s, but the input baseband sample frequency at theleft is usually much lower. This problem is solved withthe Interpolation Filter.


Fs/NDIGITALMIXER

DIGITALLOCALOSC

DUCDigital UpConverter

INTERPOLATIONFILTER

Digital IFSamples

Fs


Fs


AnalogIF

SignalD/ACONV

AnalogRF

SignalRFUpconverter

PowerAmplifierDSP


Fs/N

DIGITALMIXER

DIGITALLOCALOSC

INTERPOLATIONFILTER

Digital IFSamples

Fs


Fs


10


Interpolation Filter: Time domain

Figure 15 Figure 16

Interpolation Filter: Frequency Domain

Principles of SDR

INTERPOLATING

LOW PASS

FIR FILTER

Fs/N

IQ

INTERPOLATION

FACTOR = N

BASEBAND

INPUT

InterpolatingFilter OutputSample Rate: Fs

Baseband InputSample Rate: Fs/N

Fs

INTER-

POLATED

OUTPUT

IQ

0 IF Freq

LOCAL

OSCILLATOR

F = IF Freq

MIXER

INTERPOLATED

BASEBAND INPUT TRANSLATED OUTPUT


Fs/NDIGITALMIXER

DIGITALLOCALOSC


INTERPOLATIONFILTER

Digital IFSamples

Fs


Fs

The interpolation filter must boost the basebandinput sample frequency of s/N up to the required mixerinput and D/A output sample frequency of s.

The interpolation filter increases the sample frequencyof the baseband input signal by a factor N, known asthe interpolation factor.

At the bottom of Figure 15, the effect of theinterpolation filter is shown in the time domain.

Notice the baseband signal frequency content iscompletely preserved by filling in additional samples inthe spaces between the original input samples.

The signal processing operation performed by theinterpolation filter is the inverse of the decimation filterwe discussed previously in the DDC section.

Figure 16 is a frequency domain view of the digitalupconversion process.

This is exactly the opposite of the frequency domainview of the DDC in Figure 10.

The local oscillator setting is set equal to therequired IF signal frequency, just as with the DDC.


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DIGITALMIXER

DIGITALLOCALOSC

N

A/DCONV

LOWPASSFILTER

Translation Filtering

DSP

Fs Fb

Tuning

Freq uency

Bandwidth

Deci mation

DIGITALMIXER

DIGITALLOCALOSC

N

INTERPOLATEFILTER

TranslationFiltering

D/ACONVDSP

Fb Fs

Tuning

Freq uencyInter polation

Bandwidth

DDC Processing DUC Processing

Figure 17 Figure 18

Principles of SDR

Figure 17 shows the two-step processing performedby the digital downconverter.

Frequency translation from IF down to baseband isperformed by the local oscillator and mixer.

The tuning knob represents the programmabilityof the local oscillator frequency to select the desiredsignal for downconversion to baseband.

The baseband signal bandwidth is set by settingdecimation factor N and the lowpass FIR filter:

Baseband sample frequency b = s/N

Baseband bandwidth = 0.8 x b

The baseband bandwidth equation reflects a typical80% passband characteristic, and complex (I+Q) samples.

The bandwidth knob represents the program-mability of the decimation factor to select the desiredbaseband signal bandwidth.

Figure 18 shows the two-step processing performedby the digital upconverter:

The ratio between the required output sample rateand the sample rate input baseband sample rate deter-mines the interpolation factor N.

Baseband bandwidth = 0.8 x b

Output sample frequency s = b x N

Again, the bandwidth equation assumes a complex(I+Q) baseband input and an 80% filter.

The bandwidth knob represents the programma-bility of the interpolation factor to select the desiredinput baseband signal bandwidth.

Frequency translation from baseband up to IF isperformed by the local oscillator and mixer.

The tuning knob represents the programmabilityof the local oscillator frequency to select the desired IFfrequency for translation up from baseband.


12


Key DDC and DUC Benefits SDR Tasks

Figure 19

Here weve ranked some of the popular signalprocessing tasks associated with SDR systems on a twoaxis graph, with compute Processing Intensity on thevertical axis and Flexibility on the horizontal axis.

What we mean by process intensity is the degree ofhighly-repetitive and rather primitive operations. At theupper left, are dedicated functions like A/D convertersand DDCs that require specialized hardware structuresto complete the operations in real time. ASICs are usuallychosen for these functions.

Flexibility pertains to the uniqueness or variabilityof the processing and how likely the function may haveto be changed or customized for any specific application.At the lower right are tasks like analysis and decisionmaking which are highly variable and often subjective.

Programmable general-purpose processors or DSPsare usually chosen for these tasks since these tasks can beeasily changed by software.

Now lets temporarily step away from the softwareradio tasks and take a deeper look at programmablelogic devices.

Figure 20

DIGITALMIXER

DIGITALLOCALOSC

A/DCONV

Digital IFSamples

Fs

LOWPASSFILTER


Fs/N


D/ACONV


Fs/NDIGITALMIXER

DIGITALLOCALOSC

INTERPOLATIONFILTER

Digital IFSamples

Fs


Fs

DUCDigital Down

Converter

Think of the DDC as a hardware preprocessor forprogrammable DSP or GPP processor. It preselects onlythe signals you are interested in and removes all others.This provides an optimum bandwidth and minimumsampling rate into the processor.

The same applies to the DUC. The processor onlyneeds to generate and deliver the baseband signalssampled at the baseband sample rate. The DUC thenboosts the sampling rate in the interpolation filter,performs digital frequency translation, and deliverssamples to the D/A at a very high sample rate.

The number of processors required in a system isdirectly proportional to the sampling frequency ofinput and output data. As a result, by reducing thesampling frequency, you can dramatically reduce thecost and complexity of the programmable DSPs orGPPs in your system.

Not only do DDCs and DUCs reduce the processorworkload, the reduction of bandwidth and sampling ratehelps save time in data transfers to another subsystem. Thishelps minimize recording time and disk space, and reducestraffic and bandwidth across communication channels.

Principles of SDR


13


Early Roles for FPGAs Legacy FPGA Design Methodologies

Figure 21 Figure 22

Technology

As true programmable gate functions becameavailable in the 1970s, they were used extensively byhardware engineers to replace control logic, registers,gates, and state machines which otherwise would haverequired many discrete, dedicated ICs.

Often these programmable logic devices were one-time factory-programmed parts that were soldered downand never changed after the design went into production.

These programmable logic devices were mostly thedomain of hardware engineers and the software toolswere tailored to meet their needs. You had tools foraccepting boolean equations or even schematics to helpgenerate the interconnect pattern for the growingnumber of gates.

Then, programmable logic vendors started offeringpredefined logic blocks for flip-flops, registers andcounters that gave the engineer a leg up on popularhardware functions.

Nevertheless, the hardware engineer was stillintimately involved with testing and evaluating thedesign using the same skills he needed for testingdiscrete logic designs. He had to worry about propaga-tion delays, loading, clocking and synchronizingalltricky problems that usually had to be solved the hardwaywith oscilloscopes or logic analyzers.

Used primarily to replace discrete digitalhardware circuitry for: Control logic Glue logic Registers and gates State machines Counters and dividers

Devices were selected by hardware engineers Programmed functions were seldom changed

after the design went into production

Tools were oriented to hardware engineers Schematic processors Boolean processors Gates, registers, counters, multipliers

Successful designs required high-levelhardware engineering skills for: Critical paths and propagation delays Pin assignment and pin locking Signal loading and drive capabilities Clock distribution Input signal synchronization and skew analysis


14


FPGAs: New Device Technology FPGAs: New Development Tools

Figure 23 Figure 24

Technology

Its virtually impossible to keep up to date on FPGAtechnology, since new advancements are being madeevery day.

The hottest features are processor cores inside thechip, computation clocks to 500 MHz and above, andlower core voltages to keep power and heat down.

About five years ago, dedicated hardware multipliersstarted appearing and now youll find literally hundredsof them on-chip as part of the DSP initiative launchedby virtually all FPGA vendors.

High memory densities coupled with very flexiblememory structures meet a wide range of data flowstrategies. Logic slices with the equivalent of over tenmillion gates result from silicon geometries shrinkingdown to 0.1 micron.

BGA and flip-chip packages provide plenty of I/Opins to support on-board gigabit serial transceivers andother user-configurable system interfaces.

New announcements seem to be coming out everyday from chip vendors like Xilinx and Altera in a never-ending game of outperforming the competition.

To support such powerful devices, new design toolsare appearing that now open up FPGAs to both hard-ware and software engineers. Instead of just acceptinglogic equations and schematics, these new tools acceptentire block diagrams as well as VHDL and Verilogdefinitions.

Choosing the best FPGA vendor often hingesheavily on the quality of the design tools available tosupport the parts.

Excellent simulation and modeling tools help toquickly analyze worst case propagation delays andsuggest alternate routing strategies to minimize themwithin the part. This minimizes some of the trickytiming work for hardware engineers and can save onehours of tedious troubleshooting during design verifica-tion and production testing.

In the last few years, a new industry of third partyIP (Intellectual Property) core vendors now offerthousands of application-specific algorithms. These areready to drop into the FPGA design process to help beatthe time-to-market crunch and to minimize risk.

500+ MHz DSP Slices and Memory Structures Over 1000 dedicated on-chip hardware multipliers On-board GHz Serial Transceivers Partial Reconfigurability Maintains

Operation During Changes Switched Fabric Interface Engines Over 330,000 Logic Cells Gigabit Ethernet media access controllers On-chip 405 PowerPC RISC micro-controller cores Memory densities approaching 15 million bits Reduced power with core voltages at 1 volt Silicon geometries to 65 nanometers High-density BGA and flip-chip packaging Over 1200 user I/O pins Configurable logic and I/O interface standards

High Level Design Tools Block Diagram System Generators Schematic Processors High-level language compilers for

VHDL & Verilog Advanced simulation tools for modeling speed,

propagation delays, skew and board layout Faster compilers and simulators save time Graphically-oriented debugging tools

IP (Intellectual Property) Cores FPGA vendors offer both free and licensed cores FPGA vendors promote third party core vendors Wide range of IP cores available


15


FPGAs for SDR FPGAs Bridge the SDR Application Space

Figure 25 Figure 26

Technology

As a result, FPGAs have significantly invaded theapplication task space as shown by the center bubble inthe task diagram above.

They offer the advantages of parallel hardware tohandle some of the high process-intensity functions likeDDCs and the benefit of programmability to accommo-date some of the decoding and analysis functions of DSPs.

These advantages may come at the expense ofincreased power dissipation and increased product costs.However, these considerations are often secondary to theperformance and capabilities of these remarkable devices.

Like ASICs, all the logic elements in FPGAs canexecute in parallel. This includes the hardware multipli-ers, and you can now get over 1000 of them on a singleFPGA.

This is in sharp contrast to programmable DSPs,which normally have just a handful of multipliers thatmust be operated sequentially.

FPGA memory can now be configured with thedesign tool to implement just the right structure fortasks that include dual port RAM, FIFOs, shift registersand other popular memory types.

These memories can be distributed along the signalpath or interspersed with the multipliers and mathblocks, so that the whole signal processing task operatesin parallel in a systolic pipelined fashion.

Again, this is dramatically different from sequentialexecution and data fetches from external memory as in aprogrammable DSP.

As we said, FPGAs now have specialized serial andparallel interfaces to match requirements for high-speedperipherals and buses.

Parallel Processing Hardware Multipliers for DSP

FPGAs can now have over 500 hardware multipliers Flexible Memory Structures

Dual port RAM, FIFOs, shift registers, look up tables, etc. Parallel and Pipelined Data Flow

Systolic simultaneous data movement Flexible I/O

Supports a variety of devices, buses and interface standards High Speed Available IP cores optimized for special functions


16


ModelModel

FeatureFeature7141-4307141-430 7141-4207141-420 7142-4287142-428 71517151 71527152 71537153

125 MHz125 MHzMax Sample RateMax Sample Rate 125 MHz125 MHz 125 MHz125 MHz 200 MHz200 MHz 200 MHz200 MHz 200 MHz200 MHz

14-Bit14-BitInput ResolutionInput Resolution 14-Bit14-Bit 14-Bit14-Bit 16-Bit16-Bit 16-Bit16-Bit 16-Bit16-Bit

11Input ChannelsInput Channels 22 44 44 44 44

256256DDC ChannelsDDC Channels 2 or 42 or 4 44 256256 3232 2 or 42 or 4

1K-10K1K-10KDecimation RangeDecimation RangeCore: 2,4,8,16,32,64

GC4016: 32to 16k

Core: 2,4,8,16,32,64

GC4016: 32to 16k2 to 64K

Steps of 1

2 to 64K

Steps of 1128 to 1024

Steps of 64

128 to 1024

Steps of 6416 to 8192

Steps of 8

16 to 8192

Steps of 82 Ch: 2 to 65536

4 Ch: 2 to 256

2 Ch: 2 to 65536

4 Ch: 2 to 256

24*DEC/51224*DEC/512No. of Filter TapsNo. of Filter Taps Core: 28*DECCore: 28*DEC 28*DEC28*DEC 24*DEC/6424*DEC/64 28*DEC/828*DEC/8 28*DEC28*DEC

Normal I/QNormal I/QOutput FormatOutput FormatI/Q, Offset,

Inverse, Real

I/Q, Offset,

Inverse, RealI/Q,

Offset, Inverse

I/Q,

Offset, InverseI/Q,

Offset, Inverse

I/Q,

Offset, InverseI/Q,

Offset, Inverse

I/Q,

Offset, InverseI/Q,

Offset, Inverse

I/Q,

Offset, Inverse

16-Bit16-BitOutput ResolutionOutput Resolution 16-Bit, 24-Bit16-Bit, 24-Bit 16-Bit, 24-Bit16-Bit, 24-Bit 16-Bit, 24-Bit16-Bit, 24-Bit 16-Bit, 24-Bit16-Bit, 24-Bit 16-Bit, 24-Bit16-Bit, 24-Bit

32-bits - 0 to Fs32-bits - 0 to FsTuning FrequencyTuning Frequency 32-bits - 0 to Fs32-bits - 0 to Fs 32-bits - 0 to Fs32-bits - 0 to Fs 32-bits - 0 to Fs32-bits - 0 to Fs 32-bits - 0 to Fs32-bits - 0 to Fs 32-bits - 0 to Fs32-bits - 0 to Fs

--Phase OffsetPhase Offset 32-bits 180 deg32-bits 180 deg 32-bits 180 deg32-bits 180 deg 32-bits 180 deg32-bits 180 deg 32-bits 180 deg32-bits 180 deg 32-bits 180 deg32-bits 180 deg

32 bits32 bitsGain ControlGain Control 32 bits32 bits 32 bits32 bits 32 bits32 bits 32 bits32 bits 32 bits32 bits

NoneNoneDAC InterpolationDAC Interpolation 2 - 327682 - 32768 2 - 327682 - 32768 NoneNone NoneNone NoneNone

NoneNonePower MetersPower Meters NoneNone NoneNone NoneNone 3232 2 or 42 or 4

NoneNoneThresh DetectorsThresh Detectors NoneNone NoneNone NoneNone 3232 2 or 42 or 4

NoneNoneChannel SummersChannel Summers NoneNone NoneNone NoneNone 32 channels32 channels 2 or 4 channels2 or 4 channels

The above chart shows the salient characteristics forsome of Penteks SDR products with IP cores installedin their FPGAs. The chart provides information regard-ing the number of input channels, maximum samplingfrequency of their A/Ds, and number of DDC channelsin each one. This information is followed by DDCcharacteristics regarding the decimation range and availablesteps along with the output format and resolution.

Technology

Typical Pentek Products with Installed SDR IP Cores

Other information thats specific to each core isincluded as well as an indication of the Models thatinclude an interpolation filter and output D/A. As shownin the chart, some of these Models include power meters,threshold detectors, and gain along with phase offsetcontrol for optimizing results in applications such asdirection-finding and beamforming.

All the Models shown here are PMC or PMC/XMCmodules. These products are also available in PCI, cPCIand PCIe formats as well.

Figure 27


17


Technology

FPGA Resource Comparison

Figure 28

The above chart compares the available resources inthe four Xilinx FPGA families that are used in most ofthe Pentek products.

Virtex-II Pro: VP50 and VP70 Virtex-4: FX, LX and SX Virtex-5: FXT, LXT and SXT Virtex-6: LXT and SXT

The Virtex-II family includes hardware multipliersthat support digital filters, averagers, demodulatorsand FFTsa major benefit for software radio signalprocessing. The Virtex-II Pro family dramaticallyincreased the number of hardware multipliers and alsoadded embedded PowerPC microcontrollers.

The Virtex-4 family is offered as three subfamiliesthat dramatically boost clock speeds and reduce powerdissipation over previous generations.

The Virtex-4 LX family delivers maximum logicand I/O pins while the SX family boasts of 512 DSPslices for maximum DSP performance. The FX family isa generous mix of all resources and is the only family tooffer RocketIO, PowerPC cores, and the newly addedgigabit Ethenet ports.

*Virtex-II Pro and Virtex-4 Slices actually require 2.25 Logic Cells;

Virtex-5 and Virtex-6 Slices actually require 6.4 Logic Cells

Virtex-II Pro Virtex-4 Virtex-5 Virtex-6

VP50, VP70 FX, LX, SX FXT, LXT, SXT LXT, SXT

Logic Cells 53K74K 41K152K 46K156K 128K476K

Slices* 24K33K 18K68K 7K24K 20K74K

CLB Flip-Flops 47K66K 49K93K 150K207K 160K595K

Block RAM (kb) 4,1765,904 1,7286,768 2,1608,784 9,50438,304

DSP Hard IP 18x18 Multipliers DSP48 DSP48E DSP48E

DSP Slices 132328 64512 48640 4802,016

Serial Gbit Transceivers 020 1216 20

PCI Express Blocks 2

SelectIO 448768 480640 600

The Virtex-5 family LXT devices offer maximumlogic resources, gigabit serial transceivers, and Ethernetmedia access controllers. The SXT devices push DSPcapabilities with all of the same extras as the LXT. TheFXT devices follow as the embedded system resource devices.

The Virtex-5 devices offer lower power dissipation,faster clock speeds and enhanced logic slices. They alsoimprove the clocking features to handle faster memoryand gigabit interfaces. They support faster single-endedand differential parallel I/O buses to handle fasterperipheral devices.

The Virtex-6 devices offer higher density, moreprocessing power, lower power consumption, andupdated interface features to match the latest technologyI/O requirements including PCI Express. Virtex-6supports PCI Express 2.0 in x1 through x8 configurations.

The ample DSP slices are responsible for themajority of the processing power of the Virtex-6 family.Increases in operating speed from 500 MHz in V-4 to550 MHz in V-5 to 600 MHz in V-6 and increasingdensity allows more DSP slices to be included in thesame-size package. As shown in the chart, Virtex-6 topsout at an impressive 2016 DSP slices.


18


PMC, PMC/XMC, CompactPCI, PCI, PCI Express and VMEbus Software Radio

The Pentek family of board-level software radioproducts is the most comprehensive in the industry.Most of these products are available in several formatsto satisfy a wide range of requirements.

In addition to their commercial versions, manysoftware radio products are available in ruggedized andconduction-cooled versions.

All of the software radio products include input A/Dconverters. Some of these products are software radioreceivers in that they include only DDCs. Others aresoftware radio transceivers and they include DDCs aswell as DUCs with output D/A converters. These comewith independent input and output clocks.

All Pentek software radio products include multiboardsynchronization that facilitates the design of multichannelsystems with synchronous clocking, gating and triggering.

Penteks comprehensive software support includesthe ReadyFlow Board Support Package, the GateFlow

FPGA Design Kit and high-performance factory-installed IP cores that expand the features and rangeof many Pentek software radio products. In addition,Pentek software radio recording systems are supportedwith SystemFlow recording software that features agraphical user interface.

A complete listing of these products with activelinks to their datasheets on Penteks website is includedat the end of this handbook.

PMC/XMC Module

Products

Figure 29

CompactPCI Board

PCI Board

VMEbus BoardFull-lengthPCI Express Board

Half-lengthPCI Express Board


19


Multiband Receivers

The unit supports the channel combining mode ofthe 4016s such that two or four individual 2.5 MHzchannels can be combined for output bandwidths of5 MHz or 10 MHz, respectively.

The sampling clock can be sourced from an internal100 MHz crystal oscillator or from an external clock suppliedthrough an SMA connector or the LVDS clock/sync bus onthe front panel. The LVDS bus allows multiple modules to besynchronized with the same sample clock, gating, triggeringand frequency switching signals. Up to 80 modules can besynchronized with the Model 9190 Clock and Sync Genera-tor. Custom interfaces can be implemented by using the 64user-defined FPGA I/O pins on the P4 connector.

Versions of the 7131 are also available as a PCIboard (Model 7631A), 6U cPCI (Models 7231 and7231D dual density), or 3U cPCI (Model 7331). Allthese products have similar features.

Products

The Model 7131, a 16-Channel Multiband Receiver,is a PMC module. The 7131 PMC may be attached to awide range of industry processor platforms equippedwith PMC sites.

Two 14-bit 105 MHz A/D Converters accepttransformer-coupled RF inputs through two front panelSMA connectors. Both inputs are connected to fourTI/GC4016 quad DDC chips, so that all 16 DDCchannels can independently select either A/D.

Four parallel outputs from the four DDCs deliverdata into the Virtex-II FPGA which can be either theXC2V1000 or XC2V3000. The outputs of the two A/Dconverters are also connected directly to the FPGA tosupport the DDC bypass path to the PCI bus and for directprocessing of the wideband A/D signals by the FPGA.

Model 7131 PMC Model 7231 6U cPCI Model 7331 3U cPCI Model 7631A PCI

Figure 30Model 7231D

6U cPCIModel 7331

3U cPCI

Model 7631APCI

Model 7131PMC


20


Multiband Transceivers with Virtex-II Pro FPGA

Products

Figure 31

Model 7140 PMC/XMC Model 7240 6U cPCI Model 7340 3U cPCI Model 7640 PCI

Model 7140PMC/XMC

The Model 7140 PMC module combines bothreceive and transmit capability with a high-performanceVirtex II-Pro FPGA and supports the VITA 42 XMCstandard with optional switched fabric interfaces forhigh-speed I/O.

The front end of the module accepts two RF inputsand transformer-couples them into two 14-bit A/Dconverters running at 105 MHz. The digitized outputsignals pass to a Virtex-II Pro FPGA for signal process-ing or routing to other module resources.

These resources include a quad digital down-converter, a digital upconverter with dual D/A convert-ers, 512 MB DDR SDRAM delay memory and the PCIbus. The FPGA also serves as a control and statusengine with data and programming interfaces to each ofthe on-board resources. Factory-installed FPGA functionsinclude data multiplexing, channel selection, data packing,gating, triggering, and SDRAM memory control.

In addition to acting as a simple transceiver, themodule can perform user-defined DSP functions on thebaseband signals, developed using Penteks GateFlowand ReadyFlow development tools.

The module includes a TI/GC4016 quad digitaldownconverter along with a TI DAC5686 digitalupconverter with dual D/A converters.

Each channel in the downconverter can be set withan independent tuning frequency and bandwidth. Theupconverter translates a real or complex baseband signal toany IF center frequency from DC to 160 MHz and candeliver real or complex (I + Q) analog outputs throughits two 16-bit D/A converters. The digital upconvertercan be bypassed for two interpolated D/A outputs withsampling rates to 500 MHz.

Versions of the 7140 are also available as a PCIboard (Model 7640), 6U cPCI (Models 7240 and7240D dual density), or 3U cPCI (Model 7340). Allthese products have similar features.

VIRTEX-II Pro FPGA

XC2VP50

DSP Channelizer Digital Delay Demodulation Decoding Control etc.Control/

Status

GC4016

4-CHANNEL

DIGITAL

RECEIVER

16

16

16

14

24

FLASH

16 MB

16

DDR

SDRAM

256 MB

DDR

SDRAM

128 MB

DDR

SDRAM

128 MB

32 32 32

PCI 2.2 INTERFACE

(64 Bits / 66 MHz)

PCI BUS

(64 Bits / 66 MHz)

64

TIMING BUS

GENERATOR A

XTL

OSC A

SYNC

INTERRUPTS

& CONTROL

TIMING BUS

GENERATOR B

XTL

OSC B

Sample

Clock B In

Sample

Clock A In

LVDS Clock A

LVDS Sync A

LVDS Gate A

TTL Gate/

Trigger

TTL Sync

LVDS Clock B

LVDS Sync B

LVDS Gate B

Clock/Sync/Gate

Bus A

Clock/Sync/Gate

Bus B

To All

Sections

32

RF XFORMR RF XFORMR

RF Out RF Out

DAC5686

DIGITAL UPCONVERTER

16-bit D/A 16-bit D/A

14

RF

XFORMR

RF

XFORMR

RF In RF In

14

AD6645

105 MHz

14-bit A/D

AD6645

105 MHz

14-bit A/D

P15 XMC

VITA 42.0

(Serial RapidIO,

PCI-Express, etc.)

P4 PMC

FPGA I/O

(Option 104)

648X


21


Products

Transceivers with Dual Wideband DDC and Interpolation Filter Installed Cores

Model 7140-420 PMC/XMC Model 7240-420 6U cPCI

Model 7340-420 3U cPCI Model 7640-420 PCI

Figure 32

The Pentek IP Core 420 includes a dual high-performance wideband DDC and an interpolation filter.Factory-installed in the Model 7140 FPGA, they extendthe range of both the GC4016 ASIC DDC and theDAC5686 DUC.

Like the GC4016, each of the core 420 DDCstranslates any frequency band within the input band-width range down to zero frequency. A complex FIR lowpass filter removes any out-of-band frequency components.An output decimator and formatter deliver either complexor real data. An input gain block scales both I and Qdata streams by a 16-bit gain term.

The mixer utilizes four 18x18-bit multipliers tohandle the complex inputs from the NCO and thecomplex data input samples. The FIR filter is capable ofstoring and utilizing up to four independent sets of18-bit coefficients for each decimation value. Thesecoefficients are user-programmable by using RAMstructures within the FPGA.

The decimation settings of 2, 4, 8, 16, 32, and 64provide output bandwidths from 40 MHz down to1.25 MHz for an A/D sampling of 100 MHz. A multi-plexer in front of the Core 420 DDCs allows data to besourced from either the A/Ds or the GC4016, extendingthe maximum cascaded decimation range to 1,048,576.

The interpolation filter included in the 420 Core,expands the interpolation factor from 2 to 32,768programmable in steps of 2, and relieves the hostprocessor from performing upsampling tasks. Includingthe DUC, the maximum interpolation factor is 32,768which is comparable to the maximum decimation of theGC4016 narrowband DDC.

In addition to the Core 420, all the standardfeatures of the 7140 are retained.

Versions of the 7140-420 are also available as a PCIboard (Model 7640-420), 6U cPCI (Models 7240-420and 7240D-420 dual density), or 3U cPCI (Model7340-420). All these products have similar features.

.

RF

XFORMR

RF

XFORMR

RF

XFORMR

RF

XFORMR

AD6645

105 MHz

14-bit A/D

AD6645

105 MHz

14-bit A/D

CLOCK &

SYNC

GENERATOR

XTAL

OSC A

XTAL

OSC B

MUX

GC4016 DIGITAL

DOWNCONVERTR

DAC 5686

DIGITAL

UPCONVERTER

16-bit

500 MHZ

D/A

16-bit

500 MHZ

D/A

128 MB DDR

SDRAM

128 MB DDR

SDRAM

256 MB DDR

SDRAM

PCI 2.2

INTERFACE

MEMORY

CONTROL

&

DATA ROUTING

MEM W

FIFO

MEM W

FIFO

A/D A

FIFO

A/D B

FIFO

DDC A

FIFO

DDC B

FIFO

DDC C

FIFO

DDC D

FIFO

D/A A

FIFO

D/A B

FIFO

MUX

MUX

CFIR

FILTER

CIC

FILTER

MUX

WIDEBAND

DIGITAL

DOWNCONVERTR A

DECIMATION: 2 64

WIDEBAND

DIGITAL

DOWNCONVERTR A

DECIMATION: 2 64

M

U

X

M

U

X

MUX

CH A

RF In

CH B

RF In

CH A

RF Out

CH B

RF Out

Sample

Clock A In

Clock/Sync

Bus

Sample

Clock B In

A B C D

A B C D

MEMORY

MEMORY

DDC C

DDC D

D/A A

D/A B

A/D A

A/D B

A/D A

A/D B

DDC A

DDC B

A/D A

A/D B

DDC A

DDC BWB DDC A

DDC A

WB DDC B

DDC B

MEMORY

D/A A FIFO

MEMORY

D/A B FIFO

PCI BUS

64 bit /

66 MHz

WIDEBAND DDC CORE

INTERPOLATION CORE

XC2VP50

RF

XFORMR

RF

XFORMR

RF

XFORMR

RF

XFORMR

AD6645

105 MHz

14-bit A/D

AD6645

105 MHz

14-bit A/D

CLOCK &

SYNC

GENERATOR

XTAL

OSC A

XTAL

OSC B

MUX

GC4016 DIGITAL

DOWNCONVERTR

DAC 5686

DIGITAL

UPCONVERTER

16-bit

500 MHZ

D/A

16-bit

500 MHZ

D/A

128 MB DDR

SDRAM

128 MB DDR

SDRAM

256 MB DDR

SDRAM

PCI 2.2

INTERFACE


22


Model 7140-430 PMC/XMC Model 7240-430 6U cPCI

Model 7340-430 3U cPCI Model 7640-430 PCI

Transceivers with 256-Channel Narrowband DDC Installed Core

Products

Figure 33

For applications that require many channels ofnarrowband downconverters, Pentek offers the GateFlowIP Core 430 256-channel digital downconverter bank.Factory installed in the Model 7140 FPGA, Core 430creates a flexible, very high-channel count receiver systemin a small footprint.

Unlike classic channelizer methods, the Pentek 430core allows for completely independent programmabletuning of each individual channel with 32-bit resolutionas well as filter characteristics comparable to manyconventional ASIC DDCs.

Added flexibility comes from programmable globaldecimation settings ranging from 1024 to 8192 in stepsof 256, and 18-bit user programmable FIR decimatingfilter coefficients for the DDCs. Default DDC filtercoefficient sets are included with the core for all possibledecimation settings.

Core 430 utilizes a unique method of channelization.It differs from others in that the channel center frequen-

cies need not be at fixed intervals, and are independentlyprogrammable to any value.

Core 430 DDC comes factory installed in theModel 7140-430. A multiplexer in front of the coreallows data to be sourced from either A/D converterA or B. At the output, a multiplexer allows the 7140-430 to route either the output of the GC4016 or theCore 430 DDC to the PCI Bus.

In addition to the DDC outputs, data from bothA/D channels are presented to the PCI Bus at a rateequal to the A/D clock rate divided by any integer valuebetween 1 and 4096. A TI DAC5686 digital upconverterand dual D/A accepts baseband real or complex data streamsfrom the PCI Bus with signal bandwidths up to 40 MHz.

Versions of the 7140-430 are also available as a PCIboard (Model 7640-430), 6U cPCI (Models 7240-430and 7240D-430 dual density), or 3U cPCI (Model7340-430). All these products have similar features.

.

RF

XFORMR

RF

XFORMR

RF

XFORMR

RF

XFORMR

AD6645

105 MHz

14-bit A/D

AD6645

105 MHz

14-bit A/D

CLOCK &

SYNC

GENERATOR

XTAL

OSC A

XTAL

OSC B

MUX

GC4016 DIGITAL

DOWNCONVERTR

DAC 5686

DIGITAL

UPCONVERTER

16-bit

500 MHZ

D/A

16-bit

500 MHZ

D/A

PCI 2.2

INT

MEM W

FIFO

MEM W

FIFO

D/A A

FIFO

D/A B

FIFO

CH A

RF In

CH B

RF In

CH A

RF Out

CH B

RF Out

Sample

Clock A In

Clock/Sync

Bus

Sample

Clock B In

A B C D

A B C D

DDC 1

Local Oscillator, Mixer, Filter

M

U

X

1

2

255

256

MUX

M

U

X

DDC A

FIFO

DDC B

FIFO

DDC C

FIFO

DDC D

FIFO

OUT A

DDC A

OUT B

DDC B

OUT C

DDC C

OUT D

DDC D

PCI BUS

64 bit /

66 MHz

256 CHANNEL DIGITAL DOWNCONVERTER BANK

CORE

XC2VP50

RF

XFORMR

RF

XFORMR

RF

XFORMR

RF

XFORMR

AD6645

105 MHz

14-bit A/D

AD6645

105 MHz

14-bit A/D

CLOCK &

SYNC

GENERATOR

XTAL

OSC A

XTAL

OSC B

MUX

GC4016 DIGITAL

DOWNCONVERTR

DAC 5686

DIGITAL

UPCONVERTER

16-bit

500 MHZ

D/A

16-bit

500 MHZ

D/A

PCI 2.2

INTERFACE

DDC 1


DDC 255


DDC 256



23


Multiband Transceivers with Virtex-II Pro FPGA

Products

Figure 34

Model 7141PMC/XMC

AD6645

105 MHz

14-BIT A/D

AD6645

105 MHz

14-BIT A/D

TIMING BUS

GENERATOR A

XTL

OSC A

SYNC

INTERRUPTS

& CONTROL

TIMING BUS

GENERATOR B

XTL

OSC B

RF

XFORMR

RF

XFORMR

GC4016

4-CHANNEL

DIGITAL

RECEIVER

VIRTEX-II Pro FPGA

XC2VP50

DSP Channelizer Digital Delay Demodulation Decoding Control etc.

FLASH

16 MB

DDR

SDRAM

256 MB

DDR

SDRAM

128 MB

DDR

SDRAM

128 MBPCI 2.2 INTERFACE

(64 Bits / 66 MHz)

Sample

Clock B In

Sample

Clock A In

LVDS Clock A

LVDS Sync A

LVDS Gate A

TTL Gate/

Trigger

TTL Sync

LVDS Clock B

LVDS Sync B

LVDS Gate B

RF In RF In

Clock/Sync/Gate

Bus A

Clock/Sync/Gate

Bus B

To All

Sections Control/

Status

PCI BUS

(64 Bits / 66 MHz)

P15 XMC

VITA 42.0

(Serial RapidIO,

PCI-Express, etc.)

P4 PMC

FPGA I/O

(Option 104)

14 14

16

16

16

14

24

32

16

32 32 3264 64

RF XFORMR RF XFORMR

RF Out RF Out

DAC5686

DIGITAL UPCONVERTER

16-bit D/A 16-bit D/A

LTC2255

125 MHz

14-bit A/D

LTC2255

125 MHz

14-bit A/D

FRONT

PANEL

CONNECTOR

The Model 7141 PMC/XMC module combinesboth receive and transmit capabilities with a high-performance Virtex II-Pro FPGA and supports theVITA 42 XMC standard with optional switched fabricinterfaces for high-speed I/O.

The front end of the module accepts two RF inputsand transformer-couples them into two 14-bit A/Dconverters running at 125 MHz. The digitized outputsignals pass to a Virtex-II Pro FPGA for signal process-ing or routing to other module resources.

These resources include a quad digital down-converter, a digital upconverter with dual D/A converters,512 MB DDR SDRAM delay memory and the PCIbus. The FPGA also serves as a control and statusengine with data and programming interfaces to each ofthe on-board resources. Factory-installed FPGA functionsinclude data multiplexing, channel selection, data packing,gating, triggering, and SDRAM memory control.

In addition to acting as a simple transceiver, themodule can perform user-defined DSP functions on the

baseband signals, developed using Penteks GateFlowand ReadyFlow development tools.

The module includes a TI/GC4016 quad digitaldownconverter along with a TI DAC5686 digitalupconverter with dual D/A converters.

Each channel in the downconverter can be set withan independent tuning frequency and bandwidth. Theupconverter translates a real or complex baseband signal toany IF center frequency from DC to 160 MHz and candeliver real or complex (I + Q) analog outputs throughits two 16-bit D/A converters. The digital upconvertercan be bypassed for two interpolated D/A outputs withsampling rates to 500 MHz.

Versions of the 7141 are also available as a PCIefull-length board (Models 7741 and 7741D dual density),PCIe half-length board (Model 7841), PCI board(Model 7641), 6U cPCI (Models 7241 and 7241Ddual density), and 3U cPCI (Model 7341).

Model 7141-703 is a conduction-cooled version.

Model 7141 PMC/XMC Model 7241 6U cPCI Model 7341 3U cPCI

Model 7641 PCI Model 7741 Full-length PCIe Model 7841 Half-length PCIe


24


Products

Transceivers with Dual Wideband DDC and Interpolation Filter Installed Cores

Figure 35

.

RF

XFORMR

RF

XFORMR

RF

XFORMR

RF

XFORMR

AD6645

105 MHz

14-bit A/D

AD6645

105 MHz

14-bit A/D

CLOCK &

SYNC

GENERATOR

XTAL

OSC A

XTAL

OSC B

MUX

GC4016 DIGITAL

DOWNCONVERTR

DAC 5686

DIGITAL

UPCONVERTER

16-bit

500 MHZ

D/A

16-bit

500 MHZ

D/A

128 MB DDR

SDRAM

128 MB DDR

SDRAM

256 MB DDR

SDRAM

PCI 2.2

INTERFACE

MEMORY

CONTROL

&

DATA ROUTING

MEM W

FIFO

MEM W

FIFO

A/D A

FIFO

A/D B

FIFO

DDC A

FIFO

DDC B

FIFO

DDC C

FIFO

DDC D

FIFO

D/A A

FIFO

D/A B

FIFO

MUX

MUX

CFIR

FILTER

CIC

FILTER

MUX

WIDEBAND

DIGITAL

DOWNCONVERTR A

DECIMATION: 2 64

WIDEBAND

DIGITAL

DOWNCONVERTR A

DECIMATION: 2 64

M

U

X

M

U

X

MUX

CH A

RF In

CH B

RF In

CH A

RF Out

CH B

RF Out

Sample

Clock A In

Clock/Sync

Bus

Sample

Clock B In

A B C D

A B C D

MEMORY

MEMORY

DDC C

DDC D

D/A A

D/A B

A/D A

A/D B

A/D A

A/D B

DDC A

DDC B

A/D A

A/D B

DDC A

DDC BWB DDC A

DDC A

WB DDC B

DDC B

MEMORY

D/A A FIFO

MEMORY

D/A B FIFO

PCI BUS

64 bit /

66 MHz

WIDEBAND DDC CORE

INTERPOLATION CORE

XC2VP50

RF

XFORMR

RF

XFORMR

RF

XFORMR

RF

XFORMR

LTC2255

125 MHz

14-bit A/D

LTC2255

125 MHz

14-bit A/D

CLOCK &

SYNC

GENERATOR

XTAL

OSC A

XTAL

OSC B

MUX

GC4016 DIGITAL

DOWNCONVERTR

DAC 5686

DIGITAL

UPCONVERTER

16-bit

500 MHZ

D/A

16-bit

500 MHZ

D/A

128 MB DDR

SDRAM

128 MB DDR

SDRAM

256 MB DDR

SDRAM

PCI 2.2

INTERFACE

Model 7141-420 PMC/XMC Model 7241-420 6U cPCI Model 7341-420 3U cPCI

Model 7641-420 PCI Model 7741-420 Full-length PCIe Model 7841-420 Half-length PCIe

The Pentek IP Core 420 includes a dual high-performance wideband DDC and an interpolation filter.Factory-installed in the Model 7141 FPGA, they extendthe range of both the GC4016 ASIC DDC and theDAC5686 DUC.

Each of the core 420 DDCs translates any frequencyband within the input bandwidth range down to zerofrequency. A complex FIR low pass filter removes any out-of-band frequency components. An output decimator andformatter deliver either complex or real data. An input gainblock scales both I and Q data streams by a 16-bit gainterm.

The mixer utilizes four 18x18-bit multipliers tohandle the complex inputs from the NCO and thecomplex data input samples. The FIR filter is capable ofstoring and utilizing up to four independent sets of18-bit coefficients for each decimation value. Thesecoefficients are user-programmable by using RAMstructures within the FPGA.

The decimation settings of 2, 4, 8, 16, 32, and 64provide output bandwidths from 40 MHz down to 1.25MHz for an A/D sampling of 100 MHz. A multiplexerin front of the Core 420 DDCs allows data to be sourcedfrom either the A/Ds or the GC4016, extending themaximum cascaded decimation range to 1,048,576.

The interpolation filter included in the 420 Core,expands the interpolation factor from 2 to 32,768programmable in steps of 2, and relieves the hostprocessor from performing upsampling tasks. Includingthe DUC, the maximum interpolation factor is 32,768which is comparable to the maximum decimation of theGC4016 narrowband DDC.

Versions of the 7141-420 are also available as a PCIefull-length board (Models 7741-420 and 7741D-420 dualdensity), PCIe half-length board (Model 7841-420), PCIboard (Model 7641-420), 6U cPCI (Models 7241-420 and7241D-420 dual density), or 3U cPCI (Model 7341-420).

Model 7141-703-420 is a conduction-cooled version.


25


Transceivers with 256-Channel Narrowband DDC Installed Core

Products

Figure 36

.

RF

XFORMR

RF

XFORMR

RF

XFORMR

RF

XFORMR

AD6645

105 MHz

14-bit A/D

AD6645

105 MHz

14-bit A/D

CLOCK &

SYNC

GENERATOR

XTAL

OSC A

XTAL

OSC B

MUX

GC4016 DIGITAL

DOWNCONVERTR

DAC 5686

DIGITAL

UPCONVERTER

16-bit

500 MHZ

D/A

16-bit

500 MHZ

D/A

PCI 2.2

INT

MEM W

FIFO

MEM W

FIFO

D/A A

FIFO

D/A B

FIFO

CH A

RF In

CH B

RF In

CH A

RF Out

CH B

RF Out

Sample

Clock A In

Clock/Sync

Bus

Sample

Clock B In

A B C D

A B C D

DDC 1


M

U

X

1

2

255

256

MUX

M

U

X

DDC A

FIFO

DDC B

FIFO

DDC C

FIFO

DDC D

FIFO

OUT A

DDC A

OUT B

DDC B

OUT C

DDC C

OUT D

DDC D

PCI BUS

64 bit /

66 MHz

256 CHANNEL DIGITAL DOWNCONVERTER BANK

CORE

XC2VP50

RF

XFORMR

RF

XFORMR

RF

XFORMR

RF

XFORMR

LTC2255

125 MHz

14-bit A/D

LTC2255

125 MHz

14-bit A/D

CLOCK &

SYNC

GENERATOR

XTAL

OSC A

XTAL

OSC B

MUX

GC4016 DIGITAL

DOWNCONVERTR

DAC 5686

DIGITAL

UPCONVERTER

16-bit

500 MHZ

D/A

16-bit

500 MHZ

D/A

PCI 2.2

INTERFACE

DDC 1


DDC 255


DDC 256




For applications that require many channels ofnarrowband downconverters, Pentek offers the GateFlowIP Core 430 256-channel digital downconverter bank.Factory installed in the Model 7141 FPGA, Core 430creates a flexible, very high-channel count receiversystem in a small footprint.

Unlike classic channelizer methods, the Pentek 430core allows for completely independent programmabletuning of each individual channel with 32-bit resolutionas well as filter characteristics comparable to manyconventional ASIC DDCs.

Added flexibility comes from programmable globaldecimation settings ranging from 1024 to 8192 in stepsof 256, and 18-bit user programmable FIR decimatingfilter coefficients for the DDCs. Default DDC filtercoefficient sets are included with the core for all possibledecimation settings.

Core 430 utilizes a unique method of channelization.It differs from others in that the channel center frequen-

cies need not be at fixed intervals, and are independentlyprogrammable to any value.

Core 430 DDC comes factory installed in the Model7141-430. A multiplexer in front of the core allows data to besourced from either A/D converter A or B. At the output, amultiplexer allows the 7141-430 to route either the output ofthe GC4016 or the Core 430 DDC to the PCI Bus.

In addition to the DDC outputs, data from bothA/D channels are presented to the PCI Bus at a rate equalto the A/D clock rate divided by any integer value between1 and 4096. A TI DAC5686 digital upconverter and dualD/A accepts baseband real or complex data streams fromthe PCI Bus with signal bandwidths up to 50 MHz.

Versions of the 7141-430 are also available as a PCIefull-length board (Models 7741-430 and 7741D-430 dualdensity), PCIe half-length board (Model 7841-430), PCIboard (Model 7641-430), 6U cPCI (Models 7241-430 and7241D-430 dual density), or 3U cPCI (Model 7341-430).Model 7141-703-430 is a conduction-cooled version.


26


DDR 2

SDRAM

256 MB

DDR 2

SDRAM

256 MB

DDR 2

SDRAM

256 MB

32 32 32

32

RF

XFORMR

RF Out

DAC5686

DIGITAL

UPCONVERTER

16-bit D/A

RF

XFORMR

LTC2255

125MHz

14-bit A/D

RF In

14

RF

XFORMR

LTC2255

125MHz

14-bit A/D

RF In

14

RF

XFORMR

LTC2255

125MHz

14-bit A/D

RF In

14

RF

XFORMR

LTC2255

125MHz

14-bit A/D

RF In

14

P15 XMC

VITA 42.0

P4 PMC

FPGA I/O

(Option 104)

64

64LOCAL

BUS

VIRTEX-4 FPGA

XC4VFX60 or XC4VFX100

PCI BUS

(64 Bits / 66 MHz)

PCI 2.2

INTERFACE

SERIAL

INTERFACE

32 32 32HI-SPEED

BUSES

VIRTEX-4 FPGA

XC4VSX55

DSP Channelizer Digital Delay Demodulation Decoding Control etc.

Control/

Status

TIMING BUS

GENERATOR A

XTL

OSC A

SYNC

INTERRUPTS

& CONTROL

TIMING BUS

GENERATOR B

XTL

OSC B

LVDS Clock A

LVDS Sync A

LVDS Gate A

TTL Gate/

Trigger

TTL Sync

LVDS Clock B

LVDS Sync B

LVDS Gate B

Clock/Sync/Gate

Bus A

Clock/Sync/Gate

Bus B

To All

Sections

Sample

Clock In

Multichannel Transceivers with Virtex-4 FPGAs

Products

Model 7142PMC/XMC

Figure 37



The Model 7142 is a Multichannel PMC/XMCmodule. It includes four 125 MHz 14-bit A/D convert-ers and one upconverter with a 500 MHz 16-bit D/Aconverter to support wideband receive and transmitcommunication channels.

Two Xilinx Virtex-4 FPGAs are included: anXC4VSX55 or LX100 and an XC4VFX60 or FX100.The first FPGA is used for control and signal processingfunctions, while the second one is used for implement-ing board interface functions including the XMC interface.

It also features 768 MB of SDRAM for implementingup to 2.0 sec of transient capture or digital delay memoryfor signal intelligence tracking applications at 125 MHz.

A 16 MB flash memory supports the boot code forthe two on-board IBM 405 PowerPC microcontrollercores within the FPGA.

A 9-channel DMA controller and 64 bit / 66 MHz PCIinterface assures efficient transfers to and from the module.

A high-performance 160 MHz IP core wideband digitaldownconverter may be factory-installed in the first FPGA.

Two 4X switched serial ports, implemented with theXilinx Rocket I/O interfaces, connect the second FPGAto the XMC connector with two 2.5 GB/sec data linksto the carrier board.

A dual bus system timing generator allows separateclocks, gates and synchronization signals for the A/Dand D/A converters. It also supports large, multichannelapplications where the relative phases must be preserved.

Versions of the 7142 are also available as a PCIe full-length board (Models 7742 and 7742D dual density),PCIe half-length board (Model 7842), PCI board(Model 7642), 6U cPCI (Models 7242 and 7242D dualdensity), and 3U cPCI (Model 7342).


27


Transceivers with Four Multiband DDCs and Interpolation Filter Installed Cores

Products

Figure 38

.

RF

XFORMR

RF

XFORMR

RF

XFORMR

AD6645

105 MHz

14-bit A/D

CLOCK &

SYNC

GENERATOR

DAC 5686

DIGITAL

UPCONVERTER

16-bit

500 MHZ

D/A

PCI 2.2

INTERFACE

MEMORY

CONTROL &

DATA ROUTING

D/A

FIFO

MUXCFIR

FILTER

CIC

FILTER

MUX

DIGITAL

DOWNCONVERTR A

STAGE 1

DECIMATION: 2 256

CH A

RF In

CH B

RF In

RF Out

Sample

Clock In

Clock/Sync

Bus

A/D A

A/D A

A/D B

A/D A

MEMORY

D/A FIFO

PCI BUS

64 bit /

66 MHz

DIGITAL DOWNCONVERTER CORE

INTERPOLATION CORE XC4VSX55

RF

XFORMR

RF

XFORMR

RF

XFORMR

LTC2255

125 MHz

14-bit A/D

CLOCK &

SYNC

GENERATOR

XTAL

OSC A

XTAL

OSC B

DAC 5686

DIGITAL

UPCONVERTER

16-bit

500 MHZ

D/A

PCI 2.2

INTERFACE

LTC2255

125 MHz

14-bit A/D

RF

XFORMR

CH C

RF In

RF

XFORMR

LTC2255

125 MHz

14-bit A/D

RF

XFORMR

CH D

RF In

RF

XFORMR

LTC2255

125 MHz

14-bit A/D

A/D B

A/D C

A/D D

A/D C

A/D D

DIGITAL

DOWNCONVERTR A

STAGE 2

DECIMATION: 1 256

DIGITAL

DOWNCONVERTR B

STAGE 1

DECIMATION: 2 256

A/D A

A/D B

A/D C

A/D D

DIGITAL

DOWNCONVERTR B

STAGE 2

DECIMATION: 1 256

DIGITAL

DOWNCONVERTR C

STAGE 1

DECIMATION: 2 256

A/D A

A/D B

A/D C

A/D D

DIGITAL

DOWNCONVERTR C

STAGE 2

DECIMATION: 1 256

DIGITAL

DOWNCONVERTR D

STAGE 1

DECIMATION: 2 256

A/D A

A/D B

A/D C

A/D D

DIGITAL

DOWNCONVERTR D

STAGE 2

DECIMATION: 1 256

DDC A

MUX

A/D B

DDC B

MUX

A/D C

DDC C

MUX

A/D D

DDC D

D/A

M

U

X

M

U

X

M

U

X

M

U

X

MEM W

FIFO

MEM W

FIFO

A/D A

FIFO

A/D B

FIFO

A/D C

FIFO

A/D D

FIFO

256 MB DDR

SDRAM

256 MB DDR

SDRAM

256 MB DDR

SDRAM



The Pentek IP Core 428 includes four high-performance multiband DDCs and an interpolationfilter. Factory-installed in the Model 7142 FPGA,they add DDCs to the Model 7142 and extend therange of its DAC5686 DUC.

The Core 428 downconverter translates any frequencyband within the input bandwidth range down to zerofrequency. The DDCs consist of two cascaded decimat-ing FIR filters. The decimation of each DDC can be setindependently. After each filter stage is a post filter gainstage. This gain may be used to amplify small signalsafter out-of-band signals have been filtered out.

The NCO provides over 108 dB spurious-freedynamic range (SFDR). The FIR filter is capable ofstoring and utilizing two independent sets of 18-bitcoefficients. These coefficients are user-programmable byusing RAM structures within the FPGA. NCO tuningfrequency, decimation and filter coefficients can bechanged dynamically.

Four identical Core 428 DDCs are factory installedin the 7142-428 FPGA. An input multiplexer allowsany DDC to independently select any of the four A/Dsources. The overal decimation range from 2 to 65,536,programmable in steps of 1, provides output bandwidthsfrom 50 MHz down to 1.52 kHz for an A/D samplingrate of 125 MHz and assuming an 80% filter.

The Core 428 interpolation filter increases thesampling rate of real or complex baseband signals by afactor of 16 to 2048, programmable in steps of 4, andrelieves the host processor from performing upsamplingtasks. The interpolation filter can be used in series withthe DUCs built-in interpolation, creating a maximuminterpolation factor of 32,768.

Versions of the 7142-428 are also available as a PCIefull-length board (Models 7742-428 and 7742D-428 dualdensity), PCIe half-length board (Model 7842-428), PCIboard (Model 7642-428), 6U cPCI (Models 7242-428 and7242D-428 dual density), or 3U cPCI (Model 7342-428).


28


256-Channel DDC Installed Core with Quad 200 MHz, 16-bit A/D

Products

Figure 39

.

RF

XFORMR

RF

XFORMR

AD6645

105 MHz

14-bit A/D

PCI 2.2

INTERFACE

MUXDIGITAL

DOWNCONVERTR

BANK 1: CH 1 - 64

DECIMATION: 128 - 1024

CH A

RF In

CH B

RF In

Sample

Clock In

Sync Bus

A/D A

A/D BI & Q

PCI BUS

64 bit /

66 MHz


XC5VSX95T

RF

XFORMR

RF

XFORMR

ADS5485

200 MHz

16-bit A/D

TIMING BUS

GENERATOR

Clock / Gate /

Sync / PPS

XTAL

OSC

PCI 2.2

INTERFACE

ADS5485

200 MHz

16-bit A/D

RF

XFORMR

CH C

RF In

RF

XFORMR

ADS5485

200 MHz

16-bit A/D

RF

XFORMR

CH D

RF In

RF

XFORMR

ADS5485

200 MHz

16-bit A/D

A/D C

A/D D

DDC BANK 1

MUX

MUX

MUX

M

U

X

M

U

X

M

U

X

M

U

X

A/D A

FIFO

A/D B

FIFO

A/D C

FIFO

A/D D

FIFO

PPS In

TTL In

A/D A

A/D B

A/D C

A/D D

A/D A

A/D B

A/D C

A/D D

A/D A

A/D B

A/D C

A/D D

DIGITAL

DOWNCONVERTR

BANK 2: CH 65 - 128


DIGITAL

DOWNCONVERTR

BANK 3: CH 129 - 192


DIGITAL

DOWNCONVERTR

BANK 4: CH 193 - 256


A/D B

DDC BANK 2

A/D C

DDC BANK 3

A/D D

DDC BANK 4

I & Q

I & Q

I & Q

The Model 7151 PMC module is a 4-channel high-speed digitizer with a factory-installed 256-channelDDC core. The front end of the module accepts fourRF inputs and transformer-couples them into four16-bit A/D converters running at 200 MHz. Thedigitized output signals pass to a Virtex-5 FPGA forrouting, formatting and DDC signal processing.

The Model 7151 employs an advanced FPGA-baseddigital downconverter engine consisting of four identical64-channel DDC banks. Four independently controllableinput multiplexers select one of the four A/Ds as theinput source for each DDC bank. Each of the 256 DDCshas an independent 32-bit tuning frequency setting.

All of the 64 channels within a bank share a commondecimation setting that can range from 128 to 1024,programmable in steps of 64. For example, with a samplingrate of 200 MHz, the available output bandwidthsrange from 156.25 kHz to 1.25 MHz. Each 64-channelbank can have its own unique decimation setting

supporting as many as four different output bandwidthsfor the board.

The decimating filter for each DDC bank accepts aunique set of user-supplied 18-bit coefficients. The 80%default filters deliver an output bandwidth of 0.8*s/N,where N is the decimation setting. The rejection ofadjacent-band components within the 80% output band-width is better than 100 dB.

Each DDC delivers a complex output streamconsisting of 24-bit I + 24-bit Q samples. Any numberof channels can be enabled within each bank, selectablefrom 0 to 64. Each bank includes an output sampleinterleaver that delivers a channel-multiplexed stream forall enabled channels within the bank.

Versions of the 7151 are also available as a PCIefull-length board (Models 7751 and 7751D dual density),PCIe half-length board (Model 7851), PCI board(Model 7651), 6U cPCI (Models 7251 and 7251D dualdensity), or 3U cPCI (Model 7351).

Model 7151 PMC Model 7251 6U cPCI Model 7351 3U cPCI



29


32-Channel DDC Installed Core with Quad 200 MHz, 16-bit A/D

Products

Figure 40

.

RF

XFORMR

RF

XFORMR

AD6645

105 MHz

14-bit A/D

PCI 2.2

INTERFACE

MUXDIGITAL

DOWNCONVERTR

BANK 1: CH 1 - 8

DEC: 16 - 8192

CH A

RF In

CH B

RF In

Sample

Clock In

Sync Bus

A/D A

A/D BI & Q

PCI BUS

64 bit /

66 MHz


XC5VSX95T

RF

XFORMR

RF

XFORMR

ADS5485

200 MHz

16-bit A/D

TIMING BUS

GENERATOR

Clock / Gate /

Sync / PPS

XTAL

OSC

PCI 2.2

INTERFACE

ADS5485

200 MHz

16-bit A/D

RF

XFORMR

CH C

RF In

RF

XFORMR

ADS5485

200 MHz

16-bit A/D

RF

XFORMR

CH D

RF In

RF

XFORMR

ADS5485

200 MHz

16-bit A/D

A/D C

A/D D

BANK 1

MUX

MUX

MUX

M

U

X

M

U

X

M

U

X

M

U

X

A/D A

FIFO

A/D B

FIFO

A/D C

FIFO

A/D D

FIFO

PPS In

TTL In

A/D A

A/D B

A/D C

A/D D

A/D A

A/D B

A/D C

A/D D

A/D A

A/D B

A/D C

A/D D

DIGITAL

DOWNCONVERTR

BANK 2: CH 9 - 16

DEC: 16 - 8192

DIGITAL

DOWNCONVERTR

BANK 3: CH 17 - 24

DEC: 16 - 8192

DIGITAL

DOWNCONVERTR

BANK 4: CH 25 - 32

DEC: 16 - 8192

A/D B

BANK 2

A/D C

BANK 3

A/D D

BANK 4

8 x 4

CHANNEL

SUMMATION

POWER

METER &

THRESHOLD

DETECT

POWER

METER &

THRESHOLD

DETECT

POWER

METER &

THRESHOLD

DETECT

POWER

METER &

THRESHOLD

DETECT

A/D B

I & Q

I & Q

I & Q

SUM

Model 7152 PMC Model 7252 6U cPCI Model 7352 3U cPCI


The Model 7152 PMC module is a 4-channel high-speed digitizer with a factory-installed 32-channel DDCcore. The front end of the module accepts four RFinputs and transformer-couples them into four16-bit A/D converters running at 200 MHz. Thedigitized output signals pass to a Virtex-5 FPGA forrouting, formatting and DDC signal processing.

The Model 7152 employs an advanced FPGA-baseddigital downconverter engine consisting of four identical8-channel DDC banks. Four independently controllableinput multiplexers select one of the four A/Ds as theinput source for each DDC bank. Each of the 32 DDCshas an independent 32-bit tuning frequency setting.

All of the 8 channels within a bank share a commondecimation setting that can range from 16 to 8192,programmable in steps of 8. For example, with a samplingrate of 200 MHz, the available output bandwidths rangefrom 19.53 kHz to 10.0 MHz. Each 8-channel bank can

have its own unique decimation setting supporting asmany as four different output bandwidths for the board.

The decimating filter for each DDC bank accepts a uniqueset of user-supplied 18-bit coefficients. The 80% default filtersdeliver an output bandwidth of 0.8*s/N, where N is thedecimation setting. The rejection of adjacent-band componentswithin the 80% output band-width is better than 100 dB.

Each DDC delivers a complex output stream consist-ing of 24-bit I + 24-bit Q samples. Any number of channelscan be enabled within each bank, selectable from 0 to 8.Each bank includes an output sample interleaver thatdelivers a channel-multiplexed stream for all enabledchannels within the bank. Gain and phase control, powermeters and threshold detectors are included.

Versions of the 7152 are also available as a PCIe full-length board (Models 7752 and 7752D dual density), PCIehalf-length board (Model 7852), PCI board (Model 7652),6U cPCI (Models 7252 and 7252D dual density), or 3UcPCI (Model 7352).


30


4-Channel Beamformer Installed Core with four 200 MHz, 16-bit A/Ds

Products

Figure 41

Model 7153 is a 4-channel, high-speed software radiomodule designed for processing baseband RF or IF signals.It features four 200 MHz 16-bit A/Ds supported by a high-performance 4-channel DDC (digital downconverter)installed core and a complete set of beamforming functions.With built-in multiboard synchronization and an Auroragigabit serial interface, it provides everything needed forimplementing multichannel beamforming systems.

The Model 7153 employs an advanced FPGA-basedDDC engine consisting of four identical multiband banks.Four independently controllable input multiplexers selectone of the four A/Ds as the input source for each DDCbank. Each of the 4 DDCs has an independent 32-bittuning frequency setting.

All four DDCs have a decimation setting that canrange from 2 to 256, programmable independenly insteps of 1. The decimating filter for each DDC bankaccepts a unique set of user-supplied 18-bit coefficients.The 80% default filters deliver an output bandwidth of

0.8*s/N, where N is the decimation setting. Therejection of adjacent-band components within the 80%output band-width is better than 100 dB.

In addition to the DDCs, the 7153 features a com-plete beamforming subsystem. Each channel containsprogramable I & Q phase and gain adjustments followedby a power meter that continuously measures the individualaverage power output. The time constant of the averaginginterval for each meter is programmable up to 8 ksamples.The power meters present average power measurements foreach channel in easy-to-read registers. Each channel alsoincludes a threshold detector that sends an interrupt tothe processor if the average power level of any DDCfalls below or exceeds a programmable threshold.

Versions of the 7153 are also available as a PCIefull-length board (Models 7753 and 7753D dual density),PCIe half-length board (Model 7853), PCI board(Model 7653), 6U cPCI (Models 7253 and 7253Ddual density), or 3U cPCI (Model 7353).



DDC 1

DEC: 2 - 256Gain & Phase Adj

A/D A

A/D B I & Q

PCI-X

I/F

A/D C

A/D D

MU

X

200 MHz16-bit A/D

200 MHz16-bit A/D

200 MHz16-bit A/D

200 MHz16-bit A/D

CH BRF In

CH ARF In

CH DRF In

CH CRF In

SampleClock

Clock& SYNC

Bus

TimingClockSync

Gate /Trigger

PPS

XTAL

OSC

DDC 2


DDC 3


DDC 4


M

U

X

M

UX

M

U

X

MU

X

A/D A

A/D A

A/D B

A/D C

A/D D

M

UX

A/D A

A/D B

A/D C

A/D D

MU

X

A/D A

A/D B

A/D C

A/D D

M

UX

PCI-X

Bus

64-bits

100 MHz

I & Q

I & Q

I & Q

POWER METER

& THRESHOLD

DETECTOR

POWER METER

& THRESHOLDDETECTOR

POWER METER

& THRESHOLDDETECTOR

POWER METER

& THRESHOLD

DETECTOR

SUMMER

DIGITAL DOWN

CONVERTER CORE

XC5VSX50T FPGA

A/D A

A/D B

A/D C

A/D D

A/D B

A/D C

A/D D

AuroraGigabitSerial

Interface

Sum In

Sum Out

P15

XMC

4X

4X


31


Products

Dual SDR Transceivers with 400 MHz A/D, 800 MHz D/A, and Virtex-5 FPGAs

Model 7156PMC/XMC

RF In

14

ADS5474

400 MHz

14-bit A/D

RF

XFORMR

RF In

14

ADS5474

400 MHz

14-bit A/D

RF

XFORMR

TIMING BUS

GENERATOR

Clock/ Sync /

Gate / PPS

Sample Clock In

TTL Gate / Trig

A/D Clock Bus

TTL Sync / PPS

Sample Clk

Sync Clk

sdr principles

Documents

upper saddle river

park way

nyquist zone

benefits of sdr

embedded systems

data systems

radio handbooksamplingfigure

radio handbookbefore