sdram buffer card: 1.0 block diagram 2.0 schematics...

Deepti Electronics & Electro-optics Pvt Ltd. DEC’ 2003

DGC-FD-601 V0.0 /1

INDEX:

SDRAM BUFFER CARD:

1.0 BLOCK DIAGRAM

2.0 SCHEMATICS

3.0 PCB LAYOUT

4.0 ATP

5.0 ATR

SDRAM BUFFER CARD DEC 2003

Deepti Electronics & Electro Optics Pvt Ltd. Raman Research Institute Bangalore. Bangalore.

SDRAM BUFFER CARD

BLOCK DIAGRAM

DEEOPL__RRI_SDRAM BUFFER CARD ver 1.0 June 2003

Deepti Electronics & Electro optics Pvt. Ltd.Bangalore

UTP CON

34 PINBERGCON

UTP CON

16 LVDSPAIRS

16 LVDSPAIRS

16 LVDSPAIRS

34 PINBERGCON

FPGASPARTAN2E 200K

PQ208146(0 FREE)

(2.5V I/O)

2424

32

32

32

3

5 pairs 5 pairs 5 pairs

LVDSSERIALISER

LVDSDESERIALISER

LVDSSERIALISER

CLK

CLK29

JTAG FPGA BOOTPROM (2 nos)

XC95144TQFP117I/O(33 FREE)

(3.3V I/O)

128MBSDRAMSLOT-B

29

CLK

FPGASPARTAN2E200K

PQ208146(0 FREE)

(3.3V I/O)

19

3

15

32DQ(31:0)

VREFA

VREFA

AA(13:0)

BA0ABA1A

RASACASAWEA

DQMA(7:0)

CKEA(1:0)

CSA#(3:0)

29

128MBSDRAMSLOT-B

FPGASPARTAN2E 200K

PQ208146I/O(0 FREE)

(3.3V I/O)

DQ(31:0)

15

VREFB

VREFB

AB(13:0)

BA0BBA1B

RASBCASBWEB

3

32

DQMB(7:0)

CKEB(1:0)

CSB#(3:0)

19

29

1

4CLK DRIVE

4

CLK DRIVE

CLKGENERATOR

1

24

6

20 20

SAB(2:0)

SCLKBSDAB

CBB(7:0)

SAA(2:0)

SCLKASDAA

CBA(7:0)13 13

20

24

CLKA CLKBCLKC

XC95144TQFP117I/O

(2.5V I/O)

POWER SUPPLY INPUTS

3.3V

1.8V

2.5V

Document Number:

Page 1

SCHEMATICS

1

1

2

2

3

3

4

4

5

5

D D

C C

B B

A A

File Name :

0.1

0.20.3

NOTE

SDRAM BUFFER CARD

1 111.0

123001010203A3

REVISION STATUS SHEET

RRI

SIGNATURE

DRAWN

CHECKED

APPROVED

PROJECT TITLE SCHEMATIC DIAGRAM

DEEPTI ELECTRONICS & ELECTRO-OPTICS (P) LTD.,BANGALORE, INDIA SHEET NAME :

SIZE SHEET OFISSUE

DOC.NO. :

DATE

PROJECTION

REVISION

REV DESCRIPTION DATE APPROVAL

REV

SH

REV STATUSOF SHEETS

1

1

2

2

3

3

4

4

5

5

D D

C C

B B

A A

DECOUPLING CAPACITORS FOR CPLD

A3 10 11 123001010203

CPLD & RESISTOR

1.0

SIGNATURE

DRAWN

CHECKED

APPROVED

DATE DEEPTI ELECTRONICS & ELECTRO-OPTICS (P) LTD., BANGALORE, INDIA

SHEET NAME :

SIZE SHEETOF

ISSUE DOC. No. :

3.3V

1.8V

2.5V

VCCO_1

3.3V

VCCO_1

3.3VVCCO_1

VCCO_1

3.3V

VCCO_1

C66

0.1uF

C11

0.1uF

C115

0.1uF

C120

0.1uF

C6

0.1uF

C93

0.1uF

C18

0.1uF

C65

0.1uF

C106

0.1uF

C23

0.1uF

R56 100E

R68 100ER62 100ER59 100E

R32 100ER34 100E

R38 100E

R7 100E

R64 100E

R46 100E

R24 100E

XC95144XV

U14

XC95144XL8 42 84 141

137 55 73 109

127

18 29 36 47 62 72 89 90 99 108

114

123

144

303238

5623143

676312265

2316172519202122312426272835

142479101211131415

39414433344640484345495051 118

126133128129130131135132134137136138139140

5259535466565768586070616469 106

111110112113116115119120121124117125

717574767778807982858186878388

9195979293949610198100103102104107105

VC

CV

CC

VC

CV

CC

VCC

IO2

VCC

IO1

VCC

IO1

VCC

IO1

VCC

IO2

VCC

IO2

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

D

IO/GCK1IO/GCK2IO/GCK3

IO/GTS1IO/GTS2IO/GTS3IO/GTS4IO/GSR

TCKTDI

TDOTMS

IO1IO2IO3IO4IO5IO6IO7IO8IO9IO10IO11IO12IO13IO14

IO15IO16IO17IO18IO19IO20IO21IO22IO23IO24

IO25IO26IO27IO28IO29IO30IO31IO32IO33IO34IO35IO36IO37 IO38


IO53IO54IO55IO56IO57IO58IO59IO60IO61IO62IO63IO64IO65IO66 IO67

IO68IO69IO70IO71IO72IO73IO74IO75IO76IO77IO78IO79

IO80IO81IO82IO83IO84IO85IO86IO87IO88IO89IO90IO91IO92IO93IO94

IO95IO96IO97IO98IO99


R37 1K D5 LED

D7 LEDR45 1K

R51 1K D9 LED

D11 LEDR58 1K

R63 1K D13 LED

R40 100E

R53 100ER50 100ER49 100E

IO_46

IO_6

IO_43

IO_16

IO_41

IO_37

IO_34

IO_20

IO_15

IO_42

IO_23

IO_1

IO_40

IO_17

IO_35

IO_8

IO_22

IO_29

IO_9

IO_19

IO_45IO_26

IO_44

IO_13

IO_10

IO_25

IO_12

IO_7

IO_21

IO_38

IO_39

IO_11

IO_14

IO_24

IO_30

IO_5

IO_48

IO_18

2.5V

3.3V

1.8V

TDO_CPLD1TDO_CPLDTMS_CPLD

TCK_CPLD

IO_27IO_28

IO_32IO_31

IO_33IO_36

IO_47

LVCMOS_IO_4

LVCMOS_IO_21

LVCMOS_IO_1

LVCMOS_IO_5

LVCMOS_IO_28

LVCMOS_IO_42

LVCMOS_IO_3

LVCMOS_IO_15

LVCMOS_IO_30

LVCMOS_IO_19

LVCMOS_IO_24

LVCMOS_IO_7

LVCMOS_IO_44

LVCMOS_IO_29

LVCMOS_IO_36

LVCMOS_IO_6LVCMOS_IO_9


LVCMOS_IO_41

LVCMOS_IO_40

LVCMOS_IO_23

LVCMOS_IO_43

LVCMOS_IO_37

LVCMOS_IO_34

LVCMOS_IO_25

LVCMOS_IO_32


LVCMOS_IO_27

LVCMOS_IO_26

LVCMOS_IO_14

LVCMOS_IO_20

LVCMOS_IO_46

LVCMOS_IO_22

LVCMOS_IO_18

LVCMOS_IO_45

LVCMOS_IO_10

DOUT_CH3

DOUT_CH2

LVCMOS_IO_2

LVCMOS_IO_13

RESET

LVCMOS_IO_8

IO_3

IO_4IO_2

CLK_CPLD2CLK_CPLD1

STATUS_6

STATUS_7

STATUS_10

STATUS_8

CLK

STATUS_9

LVCMOS_IO_38

LVCMOS_IO_33

LVCMOS_IO_17

LVCMOS_IO_11

LVCMOS_IO_31

STATUS_6

STATUS_7

STATUS_8

STATUS_9

STATUS_10

CH1_TOUT2-

CH1_TOUT0-

CH1_TOUT3-

CH1_TOUT1-

CH1_TOUT3+

CH1_TOUT1+CH1_TOUT2+

CH1_TOUT0+

RIN2+RIN3+

RIN0-RIN1-

RIN2-RIN3-

RIN0+RIN1+

CH2_TOUT2+

CH2_TOUT0-CH2_TOUT1-

CH2_TOUT3-CH2_TOUT2-


CH2_TOUT3+

CH1_TCLKOUT+ CH1_TCLKOUT-

CH2_TCLKOUT+ CH2_TCLKOUT-

RCLKIN+RCLKIN-

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

SEIALISERSEIALISER

DESEIALISERSEIALISERSEIALISER

LED INDICATION

RESET CIRCUIT

A3 9 11 123001010203

LVDT SERIALISER & DESERIALISER

1.0

SIGNATURE

DRAWN

CHECKED

APPROVED


SHEET NAME :

SIZE SHEETOF

ISSUE DOC. No. :

GND

GND

GND

GND

GND

3.3V

3.3V

GND

3.3V

GND

3.3V

GND GND

3.3V

GND

3.3V

3.3V

GND

GND

3.3V

GND

3.3V

GND

GND

3.3V

GND

3.3V

GND

3.3V

3.3V

GND

3.3V

GNDGND

GND

3.3V

GND

3.3V

GND GND

3.3V

GND

3.3V

3.3V

GND

GND

3.3V

GND

3.3V

GND

GND

RESET

GND

3.3V

1.8V

2.5V

3.3V

VCCO_1 3.3V

1.8V

1.8V

3.3V

3.3V

3.3V

3.3V2.5V

J9

CON2

12

DS90CR285

U13

DS90CR285TSSOP 56

123456789

101112131415161718192021222324252627

5655545352515049484746454443424140393837363534333231302928

VCCTXIN5TXIN6TXIN7GNDTXIN8TXIN9TXIN10VCCTXIN11TXIN12TXIN13GNDTXIN14TXIN15TXIN16VCCTXIN17TXIN18TXIN19GNDTXIN20TXIN21TXIN22TXIN23VCCTXIN24

TXIN4TXIN3TXIN2

GNDTXIN1TXIN0

TXIN27LVDSGND

TXOUT0-TXOUT0+TXOUT1-TXOUT1+LVDSVCCLVDSGND

TXOUT2-TXOUT2+

TXCLKOUT-TXCLKOUT+

TXOUT3-TXOUT3+

LVDSGNDPLLGNDPLLVCCPLLGND

PWRDWN#TXCLKIN

TXIN26GNDTXIN25

U15

DS90CR286TSSOP 56

123456789

101112131415161718192021222324252627

5655545352515049484746454443424140393837363534333231302928

RxOUT22RxOUT23RxOUT24GNDRxOUT25RxOUT26RxOUT27LVDS GNDRxIN0-RxIN0+RxIN1-RxIN1+LVDS VCCLVDS GNDRxIN2-RxIN2+RxCLKIN-RxCLKIN+RxIN3-RxIN3+LVDS GNDPLL GNDPLL VCCPLL GNDPWRDWNRxCLKOUTRxOUT0

VCCRxOUT21RxOUT20RxOUT19

GNDRxOUT18RxOUT17RxOUT16


GNDRxOUT12RxOUT11RxOUT10


GNDRxOUT6RxOUT5RxOUT4RxOUT3

VCCRxOUT2RxOUT1GND

J8

CON2BERGSTICK

12

C29

0.1uF

C25

0.1uF

C26

0.1uF

C19

0.1uF

C24

0.1uF

C20

0.1uF

R191KSMD 1206

C21

0.1uF

R171KSMD 1206

R181KSMD 1206

D1

LEDSMD 1206

C99

0.1uF

C84

0.1uF

C83

0.1uF

C82

0.1uF

C111

0.1uF

C107

0.1uF

C104

0.1uF

D3

LEDSMD 1206

C54

0.1uF

C79

0.1uF

C85

0.1uF

C80

0.1uF

C76

0.1uF

C56

0.1uF

C55

0.1uF

R7110kSMD 1206

D14

DIODESOD87

C1551µFSMD 1206

SW1

SW PUSHBUTTONKSC351J

D2

LEDSMD 1206

DS90CR285

U12

DS90CR285TSSOP 56

123456789

101112131415161718192021222324252627

5655545352515049484746454443424140393837363534333231302928

VCCTXIN5TXIN6TXIN7GNDTXIN8TXIN9TXIN10VCCTXIN11TXIN12TXIN13GNDTXIN14TXIN15TXIN16VCCTXIN17TXIN18TXIN19GNDTXIN20TXIN21TXIN22TXIN23VCCTXIN24

TXIN4TXIN3TXIN2

GNDTXIN1TXIN0

TXIN27LVDSGND

TXOUT0-TXOUT0+TXOUT1-TXOUT1+LVDSVCCLVDSGND

TXOUT2-TXOUT2+

TXCLKOUT-TXCLKOUT+

TXOUT3-TXOUT3+

LVDSGNDPLLGNDPLLVCCPLLGND

PWRDWN#TXCLKIN

TXIN26GNDTXIN25

J11

CON2

12

J10

CON2

12

ROUT22ROUT23ROUT24

ROUT25ROUT26ROUT27

RIN0+

RIN1+

RIN2-RIN2+

RCLKIN-RCLKIN+

RIN3-RIN3+

RCLKOUTROUT0

RIN0-

RIN1-

CH1_TIN5CH1_TIN6CH1_TIN7

CH1_TIN8CH1_TIN9

CH1_TIN10




CH1_TIN20CH1_TIN21CH1_TIN22CH1_TIN23

CH1_TIN24CH1_TIN25



CH1_TXCLKINCH1_TIN26

CH1_TOUT0-CH1_TOUT0+CH1_TOUT1-CH1_TOUT1+

CH1_TOUT2-CH1_TOUT2+CH1_TCLKOUT-CH1_TCLKOUT+CH1_TOUT3-CH1_TOUT3+

ROUT17

ROUT1

ROUT18

ROUT2

ROUT9

ROUT19

ROUT3

ROUT12

ROUT20

ROUT4

ROUT21

ROUT5

ROUT13

ROUT10

ROUT14

ROUT6

ROUT7

ROUT15

ROUT8

ROUT16

ROUT11


CH2_TIN8CH2_TIN9

CH2_TIN10




CH2_TIN20CH2_TIN21CH2_TIN22CH2_TIN23

CH2_TIN24CH2_TIN25



CH2_TXCLKINCH2_TIN26

CH2_TOUT0-CH2_TOUT0+CH2_TOUT1-CH2_TOUT1+

CH2_TOUT2-CH2_TOUT2+CH2_TCLKOUT-CH2_TCLKOUT+CH2_TOUT3-CH2_TOUT3+

RESET

GND

3.3V

1.8V

2.5V

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

A3 8 11 123001010203

LVDT LINES FPGA

1.0

SIGNATURE

DRAWN

CHECKED

APPROVED


SHEET NAME :

SIZE SHEETOF

ISSUE DOC. No. :

GND

3.3V

1.8V

2.5V

M0_

F3

M2_

F3M

1_F3

M0_F3

M1_F3

M2_F3

2.5V

VCCO_1

3.3V

VCCO_1

1.8V

J7

CON2

123

J13 CON2

1 2J14 CON2

1 2J12 CON2

1 2

BANK7

BANK6

BANK5

BANK4 BANK3

BANK2

BANK1

BANK0

XC2S200E

U5

PQFP-2081

2

3456789

1011

12 13 14

15161718

19

2021222324

25 26

27

28

293031

32

33343536

373839

40414243444546474849

50

51

52

53

54

55565758596061626364

65 66 67

68697071

72

737475

76

77

7879

80 81 82 83 84

8586 87 88 89

909192

93 94 95 96 97 98 99 100

101

102

103

104

105

106

107

108

109

110

111

112

113

114

115

116

117

118

119

120

121

122

123

124

125

126

127

128

129

130

131

132133134135136

137

138139140141

142

143

144

145146147148149150151152

153

154

155

156

157

158

159

160161162163164165166167168169

170

171

172

173174175176

177

178179180181182

183

184

185

186

187188189

190

191192193194

195

196

197

198199200201202203204205206

207

208

37

GN

D

TMS

I/OI/OI/OI/O_VREF_L49PI/O_L49NI/OI/OI/OL48PI/O_L48N

GN

D

VCC

O

VC

CIN

T

I/O_L47PYYI/O_L47N_YYI/O_L46PYYI/O_L46NPYY

GN

D

I/O_VREF_L45PI/O_l45nI/OI/Ol_L44P_YYI/O(IRDY)_L44N_YY

GN

D

VCC

O

I/O(TRDY)

VC

CIN

T

I/OI/O_L43PI/O_VREF_L43N

GN

D

I/O_L42P_YYI/O_L42N_YYI/O_L41P_YYI/O_L41N_YY

VC

CIN

T

VCC

O

GN

D

I/O_L40PI/O_L40NI/OI/OI/OI/O_VREF_L39PI/O_L39NI/OI/O_L38P_YYI/O_L38N_YY

M1

GN

D

M0

VCC

O

M2

I/OL37N_YYI/OL37P_YYI/OI/OI/O_VREF_L36N_YYI/O_L36P_YYI/O_L35NI/O_L35PI/O_L34NI/O_L34P

GN

D

VCC

O

VC

CIN

T

I/O_L33NI/O_L33PI/OI/O_L32N

GN

D

I/O_VREF_L32PI/OI/O_(DLL)_L31N

VC

CIN

T

GCL1_l

VCC

O

GN

D

GC

K0_

lI/O

(DLL

)_L3

1PI/O I/O

_L30

NI/O

_VR

EF_

L30P

GN

DI/O

_L29

NI/O

_29P

I/O_L

28N

I/O_L

28P

VC

CIN

T

VCC

O

GN

D

I/O_L

27N

I/O_L

27P

I/O I/O I/O_L

26N

YY

I/O_V

RE

F_L2

6P_Y

YI/O I/O I/O

_L25

N_Y

YI/O

_L25

P_Y

Y

GN

D

DO

NE

VCC

O

PRO

GR

AM#

I/O(IN

IT#)

_L24

N_Y

Y

I/O(D

7)_L

24P

YY

I/O I/O I/O_V

RE

F_L2

3NI/O

_L23

PI/O I/O I/O

_L22

NI/O

(D6)

_L22

P

GN

D

VCC

O

VC

CIN

T

I/O(D

5)_L

21N

_YY

I/O_L

21P

_YY

I/O_L

20N

_YY

I/O_L

20P

_YY

GN

D

I/O_V

RE

F_L1

9NI/O

(D4)

_L19

P_

I/O

VC

CIN

T

I/O(T

RD

Y)

VCC

O

GN

D

I/O(IRDY)_L18N_YYI/O_L18P_YY

I/OI/O(D3)_L17N

I/O_VREF_L17P

GN

D

I/O_L16N_YYI/O_L16P_YYI/O_L15N_YY

I/O(D2)_L15P_YY

VC

CIN

T

VCC

O

GN

D

I/O(D1)_L14NI/O_L14P

I/OI/OI/O

I/O_VREF_BANK2_L13NI/O_L13P

I/O

I/O(D

IN,D

0)_L

12N

_YY

I/O(D

OU

T,B

US

Y)_

L12P

_YY

CC

LK

VCC

O

TDO

GN

D

TDI

I/O(CS#)_L11P_YYI/O(WRITE#)_L11N_YY

I/OI/O

I/O_VREF_L10P_YYI/O_L10N_YY

I/OI/O

I/O_L9PI/O_L9N

GN

D

VCC

O

VC

CIN

T

I/O_L8PI/O_L8NI/O_L7PI/O_L7N

GN

D

I/O_VREF_L6PI/O_L6N

I/OI/O_DLL)_L5P

GCK2_I

GN

D

VCC

O

GCK3_I

VC

CIN

T

I/O(DLL)_L5NI/O_L4P

I/O_VREF_L4N

GN

D


VC

CIN

T

VCC

O

GN

D

I/O_L1PI/O_L1N

I/OI/O

I/O_L0P_YYI/O_VREF_L0N_YY

I/OI/OI/O

TCK

VCC

O

VC

CIN

T

LVDS_I/O_13_P

LVDS_I/O_4_N

LVDS_I/O_13_N

LVDS_I/O_4_P

LVDS_I/O_14_N

LVDS_I/O_8_PLVDS_I/O_9_N

LVCMOS_IO_36

LVDS_I/O_14_P

LVDS_I/O_15_N

LVDS_I/O_1_N

LVDS_I/O_10_N

LVDS_I/O_6_N

LVDS_I/O_15_P

LVDS_I/O_8_N

LVDS_I/O_2_N

LVDS_I/O_10_P

LVDS_I/O_6_P

LVDS_I/O_16_P

LVDS_I/O_2_P

LVDS_I/O_11_N

LVDS_I/O_7_N

LVDS_I/O_16_N

LVDS_I/O_3_P

LVDS_I/O_0_P

LVDS_I/O_11_P

LVDS_I/O_7_P

LVDS_I/O_1_P

LVDS_I/O_9_P

LVDS_I/O_3_N

LVC

MO

S_I

O_1

6

LVC

MO

S_I

O_1

3

LVC

MO

S_I

O_2

0LV

CM

OS

_IO

_22

LVC

MO

S_I

O_5



LVCMOS_IO_14

LVC

MO

S_I

O_8

GND

3.3V

1.8V

DO

NE

DO

UT_

CH

2D

OU

T_C

H3

CC

LK

TDO

TMS

TCK

TDO

_F2


LVCMOS_IO_43

INIT

#PR

OG

RAM

#

LVDS_I/O_17_NLVDS_I/O_17_P


LVD

S_I

/O_1

9_P

LVD

S_I

/O_2

0_N

LVD

S_I

/O_2

1_P

LVD

S_I

/O_2

2_N

LVD

S_I

/O_2

3_P

LVD

S_I

/O_2

3_N

LVD

S_I

/O_2

5_P

LVD

S_I

/O_2

5_N

LVD

S_I

/O_2

6_P

LVD

S_I

/O_2

6_N

LVD

S_I

/O_2

9_N

LVD

S_I

/O_3

0_N

LVD

S_C

LK0_

N


LVDS_I/O_45_N

LVDS_I/O_34_P

2.5V

LVDS_I/O_47_P

LVDS_I/O_42_P

LVCMOS_IO_18

LVCMOS_IO_35

LVDS_I/O_33_P

LVDS_I/O_49_P

LVDS_I/O_46_P

LVDS_I/O_49_N

LVDS_CLK1_P

LVDS_I/O_37_P

LVDS_I/O_43_N

LVDS_I/O_35_P

LVDS_I/O_39_NLVCMOS_IO_38

LVDS_I/O_32_N

LVDS_CLK1_N

LVCMOS_IO_40

LVDS_I/O_40_N

LVDS_I/O_35_N

LVDS_I/O_33_N

LVDS_I/O_48_N

LVDS_I/O_37_N

LVDS_I/O_48_P

LVDS_I/O_34_N

LVDS_I/O_39_P

LVDS_I/O_38_P

LVCMOS_IO_41

LVDS_I/O_42_N

LVDS_I/O_40_P

LVDS_I/O_0_NLVCMOS_IO_42

LVDS_I/O_38_N

LVCMOS_IO_37

LVDS_I/O_47_N

LVDS_I/O_45_P

LVDS_I/O_36_N

LVDS_CLK2_N

LVDS_I/O_43_P

LVDS_I/O_32_P

LVDS_I/O_46_N

LVDS_I/O_36_P

LVCMOS_IO_15

LVC

MO

S_I

O_2

3

LVC

MO

S_I

O_1

0

LVCMOS_IO_25

LVC

MO

S_I

O_9

LVCMOS_IO_26

LVC

MO

S_I

O_2

4

LVCMOS_IO_27


LVCMOS_IO_3LVCMOS_IO_2LVCMOS_IO_4

LVCMOS_IO_33

LVCMOS_IO_34

LVCMOS_IO_31

LVCMOS_IO_30

LVCMOS_IO_32

LVD

S_C

LK0_

P

RESET

LVDS_CLK2_P

LVCMOS_IO_39

LVCMOS_IO_29

LVCMOS_IO_46

LVCMOS_IO_7

LVC

MO

S_I

O_6

LVD

S_I

/O_3

0_P

LVD

S_I

/O_2

7_P

LVD

S_I

/O_2

8_P

LVD

S_I

/O_2

9_P

LVC

MO

S_I

O_1

9

LVD

S_I

/O_2

8_N

LVD

S_I

/O_2

7_N

LVD

S_I

/O_2

2_P

LVD

S_I

/O_2

1_N

LVD

S_I

/O_1

9_N

LVD

S_I

/O_2

0_P

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

DECOUPLING CAPACITORS FOR FPGA1

DECOUPLING CAPACITORS FOR CPLD


HARDWARE DEBUGGER


JTAGCPLD

NEAR SMD CON

A3 7 11 123001010203

DECOUPLING CAPS & JTAG

1.0

SIGNATURE

DRAWN

CHECKED

APPROVED


SHEET NAME :

SIZE SHEETOF

ISSUE DOC. No. :

GND

3.3V

1.8V

CCLK

DONEDINPROGRAM#

GNDGND

3.3VGND

2.5V

1.8V

3.3V

3.3V3.3V

1.8V

3.3V

3.3V 3.3V

1.8V

VCCO_1

1.8V 2.5V

VCCINT

C59

0.1uF

C64

0.1uF

C9

0.1uF

C58

0.1uF

C7

0.1uF

C34

0.1uF

C35

0.1uF

C42

0.1uF

C57

0.1uF

C36

0.1uF

C46

0.1uF

C77

0.1uF

C62

0.1uF

C37

0.1uF

C5

0.1uF

C90

0.1uF

C87

0.1uF

C47

0.1uF

C10

0.1uF

C33

0.1uF

C53

0.1uF

C86

0.1uF

C151

0.1uF

C135

0.1uF

C131

0.1uF

C149

0.1uF

C13

0.1uF

C105

0.1uF

C119

0.1uF

C148

0.1uF

C100

0.1uF

C114

0.1uF

C103

0.1uF

C126

0.1uF

C14

0.1uF

C102

0.1uF

C101

0.1uF

C153

0.1uF

C130

0.1uF

C152

0.1uF

C22

0.1uF

C143

0.1uF

C150

0.1uF

C142

0.1uF

C12

0.1uF

C134

0.1uF

JP1

JUMPER

1 2

JP5

JUMPER

1 2

C140

0.1uF

C147

0.1uF

C129

0.1uF

C157

0.1uF

C156

47uF

C95

0.1uF

C108

0.1uF

C112

0.1uF

C2

0.1uF

C110

0.1uF

C109

0.1uF

C78

0.1uF

C161

0.1uF

C159

47uF

C4

0.1uF

C63

0.1uF

J4

CON10

123456789

JP2

JUMPER

1 2

C91

0.1uF

C28

0.1uF

C27

0.1uF

C16

0.1uF

C92

0.1uF

C124

0.1uF

C81

0.1uF

C71

0.1uF

C123

0.1uF

C69

0.1uF

C74

0.1uF

C67

0.1uF

C8

0.1uF

C98

0.1uF

C70

0.1uF

C68

0.1uF

C125

0.1uF

C73

0.1uF

C118

0.1uF

C113

0.1uF

C15

0.1uF

C122

0.1uF

C116

0.1uF

C72

0.1uF

C96

0.1uF

C97

0.1uF

C94

0.1uF

JP4

JUMPER

1 2

C75

0.1uF

C17

0.1uF

C61

0.1uF

C136

0.1uF

JP3 FPGA_JTAG

1 23 45 67 89 1011 1213 1415 1617 18

C51

0.1uF

C158

47uF

C160

0.1uF

C88

0.1uF

C32

0.1uF

C38

0.1uF

C89

0.1uF

GND

3.3V

1.8V

TDO

TMS

TDI

TCK

PROGRAM#

DONEDIN

CCLK

TCK_CPLD

TDI_CPLD

TMS_CPLD

TDO_CPLD

TDI TDO_P1

2.5V

TDO_P1 TDO_P2

TDO_F2 TDO

TDI_CPLD TDO_CPLD1

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

CLOCK DRIVER

PROM & DECOUPLING CAPACITORPROM & DECOUPLING CAPACITOR

CLOCK SINTHESIZER CIRCUIT

A3 6 11 123001010203

PROM,CLK SYNTHESER & DRIVER

1.0

SIGNATURE

DRAWN

CHECKED

APPROVED


SHEET NAME :

SIZE SHEETOF

ISSUE DOC. No. :

GND

3.3V

1.8V

2.5V

OSC_CLK

OSC_CLK

3.3V

3.3V

3.3V

3.3V

3.3V

3.3V

3.3V

3.3V

3.3V3.3V

3.3V

R69

4.7K

R30 39.2E

R33 39.2E

C39

2.2uF

U16xc18v04

40

6

29

10

42

18

27

8

9

28

252114

41

19

17

15

16

1343

2635 3638

573

31

D0

GN

D

D1

CF

D2

GN

D

D3

VCC

O

D4

GN

D

D5CEOD6

GN

D

D7

VC

C

CE

VCC

O

OE/RESTCCLK

VCC

O

VC

C

VCC

O

VC

C

TMSTCKTDITDO

C127

0.1uF

C141

0.1uF

C133

0.1uF

C128

0.1uF

C132

0.1uF

C121

0.1uF

C1

2.2uF

C48

0.1uF

R25

10E

C117

0.1uF

R22

10E

CLK

NCGND

VCC

U2

OSC

4

2 1

3

C41

0.1uF

C31

0.1uF

C30

0.1uF

C49

0.1uF

C40

0.1uF

C43

0.1uF

C45

0.1uF

C50

0.1uF

C44

0.1uF

U4

FS6377

1

16

2

3

7

9

4 11

15

13

12

10

5

6

8 14

SDA

SCL

SEL_CD

PD

OE

ADDR

VS

S

VS

S

CLK_A

CLK_B

CLK_C

CLK_D

XIN

XOUT

VD

D

VD

D

R8

4.7K

R70

4.7K

R72

4.7K

R43 39.2ER44 39.2E

R73

4.7K

R29 39.2E

R42 39.2E

R26 39.2ER28 39.2E

U8xc18v04

40

6

29

10

42

18

27

8

9

28

252114

41

19

17

15

16

1343

2635 3638

573

31

D0

GN

D

D1

CF

D2

GN

D

D3

VCC

O

D4

GN

D

D5CEOD6

GN

D

D7

VC

C

CE

VCC

O

OE/RESTCCLK

VCC

O

VC

C

VCC

O

VC

C

TMSTCKTDITDO

R6 47E

R4 47E

R3 47E

R2 47E

R27 39.2E

R36 39.2E

R414.7K

C52

0.1uF

C60

0.1uF

C137

0.1uF

R20

4.7K

U10

PI49FCT3805BQ

23467

1918

1715

14

10

11

1 205 16

912

8

13

OA1OA2OA3OA4OA5

OB1OB2

OB3OB4

OB5

INA

INB

VCC

AVC

CB

GN

DA

GN

DB

OEA#OEB#

GN

DQ

MONR354.7K

C138

0.1uF

C139

0.1uF

C144

0.1uF

C145

0.1uF

C146

0.1uF

C154

0.1uF

R14 100E

Y1

CRYSTAL

R16

4.7K

R1

4.7K

R5 100ER21 100ER15 100E

CLK0_CH2

CLK0_CH1CLK1_CH1CLK2_CH1CLK3_CH1

CLK1_CH2CLK2_CH2

CLKDRIVE_CH2

CLKDRIVE_CH1

PROGRAM#

DIN

INIT#CEO

TMSTCK

TDO_P1TDI

CCLK

GND

3.3V

1.8V

2.5V

PROGRAM#

DIN

INIT#DONE

TMSTCK

TDO_P2TDO_P1

CCLK

CEO

SCL

PD

CLK_DSDA

CLK_CADDR

CLK_A

SEL_CD

CLK_B

OE

CLK_CPLD2

CLK_CPLD1CLK3_CH2

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

SMD CONNECTOR GANG/UTP CONNECTOT

CPLD

TQFP144

OSCILLATOR FOR SYNTHESIZER

A3 5 11 123001010203

CPLD,CONNETORS

1.0

SIGNATURE

DRAWN

CHECKED

APPROVED


SHEET NAME :

SIZE SHEETOF

ISSUE DOC. No. :

GND

3.3V

1.8V

GNDGND

2.5V

CLK

GNDGND

3.3V

VCCINT 3.3V

VCCINT

3.3V

2.5V

3.3V

CLK

NCGND

VCC

U11

OSC

4

2 1

3

U6XC95144XL8 42 84 14

1

1 37 55 73 109

127

18 29 36 47 62 72 89 90 99 108

114

123

144

303238

5623

143

676312265

2316172519202122312426272835

142479

101211131415

39414433344640484345495051

118126133128129130131135132134137136138139140

5259535466565768586070616469

106111110112113116115119120121124117125

717574767778807982858186878388

9195979293949610198100103102104107105

VC

CV

CC

VC

CV

CC

VC

CIO

VC

CIO

VC

CIO

VC

CIO

VC

CIO

VC

CIO

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

D

IO/GCK1IO/GCK2IO/GCK3IO/GTS1IO/GTS2IO/GTS3IO/GTS4IO/GSR

TCKTDI

TDOTMS



IO25IO26IO27IO28IO29IO30IO31IO32IO33IO34IO35IO36IO37



IO67IO68IO69IO70IO71IO72IO73IO74IO75IO76IO77IO78IO79


IO95IO96IO97IO98IO99


GANG CON

J1

CON50A

135791113151719212325272931

2468

101214161820222426283032

GANG CON

J6

CON50A

135791113151719212325272931

2468

101214161820222426283032

C3

0.1uF D4 LEDR31 1K

R39 1K D6 LED

D8 LEDR48 1K

R54 1K D10 LED

D12 LEDR61 1K

J3

CON2

123

J5

CON34A

13579111315171921232527293133

2468

10121416182022242628303234

J2

CON34A

13579111315171921232527293133

2468

10121416182022242628303234

GND

3.3V

1.8V

CON_LVDS_I/O_11_N

CON_LVDS_I/O_9_NCON_LVDS_I/O_10_N

CON_LVDS_I/O_0_N

CON_LVDS_I/O_4_N

CON_LVDS_I/O_8_N

CON_LVDS_I/O_0_P

CON_LVDS_I/O_4_P

CON_LVDS_I/O_9_P

CON_LVDS_I/O_11_P

CON_LVDS_I/O_8_P

CON_LVDS_I/O_10_P

CON_LVDS_I/O_45_P

CON_LVDS_I/O_42_P

CON_LVDS_I/O_47_P

CON_LVDS_I/O_49_P

CON_LVDS_I/O_43_PCON_LVDS_I/O_44_P

CON_LVDS_I/O_46_P

CON_LVDS_I/O_48_P

CH1_TOUT3+

CH1_TOUT0+CH1_TOUT1+CH1_TOUT2+


CH2_TOUT2- CH2_TOUT2+

CH1_TCLKOUT+


CON_LVDS_I/O_23_N

CON_LVDS_I/O_33_N


CON_LVDS_I/O_20_N

CON_LVDS_I/O_25_P

CON_LVDS_I/O_33_P

CON_LVDS_I/O_30_PCON_LVDS_I/O_32_P

CON_LVDS_I/O_29_P

CON_LVDS_I/O_20_P

RIN0+

RCLKIN+

RIN0-

RCLKIN-

RIN1-RIN2-

RIN1+RIN2+

RIN3+

2.5V

CH1_TOUT0-

CON_LVDS_I/O_42_N

CON_LVDS_I/O_48_N

CON_LVDS_I/O_45_N

CON_LVDS_I/O_49_N

CON_LVDS_I/O_43_N

CH1_TOUT1-

CH1_TOUT3-

RIN3-

CH2_TOUT0-


CH1_TOUT2-

CON_LVDS_I/O_44_NCH2_TOUT1-

SA1_CH2

ROUT4

SDA_CH1

ROUT2

ROUT3

ROUT6

SCLK_CH1

ROUT1

ROUT7

CB0_CH1

CB1_CH1

CB7_CH1CB6_CH1

SA0_CH2

SCLK_CH2

SDA_CH2

SA2_CH2

LB16

LB17

LB15

LB12

LB19

LB13

LB14

LB11

LB8

TDI_CPLDTDO_CPLD1TMS_CPLD

TCK_CPLDSDA

PDADDR

ROUT16

ROUT21

CB2_CH2

CB5_CH2

CB4_CH2

ROUT25

OE

ROUT11

ROUT12

SCL

ROUT17

ROUT27

ROUT20

ROUT22ROUT23

ROUT18

ROUT13

ROUT10

SEL_CD

CB0_CH2

ROUT14

CB1_CH2

ROUT19

ROUT24

CB7_CH2

CB2_CH1

CB3_CH2

CON_LVDS_I/O_34_NCON_LVDS_I/O_34_PCON_LVDS_I/O_35_P CON_LVDS_I/O_35_N

CON_LVDS_I/O_36_NCON_LVDS_I/O_36_PCON_LVDS_I/O_37_P CON_LVDS_I/O_37_NCON_LVDS_I/O_38_P CON_LVDS_I/O_38_N

CON_LVDS_I/O_39_NCON_LVDS_I/O_39_PCON_LVDS_I/O_40_NCON_LVDS_I/O_40_P

CON_LVDS_CLK1_P CON_LVDS_CLK1_N

ROUT15

CB5_CH1

ROUT8

ROUT9

SA0_CH1

SA1_CH1SA2_CH1

LB0

LB2

LB18

LB1

LB4LB3

LB5

LB6LB10

ROUT5

CB6_CH2

CON_LVDS_I/O_21_NCON_LVDS_I/O_21_P

CON_LVDS_CLK0_NCON_LVDS_CLK0_P

RCLKOUT

ROUT26

CH1_TCLKOUT-

LB7LB9

CON_LVDS_I/O_7_P

CON_LVDS_CLK2_PCON_LVDS_I/O_6_P

CON_LVDS_CLK2_N


CON_LVDS_I/O_1_P CON_LVDS_I/O_1_N

RESET

CB4_CH1

CLK_DCLK_C

CLK

CLK_DCLK_CCON_LVDS_I/O_2_P

CON_LVDS_I/O_3_PCON_LVDS_I/O_2_NCON_LVDS_I/O_3_N

STATUS_1

STATUS_2

STATUS_3

STATUS_4

STATUS_5

STATUS_1

STATUS_2

STATUS_3

STATUS_5

ROUT0

CB3_CH1

CON_LVDS_I/O_28_P CON_LVDS_I/O_28_NCON_LVDS_I/O_27_P CON_LVDS_I/O_27_NCON_LVDS_I/O_26_P CON_LVDS_I/O_26_NCON_LVDS_I/O_17_P CON_LVDS_I/O_17_N

CON_LVDS_I/O_18_NCON_LVDS_I/O_18_PCON_LVDS_I/O_19_N


CON_LVDS_I/O_19_P

CH2_TOUT3+CH2_TCLKOUT+

CH2_TOUT3-CH2_TCLKOUT-


CON_LVDS_I/O_16_P CON_LVDS_I/O_16_NCON_LVDS_I/O_15_NCON_LVDS_I/O_15_P


STATUS_4

CON_LVDS_I/O_23_P

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

A3 4 11 123001010203

DIMM SLOTS

1.0

SIGNATURE

DRAWN

CHECKED

APPROVED


SHEET NAME :

SIZE SHEETOF

ISSUE DOC. No. :

GND

3.3V

1.8V

GND

GND

3.3V

GND

GND

3.3V

GND

3.3V

GND

3.3V

GND

3.3V

3.3V

3.3V

GND

3.3V

GND

3.3V

GND

3.3V

GND

GND

3.3V3.3V

GND

3.3V

GND

GND

GND

3.3V

GND

3.3V

3.3V

GND

3.3V

GND

GND

3.3V

GND

3.3V

3.3V

3.3V

3.3V

3.3V

3.3V

3.3V

GND

3.3V

GND

3.3V

GND

GND

GND

GND

GND

3.3V

GND

GND

GND GND

GND

3.3V

GND

3.3V

3.3V

3.3V

3.3V

3.3V

GND

GND

2.5V

DIMMSOCKET

DIMM SLOT U1

123456789

10111213141516171819202122232425262728293031323334353637383940414243

4647

4445

48495051525354555657585960616263646566676869707172737475767778798081828384

8687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168

85VssDQ0DQ1DQ2DQ3VddDQ4DQ5DQ6DQ7DQ8VssDQ9DQ10DQ11DQ12DQ13VddDQ14DQ15*CB0*CB1VssNCNCVddWEDQM0DQM1CS0DUVssA0A2A4A6A8A10/APBA1VddVddCLK0Vss

DQM2DQM3

DUCS2

DUVddNCNC*CB2*CB3VssDQ16DQ17DQ18DQ19VddDQ20NC*Vref*CKE1VssDQ21DQ22DQ23VssDQ24DQ25DQ26DQ27VddDQ28DQ29DQ30DQ31VssCLK2NCNC**SDA**SCLVdd

DQ32DQ33DQ34DQ35

VddDQ36DQ37DQ38DQ39DQ40

VssDQ41DQ42DQ43DQ44DQ45

VddDQ46DQ47*CB4*CB5

VssNCNC

VddCAS

DQM4DQM5*CS1RASVssA1A3A5A7A9

BA0A11Vdd

*CLK1*A12Vss

CKE0*CS3

DQM6DQM7

*A13VddNCNC

*CB6*CB7

VssDQ48DQ49DQ50DQ51

VddDQ52

NC*Vref

NCVss

DQ53DQ54DQ55

VssDQ56DQ57DQ58DQ59

VddDQ60DQ61DQ62DQ63

Vss*CLK3

NC**SA0**SA1**SA2

Vdd

Vss

DIMMSOCKET

DIMM SLOT U9

123456789

10111213141516171819202122232425262728293031323334353637383940414243

4647

4445

48495051525354555657585960616263646566676869707172737475767778798081828384

8687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168

85VssDQ0DQ1DQ2DQ3VddDQ4DQ5DQ6DQ7DQ8VssDQ9DQ10DQ11DQ12DQ13VddDQ14DQ15*CB0*CB1VssNCNCVddWEDQM0DQM1CS0DUVssA0A2A4A6A8A10/APBA1VddVddCLK0Vss

DQM2DQM3

DUCS2

DUVddNCNC*CB2*CB3VssDQ16DQ17DQ18DQ19VddDQ20NC*Vref*CKE1VssDQ21DQ22DQ23VssDQ24DQ25DQ26DQ27VddDQ28DQ29DQ30DQ31VssCLK2NCNC**SDA**SCLVdd

DQ32DQ33DQ34DQ35

VddDQ36DQ37DQ38DQ39DQ40

VssDQ41DQ42DQ43DQ44DQ45

VddDQ46DQ47*CB4*CB5

VssNCNC

VddCAS

DQM4DQM5*CS1RASVssA1A3A5A7A9

BA0A11Vdd

*CLK1*A12Vss

CKE0*CS3

DQM6DQM7

*A13VddNCNC

*CB6*CB7

VssDQ48DQ49DQ50DQ51

VddDQ52

NC*Vref

NCVss

DQ53DQ54DQ55

VssDQ56DQ57DQ58DQ59

VddDQ60DQ61DQ62DQ63

Vss*CLK3

NC**SA0**SA1**SA2

Vdd

Vss

A1_CH1A3_CH1A5_CH1A7_CH1

A11_CH1

A12_CH1

A13_CH1

A9_CH1BA0_CH1

RAS#_CH1

CAS#_CH1

CLK3_CH1

CLK1_CH1

GND

3.3V

1.8V

DQM1_CH1DQM4_CH1DQM5_CH1

DQM3_CH1DQM6_CH1DQM7_CH1

CKE0_CH1

CB6_CH1

CB4_CH1CB5_CH1

CB7_CH1

CS3#_CH1

CS1#_CH1

A0_CH2A2_CH2A4_CH2A6_CH2A8_CH2

A1_CH2A3_CH2A5_CH2A7_CH2

A11_CH2

A12_CH2

A13_CH2

A9_CH2A10_CH2

CS0#_CH2

BA1_CH2

CLK0_CH2

CS2#_CH2

BA0_CH2

RAS#_CH2

CAS#_CH2

CLK2_CH2 CLK3_CH2

CLK1_CH2

DQM0_CH2DQM1_CH2

DQM4_CH2DQM5_CH2

DQM2_CH2DQM3_CH2

DQM6_CH2DQM7_CH2

CKE0_CH2CS3#_CH2

CKE1_CH2

CS1#_CH2

WE#_CH2

DQ10_CH2DQ11_CH2DQ12_CH2

DQ14_CH2

DQ13_CH2

DQ9_CH2


DQ4_CH2

DQ1_CH2

DQ3_CH2DQ2_CH2

DQ5_CH2

DQ0_CH2

DQ15_CH2

CB1_CH2CB0_CH2

CB5_CH2

CB3_CH2

CB4_CH2

CB6_CH2CB2_CH2CB7_CH2

SA0_CH1SA1_CH1SA2_CH1

SA0_CH2SA1_CH2SA2_CH2

SDA_CH2SCLK_CH2

DQ16_CH1DQ17_CH1

DQ19_CH1DQ18_CH1

DQ20_CH1

DQ29_CH1DQ28_CH1

DQ30_CH1DQ31_CH1


DQ24_CH1


DQ16_CH2DQ17_CH2

DQ19_CH2DQ18_CH2

DQ20_CH2

DQ22_CH2DQ21_CH2

DQ27_CH2

DQ25_CH2DQ24_CH2

DQ26_CH2

DQ23_CH2


DQ28_CH2

CS2#_CH1

CB3_CH1

DQ5_CH1

A4_CH1

CKE1_CH1

DQ4_CH1

DQ8_CH1

A6_CH1

DQ13_CH1

DQ6_CH1

CB1_CH1

A8_CH1

DQ9_CH1

CB0_CH1

DQM0_CH1

SCLK_CH1

A10_CH1

DQ7_CH1

DQ10_CH1

WE#_CH1

DQ0_CH1

DQ11_CH1

CS0#_CH1

SDA_CH1

DQ1_CH1

DQ12_CH1

DQ15_CH1

CB2_CH1

CLK2_CH1

BA1_CH1

DQ3_CH1

DQ14_CH1

A0_CH1

CLK0_CH1

DQM2_CH1

DQ2_CH1

A2_CH1

2.5V

DQ5_CH1

DQ4_CH1

DQ8_CH1

DQ13_CH1

DQ6_CH1

DQ9_CH1

DQ7_CH1

DQ10_CH1

DQ0_CH1

DQ11_CH1

DQ1_CH1

DQ12_CH1

DQ15_CH1

DQ3_CH1

DQ14_CH1

DQ2_CH1

DQ16_CH1DQ17_CH1

DQ19_CH1DQ18_CH1

DQ20_CH1

DQ29_CH1DQ28_CH1

DQ30_CH1DQ31_CH1


DQ24_CH1DQ23_CH1DQ22_CH1DQ21_CH1

DQ10_CH2DQ11_CH2

DQ12_CH2

DQ14_CH2DQ13_CH2

DQ8_CH2

DQ7_CH2DQ6_CH2

DQ4_CH2

DQ1_CH2

DQ3_CH2DQ2_CH2

DQ5_CH2

DQ0_CH2

DQ15_CH2

DQ9_CH2

DQ16_CH2DQ17_CH2

DQ19_CH2DQ18_CH2

DQ20_CH2

DQ22_CH2DQ21_CH2

DQ23_CH2

DQ27_CH2

DQ25_CH2

DQ24_CH2

DQ26_CH2

DQ29_CH2

DQ30_CH2DQ31_CH2

DQ28_CH2

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

I/O 47 & I/O18 NOT THERE

A3 3 11 123001010203

CH2 FPGA

1.0

SIGNATURE

DRAWN

CHECKED

APPROVED


SHEET NAME :

SIZE SHEETOF

ISSUE DOC. No. :

GND

3.3V

1.8V

2.5V

M2_

CH

2M

1_C

H2

M0_

CH

2

M0_CH2

M1_CH2

M2_CH2

1.8V3.3V

R23

RESISTOR

J15 CON2

1 2J16 CON2

1 2J17 CON2

1 2

BANK7

BANK6

BANK5

BANK4 BANK3

BANK2

BANK1

BANK0

XC2S200E

U3

PQFP-2081

2

3456789

1011

12 13 14

15161718

19

2021222324

25 26

27

28

293031

32

33343536

37383940414243444546474849

50

51

52

53

54

55565758596061626364

65 66 67

68697071

72

737475

76

777879

80 81 82 83 84

8586 87 88 89

909192

93 94 95 96 97 98 99 100

101

102

103

104

105

106

107

108

109

110

111

112

113

114

115

116

117

118

119

120

121

122

123

124

125

126

127

128

129

130

131

132133134135136

137

138139140141

142

143

144

145146147148149150151152

153

154

155

156

157

158

159

160161162163164165166167168169

170

171

172

173174175176

177

178179180181182

183

184

185

186

187188189

190

191192193194

195

196

197

198199200201202203204205206

207

208

37

GN

D

TMS


GN

D

VCC

O

VC

CIN

T


GN

D

I/O_VREF_L45PI/O_l45nI/OI/Ol_L44P_YYI/O(IRDY)_L44N_YY

GN

D

VCC

O

I/O(TRDY)

VC

CIN

T


GN

D


VC

CIN

T

VCC

O

GN

DI/O_L40PI/O_L40NI/OI/OI/OI/O_VREF_L39PI/O_L39NI/OI/O_L38P_YYI/O_L38N_YY

M1

GN

D

M0

VCC

O

M2


GN

D

VCC

O

VC

CIN

T


GN

D


VC

CIN

T

GCL1_lVC

CO

GN

D

GC

K0_

lI/O

(DLL

)_L3

1PI/O I/O

_L30

NI/O

_VR

EF_

L30P

GN

DI/O

_L29

NI/O

_29P

I/O_L

28N

I/O_L

28P

VC

CIN

T

VCC

O

GN

D

I/O_L

27N

I/O_L

27P

I/O I/O I/O_L

26N

YY

I/O_V

RE

F_L2

6P_Y

YI/O I/O I/O

_L25

N_Y

YI/O

_L25

P_Y

Y

GN

D

DO

NE

VCC

O

PRO

GR

AM#

I/O(IN

IT#)

_L24

N_Y

Y

I/O(D

7)_L

24P

YY

I/O I/O I/O_V

RE

F_L2

3NI/O

_L23

PI/O I/O I/O

_L22

NI/O

(D6)

_L22

P

GN

D

VCC

O

VC

CIN

T

I/O(D

5)_L

21N

_YY

I/O_L

21P

_YY

I/O_L

20N

_YY

I/O_L

20P

_YY

GN

D

I/O_V

RE

F_L1

9NI/O

(D4)

_L19

P_

I/O

VC

CIN

T

I/O(T

RD

Y)

VCC

O

GN

D


I/OI/O(D3)_L17N

I/O_VREF_L17P

GN

D


I/O(D2)_L15P_YY

VC

CIN

T

VCC

O

GN

D


I/OI/OI/O


I/O

I/O(D

IN,D

0)_L

12N

_YY

I/O(D

OU

T,B

US

Y)_

L12P

_YY

CC

LK

VCC

O

TDO

GN

D

TDI


I/OI/O


I/OI/O

I/O_L9PI/O_L9N

GN

D

VCC

O

VC

CIN

T


GN

D

I/O_VREF_L6PI/O_L6N

I/OI/O_DLL)_L5P

GCK2_I

GN

D

VCC

O

GCK3_I

VC

CIN

T

I/O(DLL)_L5NI/O_L4P

I/O_VREF_L4NG

ND


VC

CIN

T

VCC

O

GN

D

I/O_L1PI/O_L1N

I/OI/O


I/OI/OI/O

TCK

VCC

O

VC

CIN

T

GND

3.3V

1.8V

2.5V

IO_2

9

CH2_TIN2

CH2_TIN8

IO_2

5

IO_2

8

CH2_TIN3

CH2_TIN26

IO_3

0

LB15

LB7

WE#_CH2

CH2_TIN10

CH2_TIN0

IO_2

7

DQ24_CH2

DQ27_CH2

CH2_TIN1

CH2_TIN7

DQ30_CH2

IO_3

3

CH2_TXCLKIN

DQ25_CH2

CH2_TIN22

LB6

CH2_TIN13

LB8

IO_4

5

DQ21_CH2

IO_3

9

IO_4

4

CH2_TIN4

IO_2

6

CH2_TIN11

DQ23_CH2

CH2_TIN6

IO_4

3

CH2_TIN27

DQ28_CH2

IO_4

2

CH2_TIN5

IO_3

2

IO_4

1

CH2_TIN9

DQ29_CH2

CH2_TIN12

DQ31_CH2

IO_3

1

DQ26_CH2

DQ13_CH2

DQM4_CH2

CKE1_CH2

A5_CH2

DQ16_CH2

DQ2_CH2

DQ20_CH2

DQ14_CH2

RAS#_CH2

A13_CH2

DQM2_CH2

A6_CH2

DQ22_CH2

A3_CH2

DQ3_CH2

DQ19_CH2

DQ9_CH2

CS0#_CH2

A4_CH2

DQ1_CH2

BA1_CH2

DQM3_CH2

CAS#_CH2

CLKDRIVE_CH2

A2_CH2

DQ17_CH2

CS3#_CH2

DQ4_CH2

CLK_B

A8_CH2

DQ10_CH2

A9_CH2

CS1#_CH2

DQ12_CH2

A1_CH2

DQ7_CH2

A0_CH2

DQ18_CH2

A7_CH2

DQ5_CH2

BA0_CH2A11_CH2

DQM6_CH2

DQ15_CH2

DQ8_CH2

A10_CH2

DQM7_CH2

DQ6_CH2

DQ11_CH2

LB18

LB2

IO_3

8

INIT

#

LB4

DO

UT_

CH

2C

CLK

PRO

GR

AM#

DO

UT_

CH

1

TDO

_F1

LB5

TCK

DO

NE

TDO

_F2

TMS

IO_3

6

IO_47

CH2_TIN16CH2_TIN15

CH2_TIN14

CH2_TIN17

CH2_TIN21IO_40

LB14

CH2_TIN25

IO_3

4

IO_4

6

LB3

CH

2_TI

N19

CH

2_TI

N18

DQ

M5_

CH

2

LB11

DQ

0_C

H2

LB10

IO_3

5

IO_3

7

LB9

CH

2_TI

N23

LB13

LB12

CH

2_TI

N24

LB0

SDR

AM_C

LK1_

FBK_

RES

CH2_TIN20IO

_48

LB16

LB19

LB17

DQM1_CH2DQM0_CH2

RESET

LB1

CS2#_CH2

CK

E0_

CH

2

SDRAM_CLK1_FBK

A12_CH2

SDRAM_CLK1_FBK SDRAM_CLK1_FBK_RES

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

A3 2 11 123001010203

CH1 FPGA

1.0

SIGNATURE

DRAWN

CHECKED

APPROVED


SHEET NAME :

SIZE SHEETOF

ISSUE DOC. No. :

M0_

CH

1

M2_

CH

1M

1_C

H1

GND

3.3V

1.8V

2.5V

M1_CH1

M2_CH1

M0_CH11.8V3.3V

J18 CON2

1 2J19 CON2

1 2J20 CON2

1 2

R57

RESISTOR

BANK7

BANK6

BANK5

BANK4 BANK3

BANK2

BANK1

BANK0

XC2S200E

U7

PQFP-2081

2

3456789

1011

12 13 14

15161718

192021222324

25 26

27

28

293031

32

33343536

373839

40414243444546474849

50

51

52

53

54

55565758596061626364

65 66 67

68697071

72

737475

76

77

7879

80 81 82 83 84

8586 87 88 89

909192

93 94 95 96 97 98 99 100

101

102

103

104

105

106

107

108

109

110

111

112

113

114

115

116

117

118

119

120

121

122

123

124

125

126

127

128

129

130

131

132133134135136

137

138139140141

142

143

144

145146147148149150151152

153

154

155

156

157

158

159

160161162163164165166167168169

170

171

172

173174175176

177

178179180181182

183

184

185

186

187188189

190

191192193194

195

196

197

198199200201202203204205206

207

208

37

GN

D

TMS


GN

D

VCC

O

VC

CIN

T


GN

DI/O_VREF_L45PI/O_l45nI/OI/Ol_L44P_YYI/O(IRDY)_L44N_YY

GN

D

VCC

O

I/O(TRDY)

VC

CIN

T


GN

D


VC

CIN

T

VCC

O

GN

D

I/O_L40PI/O_L40NI/OI/OI/OI/O_VREF_L39PI/O_L39NI/OI/O_L38P_YYI/O_L38N_YY

M1

GN

D

M0

VCC

O

M2


GN

D

VCC

O

VC

CIN

T


GN

D


VC

CIN

T

GCL1_l

VCC

O

GN

D

GC

K0_

lI/O

(DLL

)_L3

1PI/O I/O

_L30

NI/O

_VR

EF_

L30P

GN

DI/O

_L29

NI/O

_29P

I/O_L

28N

I/O_L

28P

VC

CIN

T

VCC

O

GN

D

I/O_L

27N

I/O_L

27P

I/O I/O I/O_L

26N

YY

I/O_V

RE

F_L2

6P_Y

YI/O I/O I/O

_L25

N_Y

YI/O

_L25

P_Y

Y

GN

D

DO

NE

VCC

O

PRO

GR

AM#

I/O(IN

IT#)

_L24

N_Y

Y

I/O(D

7)_L

24P

YY

I/O I/O I/O_V

RE

F_L2

3NI/O

_L23

PI/O I/O I/O

_L22

NI/O

(D6)

_L22

P

GN

D

VCC

O

VC

CIN

T

I/O(D

5)_L

21N

_YY

I/O_L

21P

_YY

I/O_L

20N

_YY

I/O_L

20P

_YY

GN

D

I/O_V

RE

F_L1

9NI/O

(D4)

_L19

P_

I/O

VC

CIN

T

I/O(T

RD

Y)

VCC

O

GN

D


I/OI/O(D3)_L17N

I/O_VREF_L17P

GN

D


I/O(D2)_L15P_YY

VC

CIN

T

VCC

O

GN

D


I/OI/OI/O


I/O

I/O(D

IN,D

0)_L

12N

_YY

I/O(D

OU

T,B

US

Y)_

L12P

_YY

CC

LK

VCC

O

TDO

GN

D

TDI


I/OI/O


I/OI/O

I/O_L9PI/O_L9N

GN

D

VCC

O

VC

CIN

T


GN

D

I/O_VREF_L6PI/O_L6N

I/OI/O_DLL)_L5P

GCK2_I

GN

D

VCC

O

GCK3_I

VC

CIN

T

I/O(DLL)_L5NI/O_L4P

I/O_VREF_L4N

GN

D


VC

CIN

T

VCC

O

GN

D

I/O_L1PI/O_L1N

I/OI/O


I/OI/OI/O

TCK

VCC

O

VC

CIN

T

GND

3.3V

1.8V

2.5V

DQ31_CH1

IO_5IO_6

IO_22

IO_24

A13_CH1

CS2#_CH1

DQ19_CH1DQ18_CH1

DQ20_CH1

DQ21_CH1


DQ22_CH1

DQ17_CH1DQ16_CH1

DQ26_CH1

DQ29_CH1

DQ27_CH1DQ28_CH1

DQ30_CH1

DQM2_CH1

DQM6_CH1

DQM3_CH1

DQM7_CH1

IO_20

IO_13

IO_7

IO_8

IO_10

IO_23

IO_12IO_3

IO_4IO_2

CH1_TIN6

CH1_TIN7CH1_TIN8

CH1_TIN5

CH1_TIN4CH1_TIN3

LB12

IO_9

IO_19

DO

UT_

CH

1D

IN

DO

NE

CC

LKIN

IT#

PRO

GR

AM#

TMS

TDO

_F1

TDO

_P2

TCK

A0_

CH

1

CS1

#_C

H1

CS0

#_C

H1

CS3#_CH1

A1_

CH

1A

2_C

H1

A3_

CH

1A

4_C

H1

CKE0_CH1

DQ

10_C

H1

DQ

7_C

H1

DQ

11_C

H1

DQ

12_C

H1

DQ

6_C

H1

DQ

9_C

H1

DQ

8_C

H1

DQ

13_C

H1

DQ

M1_

CH

1

DQ

M4_

CH

1

DQ

M5_

CH

1

DQ

14_C

H1

DQ

M0_

CH

1

RA

S#_

CH

1

CH1_TIN19

CH1_TIN9

CH1_TXCLKIN

CLK_A

CLKDRIVE_CH1

LB3LB2LB1

LB6

LB4

LB7LB5

LB8LB15

IO_1

IO_17

DQ

2_C

H1

DQ

4_C

H1

DQ

5_C

H1

DQ

3_C

H1

DQ

1_C

H1

LB10

CH1_TIN17IO_16

LB11

LB9

CH1_TIN2CH1_TIN1

LB13

CH1_TIN27CH1_TIN11

CH1_TIN15

CH1_TIN13

CH1_TIN26

CH1_TIN23

CH1_TIN16

CH1_TIN14

CH1_TIN24

CH1_TIN25

CH1_TIN12

CH1_TIN10

A11_CH1A12_CH1

CH1_TIN20

CH1_TIN21

CH1_TIN0

CH1_TIN18

CKE1_CH1

DQ

0_C

H1

LB16

CH1_TIN22

SDRAM_CLK0_FBK

SDRAM_CLK0_FBK_RES

IO_14

IO_11IO_15

CAS#_CH1

DQ

15_C

H1

IO_21

WE#_CH1

LB18

IO_18

LB17

LB19

RESET

LB0

LB14

A8_

CH

1A

10_C

H1

A7_

CH

1

A9_CH1

BA

1_C

H1

BA

0_C

H1

A5_

CH

1A

6_C

H1

SDRAM_CLK0_FBK SDRAM_CLK0_FBK_RES

1

1

2

2

3

3

4

4

5

5

D D

C C

B B

A A

A3 11 11 123001010203

RESISTOR

1.0

SIGNATURE

DRAWN

CHECKED

APPROVED


SHEET NAME :

SIZE SHEETOF

ISSUE DOC. No. :

R60

CAT16-LV4F12

1

23

45

67

8

10

9

12

11

14

16

15

13

R12

CAT16-LV4F12

1

23

45

67

8

10

9

12

11

14

16

15

13

R13

CAT16-LV4F12

1

23

45

67

8

10

9

12

11

14

16

15

13

R65

CAT16-LV4F12

1

23

45

67

8

10

9

12

11

14

16

15

13

R55

CAT16-LV4F12

1

23

45

67

8

10

9

12

11

14

16

15

13

R47

CAT16-LV4F12

1

23

45

67

8

10

9

12

11

14

16

15

13

R52

CAT16-LV4F12

1

23

45

67

8

10

9

12

11

14

16

15

13

R9

CAT16-LV4F12

1

23

45

67

8

10

9

12

11

14

16

15

13

R66

CAT16-LV4F12

1

23

45

67

8

10

9

12

11

14

16

15

13

R10

CAT16-LV4F12

1

23

45

67

8

10

9

12

11

14

16

15

13

R67

CAT16-LV4F12

1

23

45

67

8

10

9

12

11

14

16

15

13

R11

CAT16-LV4F12

1

23

45

67

8

10

9

12

11

14

16

15

13

LVDS_I/O_32_N

LVDS_I/O_29_P

LVDS_I/O_32_P

LVDS_I/O_30_P

LVDS_I/O_30_N

LVDS_I/O_29_N

LVDS_I/O_21_P

LVDS_I/O_22_P

LVDS_I/O_33_P

LVDS_I/O_33_N

LVDS_CLK0_P

LVDS_CLK0_N

LVDS_I/O_28_P

LVDS_I/O_27_P

LVDS_I/O_28_N

LVDS_I/O_27_N

CON_LVDS_I/O_28_N

CON_LVDS_I/O_27_P

CON_LVDS_I/O_28_P

CON_LVDS_CLK0_P

CON_LVDS_I/O_27_N

CON_LVDS_CLK0_N

CON_LVDS_I/O_32_N

CON_LVDS_I/O_29_P

CON_LVDS_I/O_32_P

CON_LVDS_I/O_30_P

CON_LVDS_I/O_30_N

CON_LVDS_I/O_29_N

CON_LVDS_I/O_33_P

CON_LVDS_I/O_33_N

CON_LVDS_I/O_26_P

CON_LVDS_I/O_26_N

LVDS_I/O_26_P

LVDS_I/O_26_N

LVDS_I/O_36_P

LVDS_I/O_35_P

LVDS_I/O_34_P

LVDS_I/O_37_N

LVDS_I/O_36_N

LVDS_I/O_35_N

LVDS_I/O_34_N

LVDS_I/O_37_P

CON_LVDS_I/O_35_P

CON_LVDS_I/O_37_N

CON_LVDS_I/O_34_P

CON_LVDS_I/O_36_PCON_LVDS_I/O_35_N


CON_LVDS_I/O_34_N

LVDS_I/O_39_N

LVDS_CLK1_P

LVDS_I/O_38_N


LVDS_I/O_40_PLVDS_CLK1_N

LVDS_I/O_38_P CON_LVDS_I/O_38_P

CON_LVDS_I/O_40_P


CON_LVDS_I/O_38_N

CON_LVDS_CLK1_P

CON_LVDS_I/O_39_N

CON_LVDS_CLK1_N


CON_LVDS_I/O_42_N


CON_LVDS_I/O_44_P

LVDS_I/O_46_N


LVDS_I/O_47_P

LVDS_I/O_49_P

LVDS_I/O_49_N

LVDS_I/O_48_N

LVDS_I/O_48_P

CON_LVDS_I/O_46_N

CON_LVDS_I/O_47_N

CON_LVDS_I/O_47_P

CON_LVDS_I/O_49_P

CON_LVDS_I/O_49_N

CON_LVDS_I/O_48_N

CON_LVDS_I/O_48_P

CON_LVDS_I/O_46_P

CON_LVDS_I/O_2_N

CON_LVDS_I/O_3_P

CON_LVDS_I/O_1_N


CON_LVDS_I/O_0_N

CON_LVDS_I/O_0_P

CON_LVDS_I/O_1_P

LVDS_I/O_16_N

CON_LVDS_I/O_13_N

CON_LVDS_I/O_19_N

CON_LVDS_I/O_13_P

CON_LVDS_I/O_16_N

CON_LVDS_I/O_20_P

LVDS_I/O_18_N

CON_LVDS_I/O_14_N

CON_LVDS_I/O_19_P

CON_LVDS_I/O_17_N

LVDS_I/O_19_P

CON_LVDS_I/O_15_PLVDS_I/O_15_P

LVDS_I/O_14_P

LVDS_I/O_13_N

LVDS_I/O_13_P

CON_LVDS_I/O_18_P

LVDS_I/O_16_P

LVDS_I/O_14_N

CON_LVDS_I/O_15_NLVDS_I/O_15_NCON_LVDS_I/O_14_P

CON_LVDS_I/O_16_P

CON_LVDS_I/O_18_N

CON_LVDS_I/O_8_N

CON_LVDS_I/O_10_P

CON_LVDS_I/O_9_P

CON_LVDS_I/O_11_N

LVDS_CLK2_N

CON_LVDS_I/O_11_P

LVDS_CLK2_P

CON_LVDS_CLK2_N

CON_LVDS_I/O_4_N

CON_LVDS_I/O_6_N

CON_LVDS_I/O_7_N

CON_LVDS_I/O_9_N

CON_LVDS_I/O_6_P

CON_LVDS_I/O_10_N

CON_LVDS_I/O_4_P

CON_LVDS_CLK2_P

LVDS_I/O_4_N

LVDS_I/O_7_N

LVDS_I/O_7_P

LVDS_I/O_6_P

LVDS_I/O_4_P

LVDS_I/O_10_P

LVDT_I/O_10_N


LVDS_I/O_8_N

LVDS_I/O_9_P

LVDS_I/O_11_N

LVDS_I/O_11_P

CON_LVDS_I/O_8_P

LVDS_I/O_43_P

LVDS_I/O_43_N

LVDS_I/O_42_N

LVDS_I/O_42_P


CON_LVDS_I/O_45_P

LVDS_I/O_44_N

LVDS_I/O_45_P

CON_LVDS_I/O_45_N

LVDS_I/O_0_N

LVDS_I/O_1_N

LVDS_I/O_3_P

LVDS_I/O_2_P

LVDS_I/O_1_P

LVDS_I/O_3_N

LVDS_I/O_2_N

LVDS_I/O_0_P

CON_LVDS_I/O_21_N


CON_LVDS_I/O_23_P

CON_LVDS_I/O_22_P

CON_LVDS_I/O_22_N

CON_LVDS_I/O_21_P

LVDS_I/O_25_N

LVDS_I/O_22_N

LVDS_I/O_21_N

CON_LVDS_I/O_25_P

LVDS_I/O_23_P

LVDS_I/O_23_N

LVDS_I/O_25_P

LVDS_I/O_6_N

CON_LVDS_I/O_20_N

LVDS_I/O_18_P

CON_LVDS_I/O_17_P

LVDS_I/O_20_P

LVDS_I/O_17_N

LVDS_I/O_20_N

LVDS_I/O_19_N

LVDS_I/O_17_P

CON_LVDS_I/O_7_P

BILL OF MATERIAL

123001010204 Dec 2003

DGC-FD-611 V0.0 Page 1/2

BILL OF MATERIAL Module Name: SDRAM BUFFER CARD Classification : Commercial SLNo

Component Description

Reference Qty Specification (Part Name +

Package)

Manufacturer/ Source (Vendor)

1 Capacitor C39, C1 2 2.2uF CAP3528

Siricom

Capacitor C2, C26, C80, C104, C115C3,C4,C5,C6,C7,C8,C9, C10,C11,C12,C13,C14,C15,C16,C17,C18,C19,C20,C21,C22,C23,C24,C25,C27,C28,C29,C30,C31,C32,C33,C34,C35,C36,C37,C38,C40,C41,C42,C43,C44,C45,C46,C47,C48,C49,C50,C51,C52,C53,C54,C55,C56,C57,C58,C59,C60,C61,C62,C63,C64,C65,C66,C67,C68,C69,C70,C71,C72,C73,C74,C75,C76,C77,C78,C79,C81,C82,C83,C84,C85 , C86, C87, C88, C89, C90, C91, C92, C93, C94, C95, C96, C97, C98, C99, C100, C101, C102, C103, C105, C106, C107, C108, C109, C110, C111, C112, C113, C114, C116, C117, C118, C119, C120, C121, C122, C123, C124, C125, C126, C127, C128, C129, C130, C131, C132, C133, C134, C135, C136, C137, C138, C139, C140, C141, C142, C143, C144, C145, C146, C147, C148, C149, C150, C151, C152, C153, C154, C157, C160, C161

155 0.1uF CAP0402MLC

Siricom

3 Capacitor C155 1 CAP 1uF CAP1206MIL

Siricom

4 Capacitor C156, C158, C159 3 47uF CAP3528

Siricom

5 LED D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13

13 LED 1206 Pack

Siricom

6 Diode D14 1 Diode SOD87

KRC

7 Jumper JP1, JP2, JP4, JP5 4 SIP-2P KRC

8 FPGA Jtag JP3 1 Header20 KRC

9 Jack Connector J6, J1 2 MJACK_CAT5-4X8P

RRI

10 34 Pin Connector

J5, J2 2 Smd-Header34 KRC

11 2 Pin SMD Connector

J7, J3 2 SIP-3P KRC

12 CPLD Jtag J4 1 SIP-9P KRC

13 2 Pin Connector

J8, J9, J10, J11 4 SIP-2P KRC

123001010204 Dec 2003

DGC-FD-611 V0.0 Page 2/2

14 2 Pin SMD Connector

J12, J13, J14, J15, J16, J17 J18, J19, J20

9 CON-SMD-2P

15 Resistor R1, R8, R16, R20, R35, R41, R69, R70, R72, R73

10 4.7K RES0805MIL

Siricom

16 Resistor R2, R3, R4, R6 4 47E RES0805MIL

Siricom

17 Resistor R5, R14, R15, R21 4 100E RES0805MIL

Siricom

18 Resistor R7, R24, R32, R34, R38, R40, R46, R49, R50, R53, R56, R59, R62, R64, R68

15 100E RES0603

Siricom

19 Resistor R9, R10, R11, R12, R13, R47, R52, R55, R60, R65, R66, R67

12 100E CAT16-LV4F12

Siricom

20 Resistor R17, R18, R19, R31, R37, R39, R45, R48, R51, R54, R58, R61, R63

13 1K RES0805MIL

Siricom

21 Resistor R25, R22 2 10E RES0603

Siricom

22 Resistor R23, R57 2 TBD RES0805MIL

Siricom

23 Resistor R26, R27, R28, R29, R36, R42, R43, R44

8 39.2E RES0805MIL

Siricom

24 Resistor R30, R33 2 39.2E RES0603

Siricom

25 Resistor R71 1 10K RES0805MIL

Siricom

26 Push Button SW1 1 KSC3 Allide Electronics

27 Dimm Slot U9, U1 2 168_dimm_socket Uroteq

28 Oscillator U2, U11 2 FOX-F4100-1 Siltaq

29 XC2S200E Fpga

U3, U5, U7 3 SPTN-PQFP208 RRI

30 FS6377 - Synthesizer

U4 1 SO16 Siltaq

31 XC95144XL- Cpld

U14, U6 2 XC95144XL RRI

32 xc18v04 -Prom

U16, U8 2 xc18v04 Insight

33 PI49FCT3805BQ – Clock Driver

U10 1 PI49FCT380 Siltaq

34 DS90CR285 – Serializer

U13, U12 2 DS90CR285 RRI

35 DS90CR286 – Deserializer

U15 1 DS90CR286 RRI

36 Crystal Y1 1 Not Used

37 Sdram Module 2 128MB Sdram Module

Bright

Prepared by: Shridhar Date: 18\12\2003 Approved by: Venkat Date: 18\12\2003

PCB LAYOUT

ACCEPTANCE TEST PROCEDURE

123001010126 DEC’ 2003

Deepti Electronics & Electro-optics Pvt Ltd. Bangalore.

i

SDRAM BUFFER CARD ACCEPTANCE TEST PROCEDURE

Document No: Issue. No.: 1 Revision: 00

123001010126 DEC’ 2003


ii

Copyright 2002 This document is copyrighted with all rights reserved. No part of this manual shall be reproduced, transmitted, communicated by any means or modes, transcribed, stored in a retrieval system or translated into any language in any form by any means without the prior written permission of Deepti Electronics & Electro-optics Pvt Ltd.

123001010126 DEC’ 2003


iii

123001010126 DEC’ 2003


iv

TABLE OF CONTENTS

1 INTRODUCTION....................................................................................1

1.1 DELIVERABLES ................................................................................1

2 SPECIFICATIONS..................................................................................1

2.1 FUNCTIONAL SPECIFICATIONS ............................................................1

2.2 ENVIRONMENTAL................................................................................2

3 ACCEPTANCE TEST PROCEDURE ..................................................2

3.1 OVERVIEW ..........................................................................................2

3.2 VISUAL EXAMINATION .......................................................................2

3.3 POWER ON TESTS ...............................................................................3

3.4 SYNTHESIZER TEST.............................................................................3

3.5 SDRAM TEST ....................................................................................3

3.6 SERIALISER / DESERIALISER TEST.......................................................3

3.7 FPGA LVDS DRIVER RECEIVER TEST...............................................4

123001010126 DEC’ 2003


v

LIST OF ABBREVIATIONS USED

+ve : Positive AC : Alternating Current CPU : Central Processing Unit CRO : Cathode Ray Oscilloscope DEEOPL : Deepti Electronics & Electro Optics (P) Ltd. ATP : Acceptance Test Report Fig. : Figure I/O : Input / Output PC : Personal Computer

RH : Relative Humidity SW : SoftWare -ve : Negative ATR : Acceptance Test Report WR# : Active low Write RD# : Active low read FPGA : Field Programmable Gate Array CPLD : Complex Programmable Logic Device SDRAM : Synchronous Dynamic Random Access Memory LVDS : Low Voltage Differential Signal

123001010126 DEC’ 2003


vi

REFERENCE DOCUMENTS Sl. No.

Document Description Document Number

1 2 3 4 5 6

123001010126 DEC’ 2003


vii

THIS PAGE IS LEFT INTENTIONALLY BLANK

123001010126 DEC’ 2003

Deepti Electronics & Electro-optics Pvt Ltd 1 Bangalore.

1 INTRODUCTION This document describes the Acceptance Test procedure (ATP) for the system.

1.1 DELIVERABLES SDRAM BUFFER CARD

Software – Driver and Test S/W

The software (Firmware) is loaded on to the FPGA boot PROMS and they are all tested.

2 SPECIFICATIONS The Finalised Requirement Specifications are as follows:

2.1 Functional Specifications

1. SDRAM Memory Size : 128MB / 256MB per slot

2. No of slots : Two

3. Speed : 80Mz Normal (100MHz Max)

4. Configuration : Two independent banks

5. SDRAM Controller (Two channels) : Implemented in FPGA

(XC2S200E-PQ208-6)

6. SDRAM Data Bus : 8/16/32Bit per bank

7. Glue Logic Interface : CPLD XC95144XL

EXTERNAL INTERFACE

8. LVDS Lines : 45 pairs + 3 clock Pairs

9. Channel Links : Channel Link Transmitter-28 BITs 66MHZ (2 Nos)

Channel Link Receiver- 28 BITS, 66MHZ

10. External interface Connector : 50 Mil pitch SMD, Two x 32 pins

(For 48 LVDS Lines)

Gang connector, two x 16 pins

(For Channel Links)

123001010126 DEC’ 2003


11. FPGA Boot Code : 18V04 Prom or XC9572 CPLD

and 29040 FLASH (or FPGA

FLASH PROM)

12. Synthesizer : 4 Clock Outputs (0.8 to 100MHz)

13. Power supply input : 3.3V , 1.8V and 2.5V

14. Board dimension : 75 x 160mm, typical

2.2 Environmental

a) Temperature : 0 to 50°C

b) Humidity : 95% RH, non-condensing

3 ACCEPTANCE TEST PROCEDURE 3.1 Overview

The ATP for the system consists of the following:

a) Visual Examination

b) Power On Tests

c) Synthesizer Test

d) SDRAM Test

e) Channel Link Transmitter / Channel Link Receiver Test

f) FPGA LVDS Driver Receiver Test

3.2 Visual Examination

Purpose: To physically check that

a) All sub-systems are in the prescribed locations

b) To check for all interconnections

c) To check for Power connections

The observation made for all tests below is noted in the table as shown in ATR.

123001010126 DEC’ 2003


3.3 Power On Tests

Purpose: To check that all subsystems gets power Method:

a) Power on the system.

b) Check for the led glow of 3.3V Supply, 1.8V Supply and 2.5V Supply.

c) Check for the reset of the system by pressing the manual switch, which is

connected to the power on reset circuit.

d) Check the nominal supply current drawn.

3.4 Synthesizer Test

Purpose: To check the output frequency (CLKA, CLKB, CLKC, CLKD) of the

synthesizer.

Method: a) Program the synthesizer for required frequency by FPGA. The output

frequency of the synthesizer is measured.

3.5 SDRAM Test

Purpose: Validation of SDRAM data. Method:

a) A 32 bit counter is written into SDRAM (2 chipselects, 4 banks ,8096

rows,1024 columns).

b) Using ChipScope The data is read back and compared with the written

data and a read counter is incremented for every read data.

3.6 Serialiser / Deserialiser Test

Purpose: Validation of Serialiser data. Method:

a) A counter is written into Serialiser at 40MHz

b) The serialiser output is looped back to deserialiser.

123001010126 DEC’ 2003


c) The deserialiser output is observed on oscilloscope.

d) The observation is given in the table as shown in ATR.

3.7 FPGA LVDS Driver Receiver Test

Purpose: Validation of LVDS data. Method:

a) A counter is written into LVDS Driver pins of FPGA.

b) The driver pins are loop backed to LVDS receiver pins of FPGA.

c) The Receiver IOs are observed in Chipscope.

d) The observation is given in the table as shown in ATR.

e) The LVDS driver / receiver built into the FPGAs is being tested for

hardware clearance at very low speed (7.3728 MHz). The device is

rated for 622 MBPS data-rate. The validation of maximum speed

capable by this card will be done with actual termination resistors that

is being planned to be populated at a later stage when they are made

available.

ACCEPTANCE TEST REPORT

123001010127 Dec’ 2003

Deepti Electronics & Electro-optics Pvt Ltd 1

Bangalore.


Project: Sdram Buffer card Type:

Date:

INDEX

1 POWER ON TEST 3

2 SYNTHESISER TEST 3

3 SDRAM TEST 4

4 CHANNEL LINK TRANSMITTER / CHANNEL LINK RECEIVER 6

5 FPGA LVDS DRIVER AND RECEIVER TEST 7

123001010127 Dec’ 2003


Bangalore.

SDRAM Buffer Card - Summary of Tests

Sl.No. TEST REMARKS

1 Visual Examination OK

2 Power On test OK

3 Synthesizer test OK

4 SDRAM test OK

5 Channel Link Transmitter / Channel Link Receiver

test

OK

6 LVDS Test OK

123001010127 Dec’ 2003


Bangalore.

1 POWER ON TEST Expected: As given in the ATP procedure.

Observed:

Test point Expected Observed

Remarks

LED

(3.3V) ON ON OK

LED

(1.8V) ON ON OK

LED

(VCCO 1.8/2.5V) ON ON OK

Input Current 0.3A

(Typical) 0.23A OK

2 SYNTHESISER TEST Expected: The output frequency (CLKA, CLKB, CLKC, CLKD) of the

synthesizer should be same as expected.

Observed:

Expected freq Observed Frq Remarks

CLK

A

(MHz)

CLK

B

(MHz)

CLK

C

(MHz)

CLK

D

(MHz)

CLK

A

(MHz)

CLK

B

(MHz)

CLK

C

(MHz)

CLK

D

(MHz) Card

No.

80 80 7.3728 7.3728 80 80 7.3728 7.3728 OK

123001010127 Dec’ 2003


Bangalore.

3 SDRAM TEST Expected: Validation of SDRAM data

Observed:

Input Data

Channel Chip

Select Bank

Expected

output

Observed

output

BA0 Incremental

counter

Incremental

counter OK

BA1 Incremental

counter

Incremental

counter OK

BA2 Incremental

counter

Incremental

counter OK

CS0

BA3 Incremental

counter

Incremental

counter OK

BA0 Incremental

counter

Incremental

counter OK

BA1 Incremental

counter

Incremental

counter OK

BA2 Incremental

counter

Incremental

counter OK

Ch1

CS1

BA3 Incremental

counter

Incremental

counter OK

123001010127 Dec’ 2003


Bangalore.

Input Data

Channel Chip

Select Bank

Expected

output

Observed

output

BA0 Incremental

counter

Incremental

counter OK

BA1 Incremental

counter

Incremental

counter OK

BA2 Incremental

counter

Incremental

counter OK

CS0

BA3 Incremental

counter

Incremental

counter OK

BA0 Incremental

counter

Incremental

counter OK

BA1 Incremental

counter

Incremental

counter OK

BA2 Incremental

counter

Incremental

counter OK

Ch2

CS1

BA3 Incremental

counter

Incremental

counter OK

123001010127 Dec’ 2003


Bangalore.

4 CHANNEL LINK TRANSMITTER / CHANNEL LINK RECEIVER

Expected: To loop back the transmitted output to Receiver and compare the

data with the required.

Observed:

Data transmitted

(CH1)

Data Received

Remark

EXP OBS OBS EXP

Incremental

Counter

Incremental

Counter

Incremental

Counter

Incremental

Counter

OK

Data transmitted

(CH2)

Data Received

Remark

EXP OBS OBS EXP

Incremental

Counter

Incremental

Counter

Incremental

Counter

Incremental

Counter

OK

123001010127 Dec’ 2003


Bangalore.

5 FPGA LVDS DRIVER AND RECEIVER TEST Expected: To loop back the transmitted output to Receiver and compare the


Observed:

Data transmitted

(CH1)

Data Received

Remark

EXP OBS OBS EXP

Incremental

Counter

Incremental

Counter

Incremental

Counter

Incremental

Counter

OK

Prepared By: Approved By:

(Quality)

123001010127 Dec’ 2003


Bangalore.


Project: Sdram Buffer card Type:

Date:

INDEX

1 POWER ON TEST 3

2 SYNTHESISER TEST 3

3 SDRAM TEST 4

4 CHANNEL LINK TRANSMITTER / CHANNEL LINK RECEIVER 6

5 FPGA LVDS DRIVER AND RECEIVER TEST 7

123001010127 Dec’ 2003


Bangalore.

SDRAM Buffer Card - Summary of Tests

Sl.No. TEST REMARKS

1 Visual Examination OK

2 Power On test OK

3 Synthesizer test OK

4 SDRAM test OK

5 Channel Link Transmitter / Channel Link Receiver

test

OK

6 LVDS Test OK

123001010127 Dec’ 2003


Bangalore.

1 POWER ON TEST Expected: As given in the ATP procedure.

Observed:

Test point Expected Observed

Remarks

LED

(3.3V) ON ON OK

LED

(1.8V) ON ON OK

LED

(VCCO 1.8/2.5V) ON ON OK

Input Current 0.3A

(Typical) 0.23A OK

2 SYNTHESISER TEST Expected: The output frequency (CLKA, CLKB, CLKC, CLKD) of the

synthesizer should be same as expected.

Observed:

Expected freq Observed Frq Remarks

CLK

A

(MHz)

CLK

B

(MHz)

CLK

C

(MHz)

CLK

D

(MHz)

CLK

A

(MHz)

CLK

B

(MHz)

CLK

C

(MHz)

CLK

D

(MHz)

Card

No.

02

80 80 7.3728 7.3728 80 80 7.3728 7.3728 OK

123001010127 Dec’ 2003


Bangalore.

3 SDRAM TEST Expected: Validation of SDRAM data

Observed:

Input Data

Channel Chip

Select Bank

Expected

output

Observed

output

BA0 Incremental

counter

Incremental

counter OK

BA1 Incremental

counter

Incremental

counter OK

BA2 Incremental

counter

Incremental

counter OK

CS0

BA3 Incremental

counter

Incremental

counter OK

BA0 Incremental

counter

Incremental

counter OK

BA1 Incremental

counter

Incremental

counter OK

BA2 Incremental

counter

Incremental

counter OK

Ch1

CS1

BA3 Incremental

counter

Incremental

counter OK

123001010127 Dec’ 2003


Bangalore.

Input Data

Channel Chip

Select Bank

Expected

output

Observed

output

BA0 Incremental

counter

Incremental

counter OK

BA1 Incremental

counter

Incremental

counter OK

BA2 Incremental

counter

Incremental

counter OK

CS0

BA3 Incremental

counter

Incremental

counter OK

BA0 Incremental

counter

Incremental

counter OK

BA1 Incremental

counter

Incremental

counter OK

BA2 Incremental

counter

Incremental

counter OK

Ch2

CS1

BA3 Incremental

counter

Incremental

counter OK

123001010127 Dec’ 2003


Bangalore.

4 CHANNEL LINK TRANSMITTER / CHANNEL LINK RECEIVER

Expected: To loop back the transmitted output to Receiver and compare the


Observed:

Data transmitted

(CH1)

Data Received

Remark

EXP OBS OBS EXP

Incremental

Counter

Incremental

Counter

Incremental

Counter

Incremental

Counter

OK

Data transmitted

(CH2)

Data Received

Remark

EXP OBS OBS EXP

Incremental

Counter

Incremental

Counter

Incremental

Counter

Incremental

Counter

OK

123001010127 Dec’ 2003


Bangalore.

5 FPGA LVDS DRIVER AND RECEIVER TEST Expected: To loop back the transmitted output to Receiver and compare the


Observed:

Data transmitted

(CH1)

Data Received

Remark

EXP OBS OBS EXP

Incremental

Counter

Incremental

Counter

Incremental

Counter

Incremental

Counter

OK

Prepared By: Approved By:

(Quality)

Dec’ 2003


Bangalore.

JUMPER SETTINGS:

JP2, JP4: Bypasses the proms U8, U16 from FPGA JTAG chain when

shorted.

JP5: Bypasses the FPGA U5 from FPGA JTAG chain when shorted.

JP1: Bypasses the CPLD U6 From CPLD JTAG chain when shorted.

J7: Selects the VCCO for U5

For Configuring U5 as LVDS Or LVCMOS2 IO short J7.1 and J7.2

For configuring u5 as LVTTL IO short J7.3 and J7.2

This also selects VCCIO2 of CPLD U14

J3: Selects the VCC of CPLD U6

This is the provision to use either XC95144XL or XC95144XV

J18, J19, J20: For booting FPGAS from Prom these Jumpers should be

shorted

sdram buffer card: 1.0 block diagram 2.0 schematics...

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