see scaling effects lloyd massengill 10 may 2005

SEE Scaling Effects

Lloyd Massengill10 May 2005

MURI 05 Kickoff 10 May 2005 2

Institute for Space and Defense Electronics Vanderbilt Engineering

Hierarchical Multi-Scale Analysis of Radiation Effects

Materials

Device Structure

Device Simulation Circuit Response

IC DesignEnergy

Deposition

Defect Models



Scaling and SEUs

“Unconventional” SEE Mechanisms in Technology Nodes Below 100nm:

Charge Sharing • Distributed effects

Secondary (nuclear) Reactions• Probabilistic effects

Track Size as Large as the Critical Region• Spatial effects

Circuit Speed on the order of Collection Dynamics• Temporal effects



Scaling and SEUs








Charge Sharing *

Issue: At the 250nm CMOS technology node, we have observed two “unusual” effects

Heavy Ion – Very low LETth Laser (2) – N-Well Edge

NFETs

PFETs

Quantum 4M SRAM SEU DataSample 581 Versus Operating Conditions

1.0E-13

1.0E-12

1.0E-11

1.0E-10

1.0E-09

1.0E-08

1.0E-07

0 10 20 30 40 50 60 70 80 90 100 110 120 130

LETeff (MeV/mg/cm2)

Upse

t Xse

ctio

n (c

m2/

bit)

No latchup after 1E7 particles @ LETeff of 120 MeV/mg/cm2. (3.6V, 125 C)

Quantum 4M SRAM SEU DataSample 581 Versus Operating Conditions

1.0E-13

1.0E-12

1.0E-11

1.0E-10

1.0E-09

1.0E-08

1.0E-07

0 10 20 30 40 50 60 70 80 90 100 110 120 130

LETeff (MeV/mg/cm2)

Upse

t Xse

ctio

n (c

m2/

bit)


* McMorrow et al, ”Single-Event Upset in Flip-Chip SRAM Induced by Through-Wafer, Two-Photon Absorption”, accepted to the 2005 NSREC

Warren et al., “The Contribution of Nuclear Reactions to Single Event Upset Cross-Section Measurements in a High-Density SEU Hardened SRAM Technology”, accepted to the 2005 NSREC



Charge Sharing Background *

Distributed-storage hardened SRAM cell:

“Single Node” events cannot produce an upset

Charge collection required at nodes on both legs

Event sequence• Sufficient charge must be

collected on one leg to float the opposite leg

• The floating leg must then collected enough charge to lose its state

Pull-Up

Access

Hardening

Pull-Down

Hardening

P-wellWithN-FET

N-wellWithP-FET

= Gate Poly = Diffusion

SensitiveRegion

Pull-Up

Access

Hardening

Pull-Down

Hardening

P-wellWithN-FET

N-wellWithP-FET


SensitiveRegion

Pull-Up

Access

Hardening

Pull-Down

Hardening

P-wellWithN-FET

N-wellWithP-FET


SensitiveRegion

Pull-Up

Access

Hardening

Pull-Down

Hardening

P-wellWithN-FET

N-wellWithP-FET


SensitiveRegion

H L

* Warren et al., “The Contribution of Nuclear Reactions to Single Event Upset Cross-Section Measurements in a High-Density SEU Hardened SRAM Technology”, accepted to the 2005 NSREC



Charge Sharing Simulations *

Mixed-mode simulations (3-D TCAD + compact model) useful for efficiency

We constructed calibrated base structure for SEE mapping

VAMPIRE simulations: 4G Opteron nodes550,000 elements, 1.5 wks per

Pull-Up

Access

Hardening

Pull-Down

Hardening

P-wellWithN-FET

N-wellWithP-FET


SensitiveRegion

Pull-Up

Access

Hardening

Pull-Down

Hardening

P-wellWithN-FET

N-wellWithP-FET


SensitiveRegion

Pull-Up

Access

Hardening

Pull-Down

Hardening

P-wellWithN-FET

N-wellWithP-FET


SensitiveRegion

Pull-Up

Access

Hardening

Pull-Down

Hardening

P-wellWithN-FET

N-wellWithP-FET


SensitiveRegion

TCAD

SPICE* Olson et al, “Simultaneous SE Charge Sharing and Parasitic Bipolar Conduction in

a Highly-Scaled SRAM Design,“ accepted to NSREC 2005



Charge Sharing Preliminary Findings *

Functionally disjoint, but physically adjacent nodes share charge

In addition, parasitic conduction affects PFET of opposite rail

Pull-Up

Access

Hardening

Pull-Down

Hardening

P-wellWithN-FET

N-wellWithP-FET


SensitiveRegion

Pull-Up

Access

Hardening

Pull-Down

Hardening

P-wellWithN-FET

N-wellWithP-FET


SensitiveRegion

Pull-Up

Access

Hardening

Pull-Down

Hardening

P-wellWithN-FET

N-wellWithP-FET


SensitiveRegion

Pull-Up

Access

Hardening

Pull-Down

Hardening

P-wellWithN-FET

N-wellWithP-FET


SensitiveRegion

H L

M7

M8

M9

M10

M2

M0

M4

M5

* Olson et al, “Enhanced Single-Event Charge Collection in Submicron CMOS Due to a Diffusion-Triggered Parasitic LPNP” presented at HEART 05



Scaling and SEUs








Secondary (Nuclear) Effects

Issue: Unable to explain upsets at very low LET in TCAD Upset cross section too small to be intra-cell variation

1.0E-13

1.0E-12

1.0E-11

1.0E-10

1.0E-09

1.0E-08

1.0E-07

0 10 20 30 40 50 60 70 80 90 100 110 120 130

LETeff (MeV/mg/cm2)

Ups

et X

sect

ion

(cm

2/bi

t)

Dyn, 3.14V, 125C Static, 3.14V, 125C Dyn, 3.3V, 32C


Brookhaven Labs, 3/27/02rdb

Ultra Low (follow-on at BNL)

Approximate Ion ( -Track Area intra

)cell Limit

TCAD Prediction

TCAD with average

LET ion does not

explain low LET upsets



Secondary (Nuclear) Effects Hypotheses

Nuclear reaction events can increase the effective LET to +/- 8x the incident LET for this simulation

In scaled technologies, the low probability of occurrence offset by: - high number of sensitive volumes (4 Mbit SRAM)- elimination of lower-LET sensitivity via hardening

LET NuclearReaction Events

-Electrons LET NuclearReaction Events

-Electrons523 MeV Neon

= 1.79 / /LET MeV mg cm2



Secondary (Nuclear) Effects Preliminary Analysis *

MRED used for preliminary investigation of potential event sources:

Conceptually simple relative energy deposition experiment 1x108 Monte-Carlo type simulations Reactions in the interconnect materials result in charge

deposition from secondary species in the sensitive volume

2m3m

Sensitive Volume5m

All Cubes

523 MeV 20Ne

Oxide

Si2m

3m

Sensitive Volume5m

All Cubes

523 MeV 20Ne

Oxide

Si

Oxide Only Oxide and Metallization

2m3m

Sensitive Volume

5m

All Cubes

523 MeV 20Ne

Oxide

Si

Si

TiN

Al

1m1m

1m

2m3m

Sensitive Volume

5m

All Cubes

523 MeV 20Ne

Oxide

Si

Si

TiN

Al

1m1m

1m

W

* Warren et al., “The Contribution of Nuclear Reactions to Single Event Upset Cross-Section Measurements in a High-Density SEU Hardened SRAM Technology” accepted to the 2005 NSREC



Secondary (Nuclear) Effects Preliminary MRED Results

Nuclear Reactions can produce products greater than 8x in energy deposition than the primary LET

Effect is exacerbated with inter-connect materials (tungsten, aluminum, etc…)

1.E+00

1.E+01

1.E+02

1.E+03

1.E+04

1.E+05

1.00E+02 1.00E+03 1.00E+04 1.00E+05 1.00E+06 1.00E+07 1.00E+08

Energy (eV)

# of

Eve

nts

SiO2/Si

W/Ti/TiN/SiO2/Si

Primary LET

* ( 1 10Nuclear events only in x 8 simulations)

High EnergyEvents



Secondary (Nuclear) Effects On-Going Work

Integration of multiple tools• Layout• TCAD modules• MRED (nuclear)

Accurate spatial relationship between sensitive regions and materials

Interconnect material affects the probability of extreme value events

Events must occur near the sensitive region to upset the cell

A step closer to developing a predictive tool



Scaling and SEUs








Track Size

Issue: Device dimensions becoming

smaller than• Commonly assumed radial

dimensions for SE charge generation tracks

• Minority carrier diffusion lengths (even in Drain/Source regions)

Device topology has implications for charge deposition

(1) M. L. Alles, et. al. , “Considerations for Single Event Effects in Non-Planar Multi-Gate SOI FETs”, submitted for presentation at the 2005 IEEE International SOI Conference.

(2) R. Chau et. al., “Advanced Depleted-Substrate Transistors: Single-Gate, Double-Gate, Tri-Gate”, 2002 International Conference on Solid State Devices and Materials (SSDM 2002), Nagoya, Japan.

(1)

(2)



Track Size

Preliminary Simulations: Simulation of an ion hit using 3D TCAD

• (Alpha Particle, LET=2.4 MeV/mg-cm2) • Normal incidence• Three locations (Body, Drain, Source)

Response shows much longer time profile vs. direct collection;• Potential profile indicates bipolar action

Hit to Channel

M. L. Alles, et. al. , “Considerations for Single Event Effects in Non-Planar Multi-Gate SOI FETs”, submitted for presentation at the 2005 IEEE International SOI Conference. Simulated Tri-gate device based on: J Choi et. al., IEDM Technical Digest, 647 (2004).



Track Size

Preliminary Findings: Hits to Drain (and Source) can

lead to notable charge collection• Implication for sensitive area• Drain and source contribution

found to depend on contact placement and size

Energy deposition process in such small devices unclear• Convention LET concept may

break down• We will study this with detailed

simulations (MRED)• Accurate TCAD modeling

(FLOODS)

M. L. Alles, et. al. , “Considerations for Single Event Effects in Non-Planar Multi-Gate SOI FETs”, submitted for presentation at the 2005 IEEE International SOI Conference.



Scaling and SEUs








Circuit Speed

Issue:

GHz circuitry have response dynamics on the same order as charge collection transient profiles

In these cases, SE transients are indistinguishable from legitimate signals

Some hardening techniques are ineffective Dynamic modeling required Detailed SE charge collection profiles are needed



Conclusions

An understanding of SEE in emerging, scaled technologies (SiGe, ultra-small CMOS and 3-d SOI) constructed with novel materials systems (strained Si, alternative dielectrics, new metallizations) requires:

Improved physical models for ion interaction with materials other than Si

Detailed SE track structure models Improved understanding of nuclear reaction effects Improved device physics for mixed-mode modeling Improved understanding of parasitic charge collection

see scaling effects lloyd massengill 10 may 2005

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