[semi theater] recent developments in advanced packaging materials and markets

SEIMCONWest7.10 © 2010 TechSearch International, Inc.

Recent Developments in Advanced Packaging Materials and Markets

E. Jan VardamanPresident

TechSearch International, Inc.

www.techsearchinc.com


Advanced Packaging Market: Strong Growth for 2010

• Advanced Packaging includes BGAs, CSPs, flip chip, and WLPs– Showing strong growth– Growth in WLP market driven by mobile phones– Expansion in flip chip market driven by wireless conversion from wire

bond to flip chip• Massive expansion in CAPEX by OSATS

– Spending plans 2.7 times the level spent in 2009 by (ASE, Amkor, SPIL, STATS ChipPAC, Unisem, and UTAC)--includes expansion for plant and equipment

– Conversion from gold to copper wire (orders for more than 5,000 copper wire bonders in 2010)

– Capacity for 300mm bumping and wafer level packaging in short supply– Companies including ASE, STATS ChipPAC, TSMC adding capacity– Fanout WLP– 3D die stacking with through silicon via (TSV) requires new equipment– Micro bumps for TSV and silicon interposer applications


Flip Chip Growth Drivers• Flip chip growth for high performance

devices– Microprocessors (all CPUs for PCs)– ASICs, FPGAs, and DSPs– Chipsets and Graphics– Digital TV and other media products

• Trends toward copper pillar• Micro bumps for TSV• Future flip chip growth in wireless

products– Driven by form factor and performance – Baseband processors moving to flip

chip– Bottom package in PoP (application

processor)

Source: Zyube

Source: ChipWorksSource: TI


Trends Impacting Laminate Substrates

• Flip chip IC bump pitch– Solder bump 170-200µm today moving to 150-160µm in next

generation– Cu pillar moving to as fine as 50µm in production

• Shift to Pb-free bumps– Finer pitch bumps– Higher reflow temperatures

• Introduction of lower-k dielectrics and Pb-free will be challenging• Substrate developments

– Higher density, thin core substrates• Substrate finishes

– Moving away from Electroless Nickel Gold (ENIG)– Adoption of Electroless Nickel, Electroless Palladium Gold (ENEPG)– Copper finish, OSP, immersion Sn, or SOP options


Growth in WLP Shipments

• Major application for WLP driven by mobile phones• Provides smaller, thinner package (low profile)• WLPs found in almost all phones from high-end to low-end handsets• CAGR of 11.5% in units (2009 to 2012)


WLP Trends

• Consumer products and other applications– Digital cameras and camcorders– MP3 players– Watch modules– Laptop computers– Medical– Automotive

• WLPs for many device types– WLPs for analog functions, power

management, RF, wireless LAN, integrated passives, sound IC, etc.

– Highest I/O count 195• Capacity shortage for 300mm WLP

– Regional shortage (Taiwan)– CAPEX for additional capacity of both 200mm

and 300mm– Companies adding capacity include TSMC,

ASE, and STATS ChipPAC Source: TPSS


Fan-out Wafer Level Packages• Die are increasing in size for WLP and number of I/O are increasing• Desire to use WLP, but can’t fan-in the I/O because there is not enough are area on

the die• Infineon eWLB

– Technology licensed by ASE and STATS ChipPAC– Companies have installed production lines– STMicroelectronics, STATS ChipPAC, and Infineon working to make a standard

package– LG moblie phones shipping with eWLB today

Source: InfineonSource: Infineon/ASE


Applications for Infineon’s eWLP

• At least 10 companies planning to adopt eWLB• LG and Bird mobile phones shipping with eWLB today

Source: Infineon/ASE


Mobile Phones Continue to Drive Packaging• Mobile phones still drive unit

volumes and a packaging technology

• Increased functionality drives high-density packaging with small form factors

– Stacked die CSPs– Package-on-Package (PoP)– System-in-Package (SiP)– Embedded components– TSV for camera modules

and other• Consumer preference for thin

light-weight products– Drive demand for low-

profile packaging – Die thinning– Increased use of WLPs

• Time-to-market and reduced cost remain goals

Source: Samsung


Moving to 3D with TSV• Applications for high-performance devices CPUs, GPUs, FPGAs, etc.• Applications for form factor and performance camera modules, wireless products• Drivers

– High bandwidth between memory and processor– Need for lower power

Source: Renesas


Prototype DRAM with TSV• DRAM

demonstrated– Elpida– Micron– NEC– Oki– Samsung

• Tezzaron announced ramp of high-speed SRAM memory

• Samsung announced combining 2 Gb DRAMs to create a smaller, faster, 4 Gb DIMM that uses less power

• PTI announces TSV packaging activity with Elpida and others

Source: Tezzaron

Source: Elpida


Issues for 3D TSV Adoption• Design guidelines and software must be available

– Current design tools not easily extended to 3D ICs– IDMs can build their own tools– University developments– R3Logic floorplanning tool– Designers must have tools and know how to use them

• Thermal solutions must be developed (especially for memory and processor)• Must be cost effective• Who will provide TSVs in silicon wafers?

– Foundries installing 300mm mass production lines, but many not ready for high volume until 2012

– IDM opt for the “do it yourself” model• Who will provide the bump, assembly, and test?

– Wafer test (to probe or not to probe)– Microbumping– Wafer thinning– Singulation– Substrates for TSV chip stack? (silicon interposer, high-density laminate)– Assembly process (underfill, etc.)– Final test

• Test issues must be resolved– Is KGD required for commercialization?– New test methodologies


Today’s Silicon Interposers

• Advantages– Can incorporate integrated passives– An interim solution before 3D IC with TSV

is possible– Planar module with stacked memory

adjacent to the processor for high speed memory requirements, can be tested prior to stacking

– Manage chip/package interaction stress with ultra low-k die

• Issues– Concern about CTE mismatch to organic

laminate of next packaging level for large interposers >20 mm x 20 mm

– Cost (especially for high via counts, yield hit for large substrates)

– Lossy lines in Si material– Does not solve problem of memory

latency– Lack of infrastructure (supply chain

handoff needs to be defined)

Source: IPDiA.

Source: DNP.


Conclusions

• Global semiconductor packaging materials market– Growth in 2010– Flip chip substrates still count for major share of dollar value of

market– Price pressures continue– New materials required for next silicon technology nodes

• Advanced packaging continues to drive unit volume growth and revenue growth

– WLP strong growth driven by need for thinner, smaller packages in mobile phones

– Adoption of fanout WLP– Flip chip will continue to grow– Capacity is expanding for FC and WLP, especially 300mm

• Emerging market for 3D TSV – Process development continues, companies installing and

qualifying 300mm production lines– Image sensors, MEMS, power amplifiers in production using

backside vias– First product true 3D IC not expected before 2012, volume after

22nm node technology

[semi theater] recent developments in advanced packaging materials and markets

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