semiconductor solutions multi-site test (soc)soc.yonsei.ac.kr/test/papers/7th/[f-1].pdfpattern...

SemiconductorSolutions

Jun.30.2006 7th Korea Test Conference1

Multi-site Test (Soc)

written byYong-Hwa Lee ([email protected])

Jin-Soo Ko ([email protected])



As a key objective from the start, multi-site test capability was designed into the tester system architecture and software to provide:

• Maximum system throughput• Maximum multi-site efficiency• Minimum development effort

Multi-Site Testing Goal



• Issues for Multi-Site test– Hardware architecture

• Digital Pin Count• Instruments per device under test• Open architecture• Asynchronous pattern generator

– Software architecture• Multisite support in software• Efficiency

Multi-Site Testing Issues



Synchronization Architecture

Universal Slot Test Head

Continuing to enhance the architectural fundamentals to meet the future requirements of SOC devices

Key Multi-Site Architectural for Parallel Test

Multi-Tiered DSP Architecture

DC & AnalogInstrumentsDC & AnalogInstruments

DigitalInstruments

DigitalInstruments

DSPEngines



Multi-Time Domain Testing

Multi-Time DomainArchitecture

All Instruments participate: DC, BBAC, VHFAC, uWave, and Digital

Clock per Instrument Board

Up to 8 Time Domains per site for true SOC / Mixed Signal IP-core testing

Faster Test Time, Higher Throughput

Pattern Generatorsper Instrument

Point-to-PointPattern Generator Communication



Multi-Rate Concurrent Test

IF2IF2ARXAX1RXAX2

SERIAL

MIC1MIC2MIC3

TXC

AGC

TXI

TXQ

AUXOUTHFEAR

AGC1

IREFVREF

PDATA

OtherDigital Pins

PCMTXD

PCMRXD DVDDAVDD

12-bitADC

FMDisc

11-bitDAC

11-bitDAC

8-bitDAC

8-bitDAC

4 DAC

ADC

RFC

9.72Mhz

Prog Div

8Khz

SOC Concurrent Test

Before: (serial)RF/IF Tests at 9.72Mhz: 800ms+ Codec Tests at 8Khz: 700ms

1500msAfter: (concurrent)

800ms

Concurrent Test Architecture allows parallel test within devicereducing test time to 800ms or 43% reduction




Multi-Rate Concurrent Test

Multi-Time DomainArchitectureAll Instruments - DC, AC, uWave, andDigital have local:

Clock and TimingInstrument ControlShare fail information across PatgensSynchronous phase start of clocks and PatgensLocal Measurement MemoryTest Computer-Independent Real Time Test Processors

Device Characterization/DebugFailure in an IP core, must trigHalt-on-Fail on other cores being tested; eg. failure in Core A caused by noise in Core B


Integra FLEX Instrument ArchitectureIntegra FLEX Instrument Architecture

FLAGFAIL

COND

Cross Time-Domain

Signaling



RTP

RTP

RTP

RTP

RTP

RTP

RTP

FLEXTest Head

RTP

Faster Test Time and Higher Throughput

Next Generation Clocking ArchitectureReal Time Test Processors

3 Levels of DSP

1. On the Host Computer

2. Local to Instrument

3. Real Time Test Processors

TesterComputer



Cross-Point

Matrix

Cross-Point

Matrix

1.536Gbit1.536Gbit

RTP

128MB

RTP

128MB

RTP

128MB

RTP

128MB

RTP

128MB

RTP

128MB

RTP

128MB

RTP

128MB

MBM

MBM

MBM

MBM

MBM

MBM

MBM

MBM

MBM

MBM

MBM

MBM

Slot1 Inst

Slot2 Inst

Slot3 Inst

Slot4 Inst

Slot5 Inst

Slot6 Inst

Slot7 Inst

Slot9 Inst

Slot10 Inst

Slot11 Inst

Slot24 Inst

Slot8 Inst

MBM

MBM

MBM

MBM

MBM

MBM

MBM

MBM

MBM

MBM

MBM

MBM

Slot1 Inst

Slot2 Inst

Slot3 Inst

Slot4 Inst

Slot5 Inst

Slot6 Inst

Slot7 Inst

Slot9 Inst

Slot10 Inst

Slot11 Inst

Slot12 Inst

Slot8 Inst

Ligh

tnin

g B

us

Mixed Signal Test PerformanceMixed Signal Test Performance


Real Time Test ProcessorsReal Time Test Processors

Level 3 DSP

Test Head-basedReal Time Test Processors (up to 8):

Real Time Processors 2 G4 each

Modularized for Upgrading128MB Memory per

Processor24 - 800Mbit/sec Busses

Parallel/Backgrounding of :Digital Signal Analysis while testingAll processes run in parallelNo waiting for Data MovementNo Tester Computer Intervention



Mixed Signal Test PerformanceMixed Signal Test Performance


Real Time Test ProcessorsDeferred Binning Test Flow



Multi-Site Efficiency

• Test program is “site-neutral” changing number of sites requires modification of channel map ONLY!

• Target to 90% - 99% multi-site efficiency!– Extensive use of hardware broadcast– Hardware site registers– Setups downloaded to tester memory

• Support for 32 sites built in, custom solutions to 128 sites

• Site flexibility allows high parallelism in smallConfiguration for many devices



Designed for massive concurrent testAll Instrument (DC, BBAC, VHFAC,

uWave Instruments) parameters can be controlled from pattern

PSETDC: Voltage, Current

Vrange, IrangeMeter RangeClampsVI Mode

AC: Source, Capture AmplitudeCapture Sample SizeCapture Sample RateOffsetDC Voltage or Current

DC Voltage or Current waveform, AC signal waveform are started with pattern microcodes.

DC Voltage or Current measurement, AC signal waveform captures are triggered from pattern microcode.

VCC3.3V

V=3.3VIrange=1AV=3.3VIrange=1A

Meas IccCurrentMeas IccCurrent

Meas IccCurrentMeas IccCurrent

V=3.3VIrange=20uAV=3.3VIrange=20uA

Voff=0.25VVoff=0.25V

Start Tri_1Start Tri_1 Vamp=1.2VVamp=1.2V

Start SineBStart SineB

Voff=0.50VVoff=0.50V

Massive Multi-Site Concurrent Testing

Uniform Multi-Time-Domain Synchronization

Pattern Controlled AC, DC Instruments



• Wait Time Reduction– Instrument settling times characterized and

controlled in Pattern Tool– Improved DC instrument performance – faster

measurements, increased metering density• Reduced Setup Times

– PSETS: instrument setup microcode in pattern– Simultaneous “broadcast” instrument setups

• Concurrent Testing– Distributed clock architecture provide ultimate

flexibility for concurrent multi-rate testing– Logical Pattern Generators (8 per site)

• On-board DSP– No lengthy data moves required– All DSP processing is done in background

Cross-Point

Matrix

Cross-Point

Matrix

1.536Gbit1.536GbitG4

128MB

G4128MB

G4128MB

G4128MB

G4128MB

G4128MB

G4128MB

G4128MB

MBM

MBM

MBM

MBM

MBM

MBM

MBM

MBM

MBM

MBM

MBM

MBM

Slot1 Inst

Slot2 Inst

Slot3 Inst

Slot4 InstSlot5 Inst

Slot6 Inst

Slot7 Inst

Slot9 Inst


Slot24 Inst

Slot8 Inst

MBM

MBM

MBM

MBM

MBM

MBM

MBM

MBM

MBM

MBM

MBM

MBM

Slot1 Inst

Slot2 Inst

Slot3 Inst


Slot6 Inst

Slot7 Inst

Slot9 Inst

Slot10 Inst

Slot11 Inst

Slot12 Inst

Slot8 InstLigh

tnin

g B

us

VO1

VO2

VO3

VO4

VO5S_in

DC SrcTurn On Output

Set V=4VSet I =2A

StrobingVoltmeter

Meas I

Voltage

Current

Highest Throughput



MultiMulti--site FLEX DIB Designsite FLEX DIB Design

Octal Site CD-P DIB on FLEX Test Head

No jumpers to meet customer’s DIB design guidelines

Component side of Octal Site CD-P DIB



•• Assign independent resources for each site to increase paralleliAssign independent resources for each site to increase parallelismsm–– HSDHSD–– Low speed signal capture optionLow speed signal capture option–– DSPDSP–– PPMUPPMU

•• Possible shared resources to reduce cost of testPossible shared resources to reduce cost of test–– Time Measurement Unit (TMU)Time Measurement Unit (TMU)–– Signal sourcesSignal sources–– High speed signal capture option High speed signal capture option

•• Possible shared resources to increase site to site correlationPossible shared resources to increase site to site correlation–– Reference DC sourceReference DC source–– Signal sourceSignal source

Test Resource AssignmentTest Resource Assignment



site0site0

BBAC Cap BBAC Cap #1#1

BBAC BBAC SrcSrc #1#1

DC30DC30

PPMUPPMU HSDHSD

site1site1

HSDHSD

site7site7

HSDHSD

refsrcrefsrc

UDBUDB

TMUTMU



DC30DC30 DC30DC30

PPMUPPMU PPMUPPMU



Resource Assignment for Octal SiteResource Assignment for Octal Site

Example of CD-P Demo Device



•• Check the input and output specs of the DC pins carefully to Check the input and output specs of the DC pins carefully to assign the appropriate test resources.assign the appropriate test resources.

•• Connect HSD PPMU for the standard DC test pins such as DC Connect HSD PPMU for the standard DC test pins such as DC level sourcing and measuring.level sourcing and measuring.

•• Use DC30 or DC 75 options instead of PPMU for testing Use DC30 or DC 75 options instead of PPMU for testing sensitive DC level sourcing and measuring.sensitive DC level sourcing and measuring.

•• If the test pin is sensitive to noise (such as filter pins), useIf the test pin is sensitive to noise (such as filter pins), use a high a high impedance and low noise OP Amp as a buffer of the DC options.impedance and low noise OP Amp as a buffer of the DC options.

•• If possible, make a path to BBAC Capture option to measure the If possible, make a path to BBAC Capture option to measure the DC level. It will provide an accurate DSP based solution for theDC level. It will provide an accurate DSP based solution for thetest (higher throughput).test (higher throughput).

DIB Circuit Design Tips for DC TestsDIB Circuit Design Tips for DC Tests



•• Check the input and output levels and assign the right amplifierCheck the input and output levels and assign the right amplifieror attenuator circuit.or attenuator circuit.

•• If the output signal power is not strong enough to drive the If the output signal power is not strong enough to drive the transmission line, add an appropriate power driver buffer.transmission line, add an appropriate power driver buffer.

•• Connect the minimum number of relays to a buffer. Additional Connect the minimum number of relays to a buffer. Additional relays will increase the capacitance of the input buffer and relays will increase the capacitance of the input buffer and reduce the frequency bandwidth.reduce the frequency bandwidth.

•• Must have loop back connection to the source option to calibrateMust have loop back connection to the source option to calibratethe buffer.the buffer.

•• AC coupling path is useful to check high DC offset signals.AC coupling path is useful to check high DC offset signals.•• Sometimes need different buffer circuits depending on the signalSometimes need different buffer circuits depending on the signal

level and frequency.level and frequency.

DIB Circuit Design Tips for AC TestsDIB Circuit Design Tips for AC Tests



•• Check each siteCheck each site’’s location on the DIB.s location on the DIB.•• Check pin Check pin ““11”” position of each site.position of each site.•• Check Handler Contactor ramifications on DIB.Check Handler Contactor ramifications on DIB.•• Place DGS lines to be central to each site.Place DGS lines to be central to each site.•• Add guards to sensitive analog signals.Add guards to sensitive analog signals.•• Add Kelvin connections at sensitive DC pins.Add Kelvin connections at sensitive DC pins.•• Ensure the symmetry of the artwork wherever possible. Ensure the symmetry of the artwork wherever possible. •• Connect AC source and capture traces by jumper pins and 0 ohm Connect AC source and capture traces by jumper pins and 0 ohm

resistors to help siteresistors to help site--toto--site correlation and debugging work.site correlation and debugging work.

•• Assign critical AC circuits placement first.Assign critical AC circuits placement first.•• Add small power ripple cap very close to power pins.Add small power ripple cap very close to power pins.•• Check the critical AC connections after autoCheck the critical AC connections after auto--routing.routing.•• Use power layers instead of power traces. Use power layers instead of power traces. •• To increase the application space, can use module boards on the To increase the application space, can use module boards on the DIB.DIB.

MultiMulti--site DIB PCB Layout Tipssite DIB PCB Layout Tips



• Use independent DC, AC, digital, and DSP options per site• Optimize the wait and capture times by analyzing the capture signal

graphically• Reduce test time through investigating the test program with accurate

test time profiler• Use high performance buffers on DIB to increase the repeatability of

the test and to decrease the measurement time• Utilize independent VM per DC channel to achieve parallel device pin

measurement• Utilize independent PPMU per HSD and AC option pins to achieve

parallel device pin measurement• Use PSET to improve the DC measurement repeatability • Utilize pattern controlled DC instruments to have true concurrent testing

Test Time Optimization Tips



Single(sec) Octal(sec) Effective single (sec) Parallelism (%)Yield (Dec. 3)

Catalyst 4.00 N/A 4.00 N/ATarget (July 03) 4.00 4.50 0.56 98.21Flex ( Oct. 23) 1.98 2.93 0.37 93.15 94.50%

Single(sec) Octal(sec) Effective single (sec) Parallelism (%)Yield (Dec. 3)

Catalyst ( Nov. 13) 3.50 N/A 3.00 N/ATarget (July 03) 3.80 4.20 0.53 98.50Flex ( Nov. 13) using 4 vhfac 1.90 3.50 0.44 87.97 93.00%Remark: We used 4 vhfac for the octal site testing, the parallelism is down about 7%

Single(sec) Quad(sec) Effective single (sec) Parallelism (%)Yield (Dec. 3)

Catalyst ( Nov. 13) 6.30 N/A 3.00 N/ATarget (July 03) 6.50 7.20 1.80 98.46Flex ( Nov. 26) using 2 vhfac 6.40 6.60 1.65 98.96 90.00%Remark: We used 2 vhfac for the quad site testing, the parallelism is down about 0.5%

Octal Site DVDP Test time

Quad site CD-RW Test time

Octal Site CDP Test time

3 Demo Devices Test Time Results on 3 Demo Devices Test Time Results on FLEXFLEX



* Throughput = (T_Catalyst – T_eff_FLEX) / T_eff-FLEX

Flex System Economics Compared to Catalyst System

281.8%695.5%981.1%Throughput Advantage Flex Vs. Single *

1.65 s0.44 s0.37 sEffective Flex System Test Time

6.40 s6.60 s (Quad)

1.90 s3.50 s

1.98 s2.93 s

SingleOctalFlex

6.30 s3.50 s4.00 sSingleCatalyst

CD-RW Test Time

DVD-P Test Time

CD-P Test TimeSitesSystem



Conclusion

• Multi-Site tester architecture provides

– Ability to test multisite– Ability to perform concurrent testing– Ability to develop test programs faster

• Multi-Site tester achieves lower cost of test for customer demo devices

– Efficient multisite testing – Higher parallelism– Higher throughput

semiconductor solutions multi-site test (soc)soc.yonsei.ac.kr/test/papers/7th/[f-1].pdfpattern...

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