seminar report on ivy bridge

IVY BRIDGE PROCESSOR MICROARCHITECTURE

A

SEMINAR REPORT

ON

IVYBRIDGE

Department of Computer


CHAPTER 1: INTRODUCTION`

The third generation of Intel Core processors microarchitecture codenamed Ivy Bridge, are

released with quad-core models for both desktop and laptop computers. This introduces a new

generation of optimization and new integrated graphics architecture support DirectX 11 which

are one of the real news this generation. provides the latest technology for applications advanced,

this quad-core processor features 8-core multitasking and additional L3 cache. With excellent

performance along with a speed incredible, also in this generation processors provides more

intelligence to your PC, allowing applications and security protocols work great in the

background. It has a screen resolution of most current and sharp thanks to technology Intel HD

2000 graphics integrated on the second generation Intel Core processors. This is a new

generation 22nm optimization of existing models. No introduction of new instructions or

changes important in architecture except some optimizations and certainly important, a graph

fully renovated in our tests has been pleasantly surprising. This generation also receives

frequency increases and reductions of greater than 15% in four models cores. A major change

that makes these models faster processors and more energetically efficient.

Fig. 1: Intel IVY BRIDGE Processor



With the introduction of the Intel microarchitecture codenamed Sandy Bridge, the

graphics processor has moved onto the same die as the CPU, and is now referred to as “processor

graphics”. In addition, processor graphics enjoys numerous architectural improvements that yield

significant performance improvements over previous generations of Intel® integrated graphics

parts. Ivy Bridge, provides another jump in functionality and performance over Sandy Bridge

microarchitecture. Ivy Bridge microarchitecture is manufactured on the new 22nm process

technology, incorporating Intel’s new tri-gate (or 3D) transistor technology. This innovative new

process yields greater performance at much lower power. For example, the new tri-gate

transistors exhibit 36% faster switching speed than the equivalent transistors on the legacy

process at the same voltage. Tri-gate transistors also leak about 10x less current in their off state,

resulting in a power saving of approximately 50% when using a comparable performance profile.

Although the Ivy Bridge microarchitecture has some significant differences from its

predecessor Sandy Bridge, it’s very easy to see that they are closely related to each other. There

are in fact no differences at the very top.

The table below compares the main features for both Intel® HD Graphics 3000 found on

the 2nd Generation Intel® Core™ processors and Intel® HD Graphics 4000 found on the 3rd

Generation Intel® Core™ processors.

Table 1: Intel® HD Graphics 3000 vs. Intel® HD Graphics 4000



CHAPTER 2: MICROPROCESSOR ARCHITECHTURE

Fig. 2: General Processor View

2.1 Microprocessor

It is the first processor on the market made with a 22nm process and enjoy also Trigate Intel

technology that designs the integrated transistors in a three-dimensional structure which

optimizes use of energy management processor. This causes the look Sandy Bridge exceeded in

frequency and overall process efficiency of consumption. Its 95w passed from 4 cores in models

only 77w in the same type of processor. That moderately helps in increasing frequencies and

adding a significantly more powerful graphics card than the last. Graphics also improves

connectivity and some other aspects already existing now also transferred to desktop solutions

such as Wireless Display, OpenCL, more computer processing power general graphics and other

more integrated into the chipset about which we will talk later. Processor now has 32 lines of

third-generation PCI Express, including modes 8GT/s, which can be distributed in configurations

of up to four graphics with links 8x. The cache is maintained in 8MB third level but this will be

Core i7 models higher end, the Core i5 models will have 6MB with lower amounts in two-core

or Core i3.



Of course maintains its basic features such as hyperthreading, the memory controller

integrated dual-channel DDR3 (XMP profiles 1.3), and DMI links to the chipset and dedicated

links for interfaces graphics where what's new. Now support HDMI 1.4a and account type is also

with Displayport 1.1 outputs. We can also control up to three screens directly from the integrated

graphics processor. Optimized Intel TurboBoost your system now also has several settings for

graphics as we are using one, two or four cores and also depending on the load of the graphics

card. For example, if a game requires only two cores then the graph will take much of the

improvement to increase the frequency of 1350MHz according to the processor. It is the first

Intel desktop processor of over 1400 million transistors.

2.2 7 Series Chipset

The chipset that will support the IvyBridge takes some days with us. Specifically since April

8. That was its release date and now gave cover to SandyBridge processors since both processors

share a 1155 socket contacts. In fact motherboards with chipsets sixth generation Ivy Bridge

processors can be mounted with the updates appropriate bios. The same goes for the seventh

generation that is Ivy Bridge oriented but also supports Sandy Bridge processors.



Fig. 3: An Ivy Bridge Core i7 Processor and Chipset



Fig. 4: Intel Z77 Express Chipset Platform Block Diagram

The Z77 chipset was the flagship model together with other similar variants as HM77 H77

or portable environments. We also find a B75aimed at business machines with the latest

improvements in system vPro Intel. The main novelty of this chipset, in almost all its variables,

is the integration of USB 3.0 natively (4 USB 3.0 ports and 12 USB 2.0 ports), becoming the first

Intel chipset built with this technology, the settings are maintained for 6Gbps SATA two ports

and four 3Gbps ports. It includes version 11 of Intel's RAID technology is added new graphics

connective capacity through FDI dedicated bus, introduces enhancements for enterprise

management systems (also for smaller IT departments), it adds support for the incorporation



Thunderbolt, will improve energy saving systems, maintaining the legacy PCI supporting some

versions and reduces the manufacturing process to 65nm.

Fig. 5: Intel Z77 Express Chipset Platform Internal Diagram

As the Z77 Motherboards ASUS Sabertooth are a good example of the type of platform

that offers the 7 series chipset Intel specifically for your model of higher range, the Z77.Among

its microarchitecture are the following examples that help us to compression its structure:

2.3 Intel ® Turbo Boost Technology 2.0

Dynamically increases the processor frequency as needed to benefit the power and thermal

headroom when operating.

2.4 Intel ® HT Technology

It allows each processor core to work on two tasks at the same time.

2.5 Intel ® Smart Cache

Dynamically assigned each processor core which reduces latency and improves performance of

the PC.



2.6 New Instructions AES-NI

It will increase the hardware acceleration of AES and also accelerate the execution of AES

applications.

2.7 CPU Speed

2.66 GHz to 3.33GHz

Fig. 6: Ivy Bridge General and Block Overview



The Core i7-3770k model becomes the spearhead with a price similar to Core i7-2700K, but

reducing consumption to 77W, the frequency are nailed(3.5GHz to 3.9GHz turbo mode), the

cache is also the same (8MB), also the number of cores and all other associated technologies. Of

course the Core i7-3770k receives the new Intel graphics which is definitely an improvement

important as it will allow us to achieve superior performance to models before and some

additional tricks. addition, has features such as :

1. The memory controller is integrated on the same processor.

2. Three-channel memory (192-bit data width).

3. The motherboard supports Intel Core i7 has four or six slots DIMM.

4. Supports only DDR3

5. Allows you to use the integrated DDR3 512 MB to 8 GB, you can also use 16 GB.

6. FSB is replaced in the interface Quick Path i7 and i5.

7. 731 million transistors (1,170 million in the Core i7 with 6 cores and12 MB of

cache).

Fig. 7: Standard Power 3rd Gen Intel Core Processors



CHAPTER 3: INSTRUCTION SET

The instruction set that works with Ivy Bridge Core i7 are the following:

1. x86 : It is the generic name given to certain microprocessors from Intel family, their

support and the basic architecture for these processors belong, by the end of their names

numbers: 8086, 80286, 80386, 80486, etc.

2. MMX : It is a SIMD instruction set designed by Intel and introduced in 1997 in their

Pentium MMX microprocessors. It was developed from September 1 inserted in the Intel

i860. It was supported by most manufacturers of x86 microprocessors since.MMX added

8 new records to the architecture, known as MM0to MM7 (hereinafter called

MMn). Indeed, these new records are mere alias records x87 FPU stack. For whatever it

is made with the FPU stack affects the MMX registers. Unlike the floating point stack,

registers MMn are fixed instead of relative, so that can be accessed randomly.

3. SSE : It is an extension to MMX instruction set processors Pentium III, introduced by

Intel in February 1999. Instructions SSE are especially suitable for decoding

MPEG2codec that is commonly used on DVD processing three-dimensional graphics and

voice recognition software. These were initially known as "KNI" by Katmai New

Instructions(Katmai was the codename of the first review of core Pentium III, Intel was

interested in distinguishing its new line of previous generation processors, the Pentium II.

4. SSE2 : It is one of the instruction sets of the IA-32 SIMD architecture. It was first used in

the first version of the Pentium 4 in2001. These extensions are designed to work with

advanced3D graphics, video encoding and decoding, recognition of voice, e-commerce,

Internet, applications engineering and scientific, etc..SSE2 extensions follow the same

pattern as those used in the SSE predecessors and MMX maintaining compatibility with

these extensions, but extends its model packages supporting double precision floating

values and whole packages of 128bits.

5. SSE3 : Known by the code name put Intel Prescott New Instructions (PNI) is the third

generation of SSE instructions for IA-32 architecture. Intel showed the SSE3 in early

2004with the revision of its CPU Pentium 4 Prescott called. In April 2005, AMD took

apart the SSE3 in reviewing E (called Venice and San Diego) of their Athlon 64

CPU.SSE3 adds 13 new instructions SSE2.



6. SSSE3 : Are minor improvements already introduced SSE3 extensions above line

Prescott, was presented at the processors Intel Core 2 Duo and Xeon. 32 new instructions

were added in order to improve execution speed.

7. x86-64 : It is an architecture based on the extension of the set ofx86 instructions to

handle 64-bit addresses. Besides a simple extension provides additional improvements as

doubling the number and size of the general-purpose registers and instructions SSE. This

is an architecture developed by AMD and implemented under the name of AMD64. The

first processor (personal computer) with support for this set of instructions was the

Opteron, released in April 2003. Later it has been implemented in multiple variants of the

Athlon 64 and later, and the Pentium 4 and Intel later, in the latter case a version of Intel

called Intel 64 (formerly EM64T).

8. SSE4.1 : It is an instruction set implemented in the microprocessor AMD K10 (K8L)

partially (only available SSE4a) and45nm Intel Core2 family and later. It was announced

on 27September 2006 at the Intel Developer Forum, showing only vague details of what

would eventually become the new set of instructions. For the next edition of the

developer forum, 2007, specified that would finally 47 instructions that make up the set

SSE4.these instructions were included with the core of the industry Penryn Intel Core 2,

consists of 47 instructions designed to improve performance in handling multimedia data,

games, cryptography and other applications.

9. SSE4.2 : Were implemented in the Intel Nehalem microarchitecture consist in 7

additional instructions designed to improve performance when working with word

processors and speed up some operations in specific applications such as scientific, these

are completed the 54 SSE4 instructions.

10. AVX : It is a set of 256-bit instructions developed by Intel Corporation as an extension to

the x86 instruction set utilized in Intel and AMD processors. Provides new features,

instructions and a new encoding scheme. Vector extension is a 256-bit SIMD operations

point for intensive floating. Improves performance in new applications, and some

existing, by managing data packets larger vector, and using more threads and cores in the

processor.



Mnemonic representation and function.

----------------------------------------------------------------

|Mnemonic |Op|SZAPC|~s|Description |Notes |

|---------+--+-----+--+--------------------------+-------------|

|ACI n |CE|*****| 7|Add with Carry Immediate |A=A+n+CY |

|ADC r |8F|*****| 4|Add with Carry |A=A+r+CY(21X)|

|ADC M |8E|*****| 7|Add with Carry to Memory |A=A+[HL]+CY |

|ADD r |87|*****| 4|Add |A=A+r (20X)|

|ADD M |86|*****| 7|Add to Memory |A=A+[HL] |

|ADI n |C6|*****| 7|Add Immediate |A=A+n |

|ANA r |A7|****0| 4|AND Accumulator |A=A&r (24X)|

|ANA M |A6|****0| 7|AND Accumulator and Memory|A=A&[HL] |

|ANI n |E6|**0*0| 7|AND Immediate |A=A&n |

|CALL a |CD|-----|18|Call unconditional |-[SP]=PC,PC=a|

|CC a |DC|-----| 9|Call on Carry |If CY=1(18~s)|

|CM a |FC|-----| 9|Call on Minus |If S=1 (18~s)|

|CMA |2F|-----| 4|Complement Accumulator |A=~A |

|CMC |3F|----*| 4|Complement Carry |CY=~CY |

|CMP r |BF|*****| 4|Compare |A-r (27X)|

|CMP M |BF|*****| 7|Compare with Memory |A-[HL] |

|CNC a |D4|-----| 9|Call on No Carry |If CY=0(18~s)|

|CNZ a |C4|-----| 9|Call on No Zero |If Z=0 (18~s)|

|CP a |F4|-----| 9|Call on Plus |If S=0 (18~s)|

|CPE a |EC|-----| 9|Call on Parity Even |If P=1 (18~s)|

|CPI n |FE|*****| 7|Compare Immediate |A-n |

|CPO a |E4|-----| 9|Call on Parity Odd |If P=0 (18~s)|

|CZ a |CC|-----| 9|Call on Zero |If Z=1 (18~s)|

|DAA |27|*****| 4|Decimal Adjust Accumulator|A=BCD format |

|DAD B |09|----*|10|Double Add BC to HL |HL=HL+BC |

|DAD D |19|----*|10|Double Add DE to HL |HL=HL+DE |



|DAD H |29|----*|10|Double Add HL to HL |HL=HL+HL |

|DAD SP |39|----*|10|Double Add SP to HL |HL=HL+SP |

|DCR r |3D|****-| 4|Decrement |r=r-1 (0X5)|

|DCR M |35|****-|10|Decrement Memory |[HL]=[HL]-1 |

|DCX B |0B|-----| 6|Decrement BC |BC=BC-1 |

|DCX D |1B|-----| 6|Decrement DE |DE=DE-1 |

|DCX H |2B|-----| 6|Decrement HL |HL=HL-1 |

|DCX SP |3B|-----| 6|Decrement Stack Pointer |SP=SP-1 |

|DI |F3|-----| 4|Disable Interrupts | |

|EI |FB|-----| 4|Enable Interrupts | |

|HLT |76|-----| 5|Halt | |

|IN p |DB|-----|10|Input |A=[p] |

|INR r |3C|****-| 4|Increment |r=r+1 (0X4)|

|INR M |3C|****-|10|Increment Memory |[HL]=[HL]+1 |

|INX B |03|-----| 6|Increment BC |BC=BC+1 |

|INX D |13|-----| 6|Increment DE |DE=DE+1 |

|INX H |23|-----| 6|Increment HL |HL=HL+1 |

|INX SP |33|-----| 6|Increment Stack Pointer |SP=SP+1 |

|JMP a |C3|-----| 7|Jump unconditional |PC=a |

|JC a |DA|-----| 7|Jump on Carry |If CY=1(10~s)|

|JM a |FA|-----| 7|Jump on Minus |If S=1 (10~s)|

|JNC a |D2|-----| 7|Jump on No Carry |If CY=0(10~s)|

|JNZ a |C2|-----| 7|Jump on No Zero |If Z=0 (10~s)|

|JP a |F2|-----| 7|Jump on Plus |If S=0 (10~s)|

|JPE a |EA|-----| 7|Jump on Parity Even |If P=1 (10~s)|

|JPO a |E2|-----| 7|Jump on Parity Odd |If P=0 (10~s)|

|JZ a |CA|-----| 7|Jump on Zero |If Z=1 (10~s)|

|LDA a |3A|-----|13|Load Accumulator direct |A=[a] |

|LDAX B |0A|-----| 7|Load Accumulator indirect |A=[BC] |

|LDAX D |1A|-----| 7|Load Accumulator indirect |A=[DE] |



|LHLD a |2A|-----|16|Load HL Direct |HL=[a] |

|LXI B,nn |01|-----|10|Load Immediate BC |BC=nn |

|LXI D,nn |11|-----|10|Load Immediate DE |DE=nn |

|LXI H,nn |21|-----|10|Load Immediate HL |HL=nn |

|LXI SP,nn|31|-----|10|Load Immediate Stack Ptr |SP=nn |

|MOV r1,r2|7F|-----| 4|Move register to register |r1=r2 (1XX)|

|MOV M,r |77|-----| 7|Move register to Memory |[HL]=r (16X)|

|MOV r,M |7E|-----| 7|Move Memory to register |r=[HL] (1X6)|

|MVI r,n |3E|-----| 7|Move Immediate |r=n (0X6)|

|MVI M,n |36|-----|10|Move Immediate to Memory |[HL]=n |

|NOP |00|-----| 4|No Operation | |

|ORA r |B7|**0*0| 4|Inclusive OR Accumulator |A=Avr (26X)|

|ORA M |B6|**0*0| 7|Inclusive OR Accumulator |A=Av[HL] |

|ORI n |F6|**0*0| 7|Inclusive OR Immediate |A=Avn |

|OUT p |D3|-----|10|Output |[p]=A |

|PCHL |E9|-----| 6|Jump HL indirect |PC=[HL] |

|POP B |C1|-----|10|Pop BC |BC=[SP]+ |

|POP D |D1|-----|10|Pop DE |DE=[SP]+ |

|POP H |E1|-----|10|Pop HL |HL=[SP]+ |

|POP PSW |F1|-----|10|Pop Processor Status Word |{PSW,A}=[SP]+|

----------------------------------------------------------------

----------------------------------------------------------------

|Mnemonic |Op|SZAPC|~s|Description |Notes |

|---------+--+-----+--+--------------------------+-------------|

|PUSH B |C5|-----|12|Push BC |-[SP]=BC |

|PUSH D |D5|-----|12|Push DE |-[SP]=DE |

|PUSH H |E5|-----|12|Push HL |-[SP]=HL |

|PUSH PSW |F5|-----|12|Push Processor Status Word|-[SP]={PSW,A}|

|RAL |17|----*| 4|Rotate Accumulator Left |A={CY,A}<- |



|RAR |1F|----*| 4|Rotate Accumulator Righ |A=->{CY,A} |

|RET |C9|-----|10|Return |PC=[SP]+ |

|RC |D8|-----| 6|Return on Carry |If CY=1(12~s)|

|RIM |20|-----| 4|Read Interrupt Mask |A=mask |

|RM |F8|-----| 6|Return on Minus |If S=1 (12~s)|

|RNC |D0|-----| 6|Return on No Carry |If CY=0(12~s)|

|RNZ |C0|-----| 6|Return on No Zero |If Z=0 (12~s)|

|RP |F0|-----| 6|Return on Plus |If S=0 (12~s)|

|RPE |E8|-----| 6|Return on Parity Even |If P=1 (12~s)|

|RPO |E0|-----| 6|Return on Parity Odd |If P=0 (12~s)|

|RZ |C8|-----| 6|Return on Zero |If Z=1 (12~s)|

|RLC |07|----*| 4|Rotate Left Circular |A=A<- |

|RRC |0F|----*| 4|Rotate Right Circular |A=->A |

|RST z |C7|-----|12|Restart (3X7)|-[SP]=PC,PC=z|

|SBB r |9F|*****| 4|Subtract with Borrow |A=A-r-CY |

|SBB M |9E|*****| 7|Subtract with Borrow |A=A-[HL]-CY |

|SBI n |DE|*****| 7|Subtract with Borrow Immed|A=A-n-CY |

|SHLD a |22|-----|16|Store HL Direct |[a]=HL |

|SIM |30|-----| 4|Set Interrupt Mask |mask=A |

|SPHL |F9|-----| 6|Move HL to SP |SP=HL |

|STA a |32|-----|13|Store Accumulator |[a]=A |

|STAX B |02|-----| 7|Store Accumulator indirect|[BC]=A |

|STAX D |12|-----| 7|Store Accumulator indirect|[DE]=A |

|STC |37|----1| 4|Set Carry |CY=1 |

|SUB r |97|*****| 4|Subtract |A=A-r (22X)|

|SUB M |96|*****| 7|Subtract Memory |A=A-[HL] |

|SUI n |D6|*****| 7|Subtract Immediate |A=A-n |

|XCHG |EB|-----| 4|Exchange HL with DE |HL<->DE |

|XRA r |AF|**0*0| 4|Exclusive OR Accumulator |A=Axr (25X)|

|XRA M |AE|**0*0| 7|Exclusive OR Accumulator |A=Ax[HL] |



|XRI n |EE|**0*0| 7|Exclusive OR Immediate |A=Axn |

|XTHL |E3|-----|16|Exchange stack Top with HL|[SP]<->HL |

|------------+-----+--+----------------------------------------|

| PSW |-*01 | |Flag unaffected/affected/reset/set |

| S |S | |Sign (Bit 7) |

| Z | Z | |Zero (Bit 6) |

| AC | A | |Auxilary Carry (Bit 4) |

| P | P | |Parity (Bit 2) |

| CY | C| |Carry (Bit 0) |

|---------------------+----------------------------------------|

| a p |Direct addressing |

| M z |Register indirect addressing |

| n nn |Immediate addressing |

| r |Register addressing |

|---------------------+----------------------------------------|

|DB n(,n) |Define Byte(s) |

|DB 'string' |Define Byte ASCII character string |

|DS nn |Define Storage Block |

|DW nn(,nn) |Define Word(s) |

|---------------------+----------------------------------------|

| A B C D E H L |Registers (8-bit) |

| BC DE HL |Register pairs (16-bit) |

| PC |Program Counter register (16-bit) |

| PSW |Processor Status Word (8-bit) |

| SP |Stack Pointer register (16-bit) |

|---------------------+----------------------------------------|

| a nn |16-bit address/data (0 to 65535) |

| n p |8-bit data/port (0 to 255) |

| r |Register (X=B,C,D,E,H,L,M,A) |

| z |Vector (X=0H,8H,10H,18H,20H,28H,30H,38H)|



|---------------------+----------------------------------------|

| + - |Arithmetic addition/subtraction |

| & ~ |Logical AND/NOT |

| v x |Logical inclusive/exclusive OR |

| <- -> |Rotate left/right |

| <-> |Exchange |

| [ ] |Indirect addressing |

| [ ]+ -[ ] |Indirect address auto-inc/decrement |

| { } |Combination operands |

| ( X ) |Octal op code where X is a 3-bit code |

| If ( ~s) |Number of cycles if condition true |

----------------------------------------------------------------



CHAPTER 4: SYSTEM USED

4.1 Package

They have a package of 22 nano meters and its construction is based on transistors Tri -Gate

(less than 50% of energy consumption at the same level of performance with respect to the

planar transistors). The surface of the package has 995 million transistors. Support

HyperThreading technologies and Turbo boost, although some features are disabled capadas or

to differentiate between the different market segments, as was the case with previous

generations. Serial clock frequencies from 2.3 GHz to 3.4GHz With Turbo Boost enabled, you

reach the 3.8 GHz overclock without practicing manual. The integrated GPU with frequencies

from 650 MHz to 850MHz, and if enabled Turbo Boost up to 1.35 GHz bandwidth ring bus of

256 bits per cycle. The bus connects the cores. Memory controller enhanced with a maximum

bandwidth of 25.6 GB/s and support for DDR31600 MHz dual-channel operation with two load /

store per cycle. Thermal Design Power W between 35 and 95 W. Dual and Quad core available

from the output of the same, of sextuple and octuple core hit the market later. Improved

performance with transcendent function operations, AES encryption and SHA-1. Additional

support for PCI Express 3.0. Multiplier maximum of x63 in the processor(In Sandy Bridge it was

x57). RAM memory support up to 2800MT/s in increments of 200 MHz Intel HD Graphics with

support for DirectX 11, OpenGL 3.1 and OpenCL 1.1.The GPU will have to have up to

16execution units. The GPU has to own up to 16 units of execution. A new number generator

and instruction RdRand, named in key Bull Mountain.

Fig. 8: Chipset



4.2 Power source.

As some may have expected, it has achieved a new feat of overclocking using CPUs Ivy Bridge

from Intel. The Core i7-3770K chip was placed on a motherboard Gigabyte Z77X-UD5H and

backed by 4 GB of DDR3- 2133 MHz (two modules of 2GB each one).

Meanwhile, a power supply (PSU) Corsair AX1200W high end provided the necessary

energy. When using a clock multiplier value of 63.0x, the i7-3770K managed to climb up to

6.616 GHz, while the clock speed of 6584.86 MHz was achieved on a test 104.52 x 63. Addition

of this, when is left to 6.511 GHz of clock frequency remained stable after being subjected to the

test SuperPi. More precisely, 1M time was 5.585 s. The test shows that the chip can withstand a

lot and exhibit good potential for overclocking and stability even when present only cooling air

or water. Of course, 6.616 GHz is not really a record. After all, the first place belongs to AMD

FX-8150 (8.58 GHz).

4.3 Frequency of Operation.

To the like that the pieces Sandy Bridge Core i7 current the CPU 3770K alsooffer shared L3

memory of 8 MB, but its integrated GPU has been updated to the new HD 4000 which packs

30% more units of execution (EUS).thermal design power (TDP) of the chip was also modified

as the new Tri-Gate technology used for 22nm Ivy Bridge helps manufacturing to reduce energy

consumption of the CPU. The end result is a chip that works on the same frequencies as the

Corei7-3700K and although it has a graphics core more fast, its TDP is 19% more low (77W vs

95W). Allike that all the others processors of the series K Launched by Intel untilnow, the Core

i7-3770K also features an unlocked multiplier which means overclockers will be able to boost

the frequency of operation of the CPU beyond what Intel had originally specified.

4.4 The New Graphics.

The new Intel HD Graphics 4000 does not go into too much detail of architecture but increases

performance dramatically and also adds support already quite widespread standards like OpenCL

and DirectX 11. This makes it more compatible with modern games exploiting recent techniques

with notable improvement in other areas such as overall computing multimedia making a greater

contribution. It's power also increases remarkably turning this graphics card a real alternative to

enjoy modern games average qualities and normal relations with quite respectable rates of

speed. We have tested some of these games like F1 2011 or HAWX 2 in DirectX 11 mode at



resolutions of 1920x1080 without filters and with average qualities and the results are quite

surprising for us, for Intel integrated graphics, with more than 30FPS average.

Fig. 9: Game View on a system with Ivy Bridge processor

Without drivers optimized Diablo 3 and moves at an average of 20-25FPS at a resolution of

1400x900 medium quality points with anti aliasing.

Fig. 10: High resolution graphics view

The F1 2011 DirectX acting moves, with and without FSAA normal adjustments to a35fps average with a screen resolution 1920x1080npuntos.allows the new graph, using Intel's QuickSync technology, compress video more efficiently than the cores themselves and further



processor freeing process can be available for other tasks. The improvement in our Core i7-3770k is 3 times faster video compression high definition with the HD 4000 with its own processor cores with overclocking quite high.

Fig. 11: Supports an iPad platform

Programs like PowerDirector, MediaConverter, Total Media Theater, and many others

already support Intel's QuickSync technology. Compress video for an ipad now we can make up

to 3 times less time than using conventional cores.

Another improvement is that since these early drivers and we have a good video acceleration

support programs as widespread as MPC-HC, VLC and Flash with the fuel even ridiculous that

in our tests, with1080p videos, barely scratches the 1% CPU consumption.

Among other features of Ivy Bridge microprocessor we will address the following:

1. Additional improvements in the manufacturing process.

Besides using 22nanometers each may have a lower power since they use a triple gate design. As

we all worked to create micros as energy efficient as possible.

2. Integrated graphics.

It adds support for DirectX 11. Its benefits are greater. Intel realized that this was his greatest

failure and has tried to solve.



3. Memory cache.

Because it has more space the L3 cache memory is much greater.

4. Consumption.

It spends a TDP of 85 watts to 77 in midrange mics for instance.

Fig. 12: Displaying working of the processor



CHAPTER 5: CONTROL SIGNALS

5.1 Clock.

As the clock type that handle is made various tests to contemplate a good overclocking

performance of these tests covered the CPU performance in steady state and accelerated

frequencies and, even if you have not mentioned about exact figures, i7 processor ES-3770K

was, on average, 10% faster than the current Core i7-2600K.

Regarding the overclocking potential, the chip also recorded a performance similar to their

counterparts in the Sandy Bridge collection and the highest frequency reached with all active

cores was established at 4.8 GHz Core i7-3770K The include four computing cores with support

for Hyper-Threading, with basic frequency 3.5GHz and technology will also support Intel's

Turbo Boost can increase their operation speed of 3.9GHz when not all nuclei are loaded.

Making a comparison between the previous version of Ivy Bridge, Sandy Bridge as shown in the

table:

Table 2: Comparison of Sandy Bridge and Ivy Bridge on Overclocking features



5.2 Instruction cycle.

The 128-bit SSE instructions are issued at a throughput rate of one process per clock cycle,

allowing a new level of efficiency of processing SSE4 optimized applications. Streaming SIMD

Extensions (SSE) is a SIMD instruction set (Single Instruction, Multiple Data - Single

Instruction, Multiple Data) added in the year1999 to the Pentium III processor, as an extension to

the x86 architecture as a response to the 3DNow!, AMD had implemented years ago. Version 4.2

of vector extensions Intel SSE brings back to the future to the x86 ISA adding new handling

instructions chains. "Back to the Future" because the support chain level ISA is a characteristic

processing of CISC architectures that are currently considered obsolete post-RISC years. But the

chain of new SSE 4.2 instructions are intended to expedite the processing of XML, which makes

them perfect for the Web and future applications based on XML.SSE 4.2 also includes a CRC

instruction that accelerates storage and applications network and an instruction for a variety

useful POPCNT task specified pattern. In addition, to provide better support multi-threaded

applications, Intel has reduced latency primitives threads synchronization. Virtualization on the

front accelerates transitions and has some improvements substantially, in its virtual memory

system that greatly reduces the number of such transitions required by the Hypervisor.

5.3 Control Unit.

To the Core i7 3770k a program called Turbo Mode is a performance feature that automatically

unlocks containers additional speed (multiplier) and allows the processor to auto-overclocking

based on thermal conditions and workload. For example, if the Power Control Unit (PCU)

detects that only one core is active and the other three are in an idle state, energy is used and

unused capacity that active thermal overclock a single core to ensure superior performance of a

single thread. Conversely, if you are running a multi-threaded application, the CPU heat capacity

measure and if the processor is running is cool enough overclock the six cores. Turbo can

provide an improvement in the speed of 400Mhzsingle and double workloads screw-thread 300

MHz triple300MHz workloads, and in applications that use four or more threads. Ivy Bridge also

handles Turbo Boost modes faster, and clings to the course, which also helps to improve

performance .



Fig. 13: Processor details of a CPU with Ivy Bridge processor



CHAPTER 6: CONCLUSION

The new generation of Intel Core processors, codenamed Ivy Bridge are largely unchanged from

previous ones but with key improvements in much needed areas. It’s reduction of manufacturing

process and production optimizations allow you to be up to 10-20% faster compared to previous

generation processors. This adds up to a much more powerful graphics and more modernized

where find better acceleration overall result, better graphics and enough speed. All well seasoned

with a consumption reduction of nearly 20% of these processors makes an interesting bet of

performance, integration and consumption reduction. We might see this trend continue, get more

effective architectures by the developments in fabrication technologies.


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