sequential logic - ece:course page
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1
Sequential Logic
Lecture 918-322 Fall 2003
Textbook: [Sections 7.1 7.2]
Overview
The third dimension: Sequential systemsMemory function ⌧Static (positive feedback)⌧Dynamic
Memory elements ⌧Latches ⌧Flip-Flops
Thursday: Clocking disciplines
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Positive Feedback: Bistability
V1
V2
V3
V2
V1 V2 V3a a
V1 = V3
V2
A
B
C
a a
VDD
Only A and B are stable operation points
Meta-stability
V1 = V3
V2C
If gain of inverter > 1C is meta-stable pointCircuit cannot remain at C
metastable
0 1
A
Bδ
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How to use Bi-stability
Now we know how store a bit (bi-stability)How can we manipulation (write) that bit
Solution 1: Interrupt the feedback Solution 2: Overpower the feedback loop (force it into another state)
Next we’ll see mostly Solution 1
SR Latch
QS
R Q
S R Q Q
0101
0011
Q100
Q010
QS
R Q
S R Q Q
1010
1100
Q101
Q011
© Prentice Hall 1995
S
R
Q
Q
S
R
Q
Q
Shows that it operates on negative logic (negative-going pulse)
Logically Interrupting the feedback loop
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JK Flip-Flop
QJ
K Q
Jn Kn Qn+1
0011
0101
Qn01Qn
(b)
(c)
S
R
Q
Q Q
J
K
φ
Q
(a)φ
© Prentice Hall 1995
Two improvements to the SR:1. No “illegal inputs”, state of Q influences which input is enabled2. Introduction of clock signal (only change state when high)
Other Flip-Flops
QJ
K Qφ
T
φQJ
K Qφφ
D
Q
Qφ
T
Toggle Flip-Flop
© Prentice Hall 1995
Q
Qφ
D
Delay Flip-Flop
a.k.a. D transparent latch
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D Latch
Equivalent circuit
D
Φ
0
1Q
The Race Problem
Q
Qφ
D
1
t
t
tloop
φ
© Prentice Hall 1995
D
Signal can race around during φ = 1
6
Race Fixes: Master-Slave Flip-Flop
S
R
Q
Q Q
QS
R
Q
Q
J
K
φ
MASTER SLAVE
QJ
K Qφ
PRESET
CLEAR
SI
RI
© Prentice Hall 1995
One-catching!(The circuit is sensitive to input changes while φ = 1)
FF operates at the falling edge of the clock
= 1
1
1= 0
0
1
Needs 38 transistors to implement!
Race Fixes: Master-Slave
Comb.Logicf1()
SComb.Logicf2()
M SM
Comb.Logicf1()
SComb.Logicf2()
M SM
Comb.Logicf1()
SComb.Logicf2()
M SM
Master: ClosedSlave: Transparent
Master: TransparentSlave: Closed
Master: ClosedSlave: Transparent
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Race Fixes: Edge Triggering #1
φ
In
X
Out
tpLH
© Prentice Hall 1995
φ
In XN2N1
Out
Edge-Triggered FF #2
QJ
KQ
>φ
© Prentice Hall 1995
φ
S
R
Q
Q
Q
J
K
QJ and K are sampled at the low-going edge of φand generate short pulses on S and R
Negative edge-triggered FF
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Single-Phase Clock: Parameters of Interest
data
clk
Q
clk-to-Q (propagation) delay (tpFF)
hold time
setup time
cycle time
Unstable data
Maximum Clock Frequency
F F’s
LOGIC
tp,comb
φ
tp,FF + tp,comb + tsetup < T
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Overview
The third dimension: Sequential systemsMemory function ⌧Static (positive feedback)⌧Dynamic
Memory elements ⌧Latches ⌧Flip-Flops
SR Flip-Flop
VDD
Q
Q
RS
φφM1 M3
M4M2
M6
M5 M7
M8
© Prentice Hall 1995
= 10 =
= 1
Ratioed logic
A master-slave D-FF implementation based on this structure would require only 22 (10+10+2) transistors!
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6-Transistor CMOS SR-Flip Flop
VDD
φ
M1 M3
M4M2
M5R
φ
S
Very popular in static memories!Solution 2: Overpowering the feedback loop
D-latch(1)
D
Q
QQQ
VDD
D
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D-latch(2)
C
C
Q
Q
D
C C
D
C
Q
Q
C = 0
=0
D-latch(3)
C
QD
C Make this really weakTherefore D input overpowers
feedback
How to make weak inverter:W/L: Make W small or make L large
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D Flip-Flop (Master-Slave)
D
ΦΦ
Q
Q
Φ (Controls operation & provides synchronization)Φ
Φ
t0
1
Load Master Transfer to Slave
D
Q
Q
Φ
Master Slave
DFF (Clear and Set)
D
Φ Φ
ΦΦ
Set
Clear
Q
Q
Set = 1: Clear = 1 (AND2 -> NOT same as the previous circuit)Clear = 0 (Q = 1)
Set = 0: Clear = 1 (Q = 1)Clear = 0 forbidden!
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DFF (Load Control)
D
Φ Φ
Q
Q
ΦΦ
Load
master slave
φ⋅Load
WARNING: This is now dynamic logic! We’ll talk about that later
Registers with DFFs
D1 Q
Φ[0]
[1]Φ
D2 Q
Dn-2 Q
Φ[n-2]
[n-1]Φ
Dn-1 Q
:
Q
[0]
[1]
Q
[n-1]
Φ
Q
:
Combinationallogic
Primary outputs
Primary inputs
Present state
Next state
Huffman model of FSMs