SERIAL I/O WITH 8085

Basics of serial communication

PROCESSOR

(PARALLEL)

DEVICEMODEM

(SERIAL)

PARALLEL TO SERIAL

SERIAL TO PARALLEL

SERIAL I/0 MODE

TRANSMITTER RECEIVER

SYNCHRONOUS TRANSMISSIONCLK

SYNC SYNC

DATA

ASYNCHRONOUS TRANSMISSIONStart and stop bits

SYNCHRONOUS • BLOCK OF DATA TRANSMITTED ALONG WITH SYNC INFORMATION• HIGH SPEED TRANSMISSION

ASYNCHRONOUS•CHARACTER CARRIES INFORMATION WITH START AND STOP BITS•WHEN NO DATA IS TRANSMITTED RECEIVER STAYS AT LOGIC 1 CALLED MARK ; LOGIC 0 CALLED SPACE•TRANSMISSION STARTS WITH ONE START BIT AND ONE OR MORE STOP BITS . THIS IS FRAMING

Serial Interfaces: RS-232

•DB25S is a 25 pin connector withfull RS-232 functionality•The computer socket has a femaleouter casing with male connectingpins•The terminating cable connectorhas a male outer casing withfemale connecting pins

TTL to RS-232

Types of equipmentDTE Data Terminal EquipmentOriginally applied to CRT terminals or other input devicesToday, DTE mainly applies to a computerDCE Data Communication EquipmentOriginally applied to modems or similar communicationsequipment Still applies today A modem is a device that converts a digital signal (e.g. froman RS232 interface) to an analogue signal for transmissionover a traditional telephone line (MODEM: MOdulator-DEModulator)

VOLTAGE LEVEL

+3V TO +15 VLOGIC 0

VOLTAGE LEVEL

-3V TO -15 VLOGIC 1

BUT USUSALLY LOGIC 1 +12VLOGIC 0-12V

????!!!!!!

YEP…. THATS RIGHT…..HERE WE USE

NEGATIVE TRUE LOGIC

• TO MAKE RS 232 COMPATIBLE WITH TTL LOGIC ,• VOLTAGE TRANSLATORS CALLED LINE DRIVERS & LINE RECEIVERS ARE USED

VOLTAGE TRANSLATORS

LINE DRIVERSMC1488 CONVERTS

LOGIC 1 -9VLOGIC 0+9V

LINE RECEIVERSMC1489 CONVERTS-9VLOGIC 1(+3.4V)+9VLOGIC 0(0.2V)

RS232 pins

Data signals

Control signals

Timing signals

grounds

SIGNALS OF RS232

We are concerned about,

11 bits required to send a single character (10 if one stop bits are used) Bit rate (bits/sec): actual rate at which bits are transmittedBaud rate: rate at which the signalling elements, used to represent bits, are transmitted

DTEMICRO

COMPUTER

DCE MODEM

2

3

7 7

3

2TX

TXRX

RX

GND

DTE Vs DCE

DTE DTE

2

3

7 7

3

2TX

RXRX

TX

GND

DTE Vs DTE

*NULL MODEM CONNECTION

Typical System Connections

LOOP-BACK

CONNEC-TIONS

• used to test hardware

NULL MODEM

COMMUNI-CATION

• Used for communica-tion 7 7

SERIAL INTERFACES : 8251A USART

The functions and requirement for SERIAL I/O are,Input port & Output port for interfacingDATA TX MPU converts parallel to serialDATA RX MPU converts serial to parallel

Synchronization between MPU and slow peripheral

USART – Universal Synchronous /Asynchronous Receiver/ Transmitter It incorporates all the above features in a single chip and other sophisticated functions for serial communication.

It is a programmable device i.e its functions and specifications for serial i/o can be determined by writing instructions to its internal registers

8251A USART device widely used for serial i/o

The 8251A Programmable Communication Interface

Programmable chip for synchronous and

asynchronous communication

28 pin DIP

Enhanced version of 8251

8251

A

8251A- BLOCK DIAGRAM

READ/WRITE CONTROL LOGIC

• Interfaces 8251 with MPU

• Determines functions acc. To control word

• Monitors data flow

TRANSMITTER

• Converts parallel word from MPU to serial bits

RECEIVER

• Converts serial bits to parallel word

DATA BUS BUFFER

• 8 bit data bus

MODEM CONTROL

• To establish communication through modems over telephone lines

8251A- PIN DIAGRAM

PIN DESCRIPTION PIN DESCRIPTION

D7-D0 DATA BUS C/D’ CONTROL/DATA

RD’ READ COMMAND WR’ WRITE COMMAND

CS’ CHIP SELECT CLK CLOCK PULSE

RESET RESET TxC’ TRANSMITTER CLOCK

TxD TRANSMITTER DATA RxC’ RECEIVER CLOCK

RxD RECEIVER DATA RxRDY RECEIVER READY

TxTDY TRANSMITTER READY DSR’ DATA SET READY

DTR’ DATA TERMINAL READY SYNDET/BD

SYNC DETECT/ BREAK DETECT

RTS’ REQUEST TO SEND DATA CTS’ CLEAR TO SEND DATA

TxE TRANSMITTER EMPTY Vcc +5V SUPPLY

GND GROUND

READ/WRITE CONTROL LOGIC AND REGISTERS

INPUT SIGNALS

CS’ – CHIP SELECT LOGIC 0 8251 is selected by the MPU

RD’ – READ SIGNALLOGIC 0 The MPU reads the status from status register or accepts

input from data bufferWR’ – WRITE SIGNAL

LOGIC 0 The MPU writes in the control register or sends data to output buffer

SIX INPUT SIGNALS

THREE BUFFER REGISTERS• STATUS REG.• CONTROL REG• DATA REG.

C/D’– CONTROL / DATA LOGIC 0 data buffer is addressed LOGIC 1 control register or status register

is addressed CONTROL REGISTER - ->WR’

STATUS REGISTER -- > RD’

RESET – Reset LOGIC 1 forces 8251 to RESET and enters

into idle mode CLK - clock

REFERS TO SYSTEM CLOCKNecessary for communication with the processor

REGISTERS CONTROL REGISTER

16 BIT REGISTER first byte MODE INSTRUCTION ( WORD ) second byte COMMAND INSTRUCTION ( WORD ) Register can be accessed when C/D’ is HIGH and WR’ is

LOW STATUS REGISTER

Input register that checks the READY status of the peripheral

Register can be accessed when C/D’ is HIGH and RD’ is LOW

DATA REGISTER 8 BIT bidirectional register – addressed as input or output Register can be accessed when C/D’ is LOW

TRANSMITTER SECTION

TRANSMITTER - CONVERTS PARALLEL FROM MPU TO SERIAL

TWO REGISTERS – BUFFER REGISTER – TO HOLD 8 BITS - OUTPUT REGISTER – TO CONVERT TO STREAM OF SERIAL BITS

THREE OUTPUT AND ONE INPUT SIGNALS

INPUT SIGNAL : TXC’ - TRANSMITTER CLOCK

CONTROLS THE RATE AT WHICH BITS ARE TRANSMITTED BY USARTCLOCK FREQ – 1/16/64 TIMES THE BAUD

OUTPUT SIGNAL : TXD - TRANSMIT DATA

SERIAL BITS ARE TRANSMITTED ON THIS LINE

TxRDY – TRANSMITTER READY LOGIC 1 – BUFFER EMPTY; USART READY TO ACCEPT TO INTERRUPT MPU or INDICATE STATUS

TxE – TRANSMITTER EMPTY LOGIC 1 – OUTPUT REGISTER IS EMPTY LOGIC 0 - BYTE IS TRANSFERRED FROM BUFFER TO REG.

RECEIVER SECTION

RECEIVER - CONVERTS SERIAL TO PARALLEL TWO REGISTERS - INPUT REGISTER – TO HOLD SERIAL

8 BITS WITH START & STOP BITS AND CONVERT THEM TO PARALLEL - BUFFER REGISTER – TO STORE PARALLEL BITS

TWO INPUT AND ONE OUTPUT SIGNALSINPUT SIGNAL :

RXC’ - RECEIVER CLOCKCONTROLS THE RATE AT WHICH BITS ARE RECEIVED BY USARTCLOCK FREQ – 1/16/64 TIMES THE BAUD

RXD - RECEIVE DATA SERIAL BITS ARE RECEIVED ON THIS LINE

OUTPUT SIGNAL : RxRDY – RECEIVER READY

LOGIC 1 – USART HAS A CHARACTER IN THE BUFFER REGISTER NAD READY TO TRANSFER TO MPU TO INTERRUPT MPU or INDICATE STATUS

8251 mode register- MODE WORD

7 6 5 4 3 2 1 0 Mode register

Number of Stop bits

00: invalid01: 1 bit10: 1.5 bits11: 2 bits

Character length

00: 5 bits01: 6 bits10: 7 bits11: 8 bits

Baud Rate

00: Syn. Mode01: ASYNC x1 10: ASYNC x16 11: ASYNC x64

PARITY CONTROLX0 – NO PARITY01 – ODD PARITY11 – EVEN PARITY

Command Register

Status Register

INITIALISING THE 8251A

MPU INFORMS 8251 – MODE, BAUD, STOP BITS, PARITY CONTROL WORDS TO BE LOADED FROM MPU TO 8251

MODE WORD

SPECIFIESCHARACTERIS

TICSBAUD, PARITYNUMBER OF

STOP BITS

ENABLES DATA TRANSMISSION OR RECEPTION

PROVIDES INFORMATION

REGARDING REGISTER STATUS

AND TRANSMISSION

ERRORS

RESET OPERATION

WRITE COMMAND WORD TO CONTROL REGISTER

OPERATION FLOW