sg2524, sg3524, sg3524y regulating pulse...
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SG2524, SG3524, SG3524YREGULATING PULSE-WIDTH MODULATORS
SLVS077A – APRIL 1977 – REVISED AUGUST 1995
Copyright 1995, Texas Instruments Incorporated
4–3POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
• Complete PWM Power Control Circuitry
• Uncommitted Outputs for Single-Ended orPush-Pull Applications
• Low Standby Curren t . . . 8 mA Typ
• Interchangeable With Silicon GeneralSG2524 and SG3524
description
The SG2524 and SG3524 incorporate on singlemonolithic chips all the functions required in theconstruction of a regulating power supply, inverter,or switching regulator. They can also be used asthe control element for high-power-output applications. The SG2524 and SG3524 were designed for switchingregulators of either polarity, transformer-coupled dc-to-dc converters, transformerless voltage doublers, andpolarity converter applications employing fixed-frequency, pulse-width-modulation (PWM) techniques. Thecomplementary output allows either single-ended or push-pull application. Each device includes an on-chipregulator, error amplifier, programmable oscillator, pulse-steering flip-flop, two uncommitted pass transistors,a high-gain comparator, and current-limiting and shut-down circuitry.
The SG2524 is characterized for operation from –25°C to 85°C, and the SG3524 is characterized for operationfrom 0°C to 70°C.
AVAILABLE OPTIONS
TINPUT PACKAGED DEVICES
CHIP FORMTA
INPUTREGULATION
MAX (mV)SMALL OUTLINE
(D)PLASTIC DIP
(N)
CHIP FORM(Y)
0°C to 70°C 30 SG3524D SG3524N SG3524Y
–25°C to 85°C 20 SG2524D SG2524N —
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
IN–IN+
OSC OUTCURR LIM+CURR LIM–
RTCT
GND
REF OUTVCCEMIT 2COL 2COL 1EMIT 1SHUTDOWNCOMP
D OR N PACKAGE(TOP VIEW)
PRODUCTION DATA information is current as of publication date.Products conform to specifications per the terms of Texas Instrumentsstandard warranty. Production processing does not necessarily includetesting of all parameters.
SG2524, SG3524, SG3524YREGULATING PULSE-WIDTH MODULATORS
SLVS077A – APRIL 1977 – REVISED AUGUST 1995
4–4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
functional block diagram
T COL 2
OSC OUTEMIT 2
EMIT 1
COL 1
Vref
ReferenceRegulator
Comparator
Oscillator
SHUTDOWN
Error Amplifier
1
2
9
4
5CURR LIM –
CURR LIM+
GND8
10
+
–
+
–
NOTE A. Resistor values shown are nominal.
12
1113
143
IN–
IN+
COMP
1 kΩ10 kΩ
15
RT
CT
REF OUT16
6
7
Vref
Vref
Vref
Vref
VCC
Vref
SG2524, SG3524, SG3524YREGULATING PULSE-WIDTH MODULATORS
SLVS077A – APRIL 1977 – REVISED AUGUST 1995
4–5POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SG3524Y chip information
This chip, when properly assembled, displays characteristics similar to the SG3524. Thermal compression orultrasonic bonding may be used on the doped aluminum bonding pads. The chip may be mounted withconductive epoxy or a gold-silicon preform.
BONDING PAD ASSIGNMENTS
CHIP THICKNESS: 15 MILS TYPICAL
BONDING PADS: 4 × 4 MILS MINIMUM
TJmax = 150°C
TOLERANCESARE ±10%.
ALL DIMENSIONS ARE IN MILS.
89
79
(1)
(2) (3) (4) (5) (6) (7)
(8)
(9)
(10)
(11)(12)(13)(14)
(15)
(16)
(11)
(10)
(2)
(9)
(3)EMIT1
SHUTDOWN
COMP
IN+
OSC OUTSG3524Y
COL1(12)
(4)CURR LIM+
(1)IN–
CO
L2
CU
RR
LIM
– RT
CT
GN
D
(5) (6) (7) (8)
EM
IT2
VRE
F O
UT
CC
(16) (15) (14) (13)
SG2524, SG3524, SG3524YREGULATING PULSE-WIDTH MODULATORS
SLVS077A – APRIL 1977 – REVISED AUGUST 1995
4–6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature range (unless otherwise noted) †
Supply voltage, VCC (see Notes 1 and 2) 40 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Collector output current, ICC 100 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reference output current, IO(ref) 50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Current through CT terminal –5 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Continuous total power dissipation See Dissipation Rating Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating free-air temperature range, TA: SG2524 – 25°C to 85°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SG3524 0°C to 70°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Storage temperature range, Tstg – 65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, andfunctional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is notimplied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltage values are with respect to network ground terminal.2. The reference regulator may be bypassed for operation from a fixed 5-V supply by connecting the VCC and reference output pin both
to the supply voltage. In this configuration, the maximum supply voltage is 6 V.
DISSIPATION RATING TABLE
PACKAGETA ≤ 25°C
POWER RATING DERATING FACTOR DERATE
ABOVE TA
TA = 70°C POWER RATING
TA = 85°C POWER RATING
N 1000 mW 9.2 mW/ °C 41°C 733 mW 595 mW
D 950 mW 7.6 mW/ °C 25°C 608 mW 494 mW
recommended operating conditions
SG2524 SG3524UNIT
MIN MAX MIN MAXUNIT
Supply voltage, VCC 8 40 8 40 V
Reference output current 0 50 0 50 mA
Current through CT terminal –0.03 –2 –0.03 –2 mA
Timing resistor, RT 1.8 100 1.8 100 kΩ
Timing capacitor, CT 0.001 0.1 0.001 0.1 µF
Operating free-air temperature –25 85 0 70 °C
N
n1
(xn
X)2
N
1
N
n1
(xn
X)2
N
1
SG2524, SG3524, SG3524YREGULATING PULSE-WIDTH MODULATORS
SLVS077A – APRIL 1977 – REVISED AUGUST 1995
POST OFFICE BOX 655303 DALLAS, TEXAS 75265• 4–7
elec
tric
al c
hara
cter
istic
s ov
er r
ecom
men
ded
oper
atin
g fr
ee-a
ir te
mpe
ratu
re r
ange
, VC
C =
20
V, f
= 20
kH
z (u
nles
s ot
herw
ise
note
d)
refe
renc
e se
ctio
n
PAR
AM
ET
ER
TE
ST
CO
ND
ITIO
NS
†S
G25
24S
G35
24S
G35
24Y
UN
ITPA
RA
ME
TE
RT
ES
T C
ON
DIT
ION
S†
MIN
TY
P‡
MA
XM
INT
YP
‡M
AX
MIN
TY
P‡
MA
XU
NIT
Out
put v
olta
ge4.
85
5.2
4.6
55.
45
V
Inpu
t reg
ulat
ion
VC
C =
8 V
to 4
0 V
1020
1030
10m
V
Rip
ple
reje
ctio
nf =
120
Hz
6666
66dB
Out
put r
egul
atio
nI O
= 0
mA
to 2
0 m
A20
5020
5020
mV
Out
put v
olta
ge c
hang
e w
ith te
mpe
ratu
reT A
= M
IN to
MA
X0.
3%1%
0.3%
1%
Sho
rt-c
ircui
t out
put c
urre
nt§
Vre
f = 0
100
100
100
mA
†F
or c
ondi
tions
sho
wn
as M
IN o
r M
AX
, use
the
appr
opria
te v
alue
spe
cifie
d un
der
reco
mm
ende
d op
erat
ing
cond
ition
s.‡
All
typi
cal v
alue
s, e
xcep
t for
tem
pera
ture
coe
ffici
ents
, are
at T
A =
25°
C§
Sta
ndar
d de
viat
ion
is a
mea
sure
of t
he s
tatis
tical
dis
trib
utio
n ab
out t
he m
ean
as d
eriv
ed fr
om th
e fo
rmul
a:
osci
llato
r se
ctio
n
PAR
AM
ET
ER
TE
ST
CO
ND
ITIO
NS
†S
G25
24, S
G35
24S
G35
24Y
UN
ITPA
RA
ME
TE
RT
ES
T C
ON
DIT
ION
S†
MIN
TY
P‡
MA
XM
INT
YP
‡M
AX
UN
IT
f osc
Osc
illat
or fr
eque
ncy
CT
= 0
.001
µF,
RT
= 2
kΩ
450
450
kHz
Sta
ndar
d de
viat
ion
of fr
eque
ncy§
All
valu
es o
f vol
tage
, tem
pera
ture
,re
sist
ance
, and
cap
acita
nce
cons
tant
5%5%
∆fos
cF
requ
ency
cha
nge
with
vol
tage
VC
C =
8 V
to 4
0 V,
T A =
25°
C1%
1%∆f
osc
Fre
quen
cy c
hang
e w
ith te
mpe
ratu
reT A
= M
IN to
MA
X2%
Out
put a
mpl
itude
at O
SC
OU
TT A
= 2
5°C
3.5
3.5
V
t wO
utpu
t pul
se d
urat
ion
(wid
th)
at O
SC
OU
TC
T =
0.0
1 µF
,T A
= 2
5°C
0.5
0.5
µs†
For
con
ditio
ns s
how
n as
MIN
or
MA
X, u
se th
e ap
prop
riate
val
ue s
peci
fied
unde
r re
com
men
ded
oper
atin
g co
nditi
ons.
‡A
ll ty
pica
l val
ues,
exc
ept f
or te
mpe
ratu
re c
oeffi
cien
ts, a
re a
t TA
= 2
5°C
§S
tand
ard
devi
atio
n is
a m
easu
re o
f the
sta
tistic
al d
istr
ibut
ion
abou
t the
mea
n as
der
ived
from
the
form
ula:
SG2524, SG3524, SG3524YREGULATING PULSE-WIDTH MODULATORSSLVS077A – APRIL 1977 – REVISED AUGUST 1995
4–8 POST OFFICE BOX 655303 DALLAS, TEXAS 75265•
elec
tric
al c
hara
cter
istic
s ov
er r
ecom
men
ded
oper
atin
g fr
ee-a
ir te
mpe
ratu
re r
ange
, VC
C =
20
V, f
= 20
kH
z (u
nles
s ot
herw
ise
note
d)
erro
r am
plifi
er s
ectio
n PAR
AM
ET
ER
TE
ST
CO
ND
ITIO
NS
†S
G25
24S
G35
24S
G35
24Y
UN
ITPA
RA
ME
TE
RT
ES
T C
ON
DIT
ION
S†
MIN
TY
P‡
MA
XM
INT
YP
‡M
AX
MIN
TY
P‡
MA
XU
NIT
VIO
Inpu
t offs
et v
olta
geV
IC =
2.5
V0.
55
210
2m
V
I IBIn
put b
ias
curr
ent
VIC
= 2
.5 V
210
210
2µA
Ope
n-lo
op v
olta
ge a
mpl
ifica
tion
7280
6080
80dB
VIC
RC
omm
on-m
ode
inpu
t vol
tage
ran
geT A
= 2
5°C
1.8 to 3.4
1.8 to 3.4
V
CM
MR
Com
mon
-mod
e re
ject
ion
ratio
7070
70dB
B1
Uni
ty-g
ain
band
wid
th3
33
MH
z
Out
put s
win
gT A
= 2
5°C
0.5
3.8
0.5
3.8
0.5
3.8
V
†F
or c
ondi
tions
sho
wn
as M
IN o
r M
AX
, use
the
appr
opria
te v
alue
spe
cifie
d un
der
reco
mm
ende
d op
erat
ing
cond
ition
s.‡
All
typi
cal v
alue
s, e
xcep
t for
tem
pera
ture
coe
ffici
ents
, are
at T
A =
25°
C
outp
ut s
ectio
n
PAR
AM
ET
ER
TE
ST
CO
ND
ITIO
NS
†S
G25
34, S
G35
24S
G35
24Y
UN
ITPA
RA
ME
TE
RT
ES
T C
ON
DIT
ION
S†
MIN
TY
P‡
MA
XM
INT
YP
‡M
AX
UN
IT
V(B
R)C
EC
olle
ctor
-em
itter
bre
akdo
wn
volta
ge40
V
Col
lect
or o
ff-st
ate
curr
ent
VC
E =
40
V0.
0150
0.01
µA
Vsa
tC
olle
ctor
-em
itter
sat
urat
ion
volta
geI C
= 5
0 m
A1
21
V
VO
Em
itter
out
put v
olta
geV
C =
20
V,I E
= –
250
µA17
1818
V
t rTu
rn-o
ff vo
ltage
ris
e tim
eR
C =
2 k
Ω0.
20.
2µs
t fTu
rn-o
n vo
ltage
fall
time
RC
= 2
kΩ
0.1
0.1
µs†
For
con
ditio
ns s
how
n as
MIN
or
MA
X, u
se th
e ap
prop
riate
val
ue s
peci
fied
unde
r re
com
men
ded
oper
atin
g co
nditi
ons.
‡A
ll ty
pica
l val
ues,
exc
ept f
or te
mpe
ratu
re c
oeffi
cien
ts, a
re a
t TA
= 2
5°C
com
para
tor
sect
ion
PAR
AM
ET
ER
TE
ST
CO
ND
ITIO
NS
†S
G25
34, S
G35
24S
G35
24Y
UN
ITPA
RA
ME
TE
RT
ES
T C
ON
DIT
ION
S†
MIN
TY
P‡
MA
XM
INT
YP
‡M
AX
UN
IT
Max
imum
dut
y cy
cle,
eac
h ou
tput
45%
VIT
Inpu
tthr
esho
ldvo
ltage
atC
OM
PZ
ero
duty
cyc
le1
1V
VIT
Inpu
t thr
esho
ld v
olta
ge a
t CO
MP
Max
imum
dut
y cy
cle
3.5
3.5
V
I IBIn
put b
ias
curr
ent
–1
–1
µA†
For
con
ditio
ns s
how
n as
MIN
or
MA
X, u
se th
e ap
prop
riate
val
ue s
peci
fied
unde
r re
com
men
ded
oper
atin
g co
nditi
ons.
‡A
ll ty
pica
l val
ues,
exc
ept f
or te
mpe
ratu
re c
oeffi
cien
ts, a
re a
t TA
= 2
5°C
SG2524, SG3524, SG3524YREGULATING PULSE-WIDTH MODULATORS
SLVS077A – APRIL 1977 – REVISED AUGUST 1995
POST OFFICE BOX 655303 DALLAS, TEXAS 75265• 4–9
elec
tric
al c
hara
cter
istic
s ov
er r
ecom
men
ded
oper
atin
g fr
ee-a
ir te
mpe
ratu
re r
ange
, VC
C =
20
V, f
= 20
kH
z (u
nles
s ot
herw
ise
note
d)
curr
ent l
imiti
ng s
ectio
n
PAR
AM
ET
ER
TE
ST
CO
ND
ITIO
NS
SG
2524
SG
3524
SG
3524
YU
NIT
PAR
AM
ET
ER
TE
ST
CO
ND
ITIO
NS
MIN
TY
P†
MA
XM
INT
YP
†M
AX
MIN
TY
P†
MA
XU
NIT
VI
Inpu
t vol
tage
ran
ge (
eith
er in
put)
–1 to 1
–1 to 1
V
V(S
EN
SE
)S
ense
vol
tage
at T
A =
25°
CV
(IN
+)
– V
(IN
–) ≥
50
mV,
175
200
225
175
200
225
175
200
225
mV
Tem
pera
ture
coe
ffici
ent o
f sen
se v
olta
geV
(CO
MP
) =
2 V
0.2
0.2
0.2
mV
/°C
†A
ll ty
pica
l val
ues,
exc
ept f
or te
mpe
ratu
re c
oeffi
cien
ts, a
re a
t TA
= 2
5°C
.
tota
l dev
ice
PAR
AM
ET
ER
TE
ST
CO
ND
ITIO
NS
SG
2524
, SG
3524
SG
3524
YU
NIT
PAR
AM
ET
ER
TE
ST
CO
ND
ITIO
NS
MIN
TY
P†
MA
XM
INT
YP
†M
AX
UN
IT
I st
Sta
ndby
cur
rent
VC
C =
40
V,IN
–, C
UR
R L
IM+
, CT,
GN
D, C
OM
P, E
MIT
1, E
MIT
2 g
roun
ded
IN+
at 2
V,
All
othe
r in
puts
and
out
puts
ope
n8
108
mA
†A
ll ty
pica
l val
ues,
exc
ept f
or te
mpe
ratu
re c
oeffi
cien
ts, a
re a
t TA
= 2
5°C
.
SG2524, SG3524, SG3524YREGULATING PULSE-WIDTH MODULATORS
SLVS077A – APRIL 1977 – REVISED AUGUST 1996
4–10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
0.1 µF
2 kΩ
10 kΩ
RT
1 W2 kΩ
8
4
2
1
9
6
7
10
11
14
16
3
12
13
(Open)
Outputs
VCC = 8 V to 40 V
15
SHUTDOWN
CT
RT
COMP
IN–
IN+
CURR LIM+ COL 2
COL 1
OSC OUT
REF OUT
EMIT 2
EMIT 1
GND
SG2524 or SG3524
VCC
CT
2 kΩ
1 W2 kΩ
2 kΩ10 kΩ
1 kΩ
5CURR LIM–
VREF
VREF
Figure 1. General Test Circuit
≈ 0 V
≈ VCC
VOLTAGE WAVEFORMS
90%
10%10%
90%
trtf
TEST CIRCUIT
Circuit Under Test
Output
2 kΩ
VCC
Output
Figure 2. Switching Times
SG2524, SG3524, SG3524YREGULATING PULSE-WIDTH MODULATORS
SLVS077A – APRIL 1977 – REVISED AUGUST 1996
4–11POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
1
Frequency – Hz
–10
0
10
20
30
40
50
60
70
80
90
Ope
n-Lo
op V
olta
ge A
mpl
ifica
tion
of E
rror
Am
plifi
er –
dB
10 M1 M100 k10 k1 k100
– O
scill
ator
Fre
quen
cy –
Hz
RT – Timing Resistance – k Ω
RL is resistance from COMP to ground
ÎÎÎÎÎÎÎÎRL = 300 kΩ
ÎÎÎÎÎÎÎÎ
RL = 1 MΩ
20 40 1007010742
ÎÎÎÎÎÎÎÎRL = 100 kΩ
ÎÎÎÎRL = 30 kΩ
OPEN-LOOP VOLTAGE AMPLIFICATIONOF ERROR AMPLIFIER
vsFREQUENCY
OSCILLATOR FREQUENCYvs
TIMING RESISTANCE
VCC = 20 VTA = 25°C
RL = ∞
VCC = 20 VTA = 25°C
1M
400 k
100 k
40 k
10 k
4 k
1 k
400
100
CT = 0.1 µF
CT = 0.01 µF
CT = 0.03 µF
CT = 0.003 µF
CT = 0
f osc
CT = 0.001 µF
Figure 3 Figure 4
OUTPUT DEAD TIMEvs
TIMING CAPACITANCE
1
10
4
0.001 0.01
Out
put D
ead
Tim
e –
0.004 0.10.040.1
0.4
µs
CT – Timing Capacitance – µF
Figure 5
SG2524, SG3524, SG3524YREGULATING PULSE-WIDTH MODULATORS
SLVS077A – APRIL 1977 – REVISED AUGUST 1996
4–12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PRINCIPLES OF OPERATION†
The SG2524 is a fixed-frequency pulse-width-modulation voltage-regulator control circuit. The regulator operates ata fixed frequency that is programmed by one timing resistor, RT, and one timing capacitor CT. RT establishes aconstant charging current for CT. This results in a linear voltage ramp at CT, which is fed to the comparator providinglinear control of the output pulse duration (width) by the error amplifier. The SG2524 contains an on-board 5-Vregulator that serves as a reference as well as supplying the SG2524 internal regulator control circuitry. The internalreference voltage is divided externally by a resistor ladder network to provide a reference within the common-moderange of the error amplifier as shown in Figure 6, or an external reference may be used. The output is sensed by asecond resistor divider network and the error signal is amplified. This voltage is then compared to the linear voltageramp at CT. The resulting modulated pulse out of the high-gain comparator is then steered to the appropriate outputpass transistor (Q1 or Q2) by the pulse-steering flip-flop, which is synchronously toggled by the oscillator output. Theoscillator output pulse also serves as a blanking pulse to ensure both outputs are never on simultaneously during thetransition times. The duration of the blanking pulse is controlled by the value of CT. The outputs may be applied ina push-pull configuration in which their frequency is half that of the base oscillator, or paralleled for single-endedapplications in which the frequency is equal to that of the oscillator. The output of the error amplifier shares a commoninput to the comparator with the current-limiting and shut-down circuitry and can be overridden by signals from eitherof these inputs. This common point is also available externally and may be employed to control the gain of, tocompensate the error amplifier, or to provide additional control to the regulator.
APPLICATION INFORMATION †
oscillator
The oscillator controls the frequency of the SG2524 and is programmed by RT and CT as shown in Figure 4.
f 1.30RT CT
where RT is in kΩCT is in µFf is in kHz
Practical values of CT fall between 0.001 and 0.1 µF. Practical values of RT fall between 1.8 and 100 kΩ. Thisresults in a frequency range typically from 130 Hz to 722 kHz.
blanking
The output pulse of the oscillator is used as a blanking pulse at the output. This pulse duration is controlled bythe value of CT as shown in Figure 5. If small values of CT are required, the oscillator output pulse duration maystill be maintained by applying a shunt capacitance from OSC OUT to ground.
synchronous operation
When an external clock is desired, a clock pulse of approximately 3 V can be applied directly to the oscillatoroutput terminal. The impedance to ground at this point is approximately 2 kΩ. In this configuration, RT CT mustbe selected for a clock period slightly greater than that of the external clock.
† Throughout these discussions, references to the SG2524 apply also to the SG3524.
SG2524, SG3524, SG3524YREGULATING PULSE-WIDTH MODULATORS
SLVS077A – APRIL 1977 – REVISED AUGUST 1996
4–13POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION †
synchronous operation (continued)
If two or more SG2524 regulators are to be operated synchronously, all oscillator output terminals should betied together. The oscillator programmed for the minimum clock period is the master from which all the otherSG2524s operate. In this application, the CTRT values of the slaved regulators must be set for a periodapproximately 10% longer than that of the master regulator. In addition, CT (master) = 2 CT (slave) to ensurethat the master output pulse, which occurs first, has a longer pulse duration and subsequently resets the slaveregulators.
voltage reference
The 5-V internal reference may be employed by use of an external resistor divider network to establish areference common-mode voltage range (1.8 V to 3.4 V) within the error amplifiers as shown in Figure 6, or anexternal reference may be applied directly to the error amplifier. For operation from a fixed 5-V supply, theinternal reference may be bypassed by applying the input voltage to both the VCC and VREF terminals. In thisconfiguration, however, the input voltage is limited to a maximum of 6 V.
To NegativeOutput Voltage
REF OUT
5 kΩ R1
To PositiveOutput Voltage
R25 kΩ
REF OUT
+
–
+
–
5 kΩ
5 kΩ
R2
R1
VO 2.5V R1 R2R1
VO 2.5V 1 R2R1
2.5 V 2.5 V
Figure 6. Error Amplifier Bias Circuits
error amplifier
The error amplifier is a differential-input transconductance amplifier. The output is available for dc gain controlor ac phase compensation. The compensation node (COMP) is a high-impedance node (RL = 5 MΩ). The gainof the amplifier is AV = (0.002 Ω–1)RL and can easily be reduced from a nominal 10,000 by an external shuntresistance from COMP to ground. Refer to Figure 3 for data.
compensation
COMP, as discussed above, is made available for compensation. Since most output filters introduce one or moreadditional poles at frequencies below 200 Hz, which is the pole of the uncompensated amplifier, introductionof a zero to cancel one of the output filter poles is desirable. This can best be accomplished with a series RCcircuit from COMP to ground in the range of 50 kΩ and 0.001 µF. Other frequencies can be canceled by useof the formula f ≈ 1/RC.
† Throughout these discussions, references to the SG2524 apply also to the SG3524.
SG2524, SG3524, SG3524YREGULATING PULSE-WIDTH MODULATORS
SLVS077A – APRIL 1977 – REVISED AUGUST 1996
4–14 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION †
shut-down circuitry
COMP can also be employed to introduce external control of the SG2524. Any circuit that can sink 200 µA canpull the compensation terminal to ground and thus disable the SG2524.
In addition to constant-current limiting, CURR LIM+ and CURR LIM– may also be used in transformer-coupledcircuits to sense primary current and shorten an output pulse should transformer saturation occur. CURR LIM–may also be grounded to convert CURR LIM+ into an additional shut-down terminal.
current limiting
A current-limiting sense amplifier is provided in the SG2524. The current-limiting sense amplifier exhibits athreshold of 200 mV ±25 mV and must be applied in the ground line since the voltage range of the inputs is limitedto 1 V to –1 V. Caution should be taken to ensure the –1 V limit is not exceeded by either input, otherwisedamage to the device may result.
Foldback current limiting can be provided with the network shown in Figure 7. The current-limit schematic isshown in Figure 8.
VO
RsR2
R1EMIT 2
EMIT 1
SG2524
IO(max) 1
Rs200 mV
VO R2
R1 R2
IOS 200 mV
Rs
CURR LIM+
CURR LIM–
11
14
5
4
Figure 7. Foldback Current Limiting for Shorted Output Conditions
Constant-Current Source
CURR LIM+
COMP CT
Comparator
Error Amplifier
CURR LIM–
Figure 8. Current-Limit Schematic
† Throughout these discussions, references to the SG2524 apply also to the SG3524.
SG2524, SG3524, SG3524YREGULATING PULSE-WIDTH MODULATORS
SLVS077A – APRIL 1977 – REVISED AUGUST 1996
4–15POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION †
output circuitry
The SG2524 contains two identical npn transistors, the collectors and emitters of which are uncommitted. Eachtransistor has antisaturation circuitry that limits the current through that transistor to a maximum of 100 mA forfast response.
general
There are a wide variety of output configurations possible when considering the application of the SG2524 asa voltage regulator control circuit. They can be segregated into three basic categories:
1. Capacitor-diode-coupled voltage multipliers2. Inductor-capacitor-implemented single-ended circuits3. Transformer-coupled circuits
Examples of these categories are shown in Figures 9, 10 and 11 respectively. Detailed diagrams of specificapplications are shown in Figures 12 through 15.
VIVO
VI > VO
VI
VI < VO
VO
D1
VI–VO
VI
VO
VI < VO
VI
D1
VO
VI > VO
D1
VI
–VO
| +VI | > | – VO | | +VI | < | – VO |
Figure 9. Capacitor-Diode-Coupled Figure 10. Single-Ended Inductor CircuitVoltage-Multiplier Output Stages
† Throughout these discussions, references to the SG2524 apply also to the SG3524.
SG2524, SG3524, SG3524YREGULATING PULSE-WIDTH MODULATORS
SLVS077A – APRIL 1977 – REVISED AUGUST 1996
4–16 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION †
VO
PUSH-PULL
VO
VI
FLYBACK
ÎÎÎÎ
VI
Figure 11. Transformer-Coupled Outputs
SG2524
COMP
.
CURR LIM+
EMIT 2
COL 2
COL 1
EMIT 1
GND
OSC OUT
CT
RT
REF OUT
IN+
IN–
0.01 µF
0.1 µF
5 kΩ
5 kΩ
2 kΩ
50 µF
–5 V20 mA
1N916
1N91620 µF
1N91615 kΩ
VCC = 15 V
VCC
CURR LIM–SHUTDOWN
+
1
2
16
6
7
10
3
11
12
13
14
4
5
9
8
15
5 kΩ
+
Figure 12. Capacitor-Diode Output Circuit
†Throughout these discussions, references to the SG2524 apply also to the SG3524.
SG2524, SG3524, SG3524YREGULATING PULSE-WIDTH MODULATORS
SLVS077A – APRIL 1977 – REVISED AUGUST 1996
4–17POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION †
VCC = 5 V
0.1 µF1 MΩ
300 Ω
1N916
1N916
20T200 Ω
–15 V
20 mA
15 V
50 µF
50 µF
50T
50T
TIP29A
1 Ω
1N916620 Ω
510 Ω
2N2222
4.7 µF
0.001 µF
0.02 µF
5 kΩ
2 kΩ
100 µF
5 kΩ
5 kΩ
SG2524
VCC
OSC OUT
GNDCOMP
CURR LIM+
EMIT 2
COL 2
COL 1
EMIT 1
CURR LIM–
CT
RT
REF OUT
IN+
IN–
+
+
SHUTDOWN
25 kΩ
+
+
1
2
16
6
7
10
3
11
12
13
14
4
5
9
15
8
InputReturn
Figure 13. Flyback Converter Circuit
Input Return0.1 Ω
3 kΩ1N3880
500 µF
1 A5 V
0.9 mHTIP115
SG2524
VCC
OSC OUTGND
VCC = 28 V
0.001 µF
50 kΩ
5 kΩ
3 kΩ
0.1 µF
0.02 µF
5 kΩ
CURR LIM+
EMIT 2
COL 2
COL 1
EMIT 1
SHUTDOWN
CT
RT
REF OUT
IN+
IN–
CURR LIM–
COMP
1
2
16
6
7
10
3
11
12
13
14
4
5
9
15
8
5 kΩ
5 kΩ+
Figure 14. Single-Ended LC Circuit
†Throughout these discussions, references to the SG2524 apply also to the SG3524.
SG2524, SG3524, SG3524YREGULATING PULSE-WIDTH MODULATORS
SLVS077A – APRIL 1977 – REVISED AUGUST 1996
4–18 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION †
5 kΩ
0.01 µF
0.1 µF
2 kΩ
5 kΩ
20 kΩ
1500 µF
0.1 Ω
100 µF
+
–5 A5 V
20T
20T
5T
5T
TIR101A
1 mH
TIP31A
100 Ω
100 Ω
TIP31A1W
1 kΩ
VCC = 28 V
GNDOSC OUT
VCC
SG2524
CURR LIM+
EMIT 2
COL 2
COL 1
EMIT 1
SHUTDOWN
CT
RT
REF OUT
IN+
IN–
CURR LIM–
COMP
1
2
16
6
7
10
3
11
12
13
14
4
5
9
15
8
5 kΩ
5 kΩ
0.001 µF
+
+
1W1 kΩ
Figure 15. Push-Pull Transformer-Coupled Circuit
†Throughout these discussions, references to the SG2524 apply also to the SG3524.
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