!SHUNT STATCOM BASED ON 3-LEVEL DIODE-CLAMPED CONVERTERS AND TWELVE-PHASE MAGNETICS

Xiaogang H-g B .Sc. Xi'an Jiaotong University, Xi'an, P.RaChina MSc. Xi'an Jiaotong University, Xi'an, P.R.China

A Thesis submitted to the Faculty of Graduate Studies and Research in Partial Fulfillment of the Requirements for the Degree of Master of Engineering

Department of Electricai and Cornputer Engineering Mcûili University

Montreal, Quebec, Canada August, 1999

Q Xiaogang Huang

Natid L i i Eibüathèque nationaie du Canada

Acquisitions and Acquisitions et Bibliographie SeMces senrices bibliographiques

The author bas granteci a non- L'auteur a accordé une licence non exclusive licence dowing the exciusive permettant à la National Library of Canada to Bibliothèque nationale du Canada de reproduce, loan, distribute or seil reproduire, prêter, distribuer ou copies of this thesis in microform, vendre des copies de cette thèse sous paper or electronic formats. la forme de rnicrofiche/fïim, de

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The auîhor retains ownership of the L'auteur conserve la propriété du copyright in this thesis. Neither the droit d'auteur qui protège cette thèse. thesis nor substantial extracts fiom it Ni la thèse ni des extraits substantiels may be printed or otherwise de celle-ci ne doivent être imprimés reproduced without the author's ou autrement reproduits sans son permissioa autorisation.

Dedicated to my parents and all my friends

This thesis offers a novel topology for the implemcntation of a shunt STATCOM

based on a puping of four 3-leveL diode-clamptd converters, switching at Iine

frequency and couplai to the ac system through wye/wye and wyeldelta phase-shifting

transformers.

The advantages include k t voltage controI through ihe gating pattern and the

reduced size of the dc capacitor. The dominant harmonie on the ac side is the 1 lh and on

the dc side. the 12'. The proposed STATCOM can meet Totd Harmonic Distonion

CTW)) requirements.

The operation principles of the proposed STATCOM are described. Eiarmonics

management on both ac side and dc side is explained. The concepts in this thesis have

ken proven by power system simulation software, PSCAD/EMTDC.

Ce mémoire propose une nouvelle topdogie pour réaliser un STATCOM de

type shunt. Elle est basée sur l'idée d'avoir quatres converüsseu~~ à trois niveaux

cbaque, cornmutant à la fréquence du réseau, Ils sont cwplk au système alternatif à

travers des transformahm étoile-étoiie et dtoile-triangle.

Parmi les avanîages de cette méthode, se trouvent le control direct du voltage

et la réduction de îaîk de la capacid en régime continu. Les harmoniques

dominantes sont réduites B Ia llème et la Uème sur les côtés alternatif et continu

respectivement. On n'en conclut que la méthode suggkée diminue la distortion due

aux harmoniques.

Dans ce mémoire, je développe le principe du STATCOM suggéré, la plage

du fonctionnernent ainsi que le traitement des harmoniques sur les deux côtés

alternatif et continu. iI reste a signaier le rôle important du logiciel de simulation

PSCADAMTDC pour le succès du projet.

--- II!

ACKNOWLEDGMENTS

1 wodd iike to express my sincere thanks to Dr. B.T. Ooi and DY. G. Joos, my supervisors, for theu extremely helpfui guidance, continuous encouragement and their personal fiendships throughout my study. Their dedicated endeavors on research in FACTs area are the exceptionai inspiration for m y study, rcsearch and publicatiorxs. Ako theu arrangement in my 6uancial support fiom their research gant fiom the Natural Sciences and Engineering Research Council of Canada is acknowledged.

1 would like to thank Dr. F.D. Galiana for providing the excellent cornputer facilities in Power Engineering Lab at McGill, which make the digital simdations with PSCADEMTDC and MATLAB available. Many thanks go to Professor D. McGillis for his warm fiiendstiip and professional discussion.

1 am gratefui to Dr. B. Mwinyiwiwa and Dr. A. Bakhshai who have gone back to their home countries for previously their brotherhood helps and detailed discussions. Also my Iab colleagues and ends in power lab of both McGill University and Concordia University made my time there interesting. They are Dr. Y. Chen, John Cheng, Bin Lu Xin Nie. Songtao Jia Mark Phelan, Hombeto, Xi Youhao, Mei Qiou, Haibo Zhang, Xiaotong Wang, Haibo Pan and others I rnay have rnissed.

I would like to eaend my thanks the staffs of Electical Engineering Depamnent for their unconditional helps whenever I asked for. Especially to Ms. N. de Verteuil, Ms. T. Hyland, C. Greco, Ms. M. Bergeron, Mr. C. Jorgenson and MIS. PMenon.

My special thanks go to my current colleagues at SB Telecom for their understanding and support on nnishing this thesis. EspeciaIIy thanks to ML Rouhana Rouhana for making an expert French translation of the Abstract.

And, it goes without saying, my parents for their everIasting Iove and continwus support on aii my oversea education even though they couidn't understand what is written in tbis thesis. I wodd also iike to Say that m y boyfkd, fian Hu, his love and heIp can not only be mentioned. I am indebted to a Iot of m y fiends in my home country for the expected messages fiom me but somehow interupted durhg my school time. Their h d s h i p s in my rnemory are always the kind of energy and support.

TABLE OF CONTENTS

ABSTRACT

RÉsUMÉ

ACKNOWLEDGMENTS

TABLE OF CONTENS 0

LIST OF FIGURES

LIST OF MAIN SYMBOLS

LIST OF ACRONYMS

CHAPTER 1 INTRODUCTION

1.1 Successful Implementation of Shunt STATCOM

1.2 MuItiIevel Converter and the STATCOM Topolog Proposal

1.3 Thesis Organization

CIWPTER 2 DESCRIPTION OF PROPOSED STATCOM

2.1 Shunt STATCOM Systern Configuration

3.2 Basic 3-LeveI Voltage-Source Bridge Converter

2.3 Linear Control of the Magnitudes of AC VoItages

2.3 Control of The Phase Angle of AC Voltages

2.4.1 General Compensation PrincipIe

2-47 DC Voltage

2.4.3 Qualitative Analysis of Total DC Voltage Reguiation

2.4.4 Equaiization of Capacitor VoItages and STATCOM

Operation mode

2.5 STATCOM Control Scheme

2.5.1 Quadrature Condition

2.53 Capacitor VoItage Equaiisation

2-53 AC Voltage Reguiation

i

ii

iii

iv

vii

ix

i

1

i

3

5

7

7

8

1 O

11

1 I

12

14

16

20

20

22

23

iv

TABLE OF CONTENTS v

CHAPTER 3 AC EIARMONICS MANAGEME:NT 24 3.1 Line Side Harmonies at (6m-1) and (6m+l) 24

32 PhaseShifting Transformer 25

3.2.1 Analysis of AC-Side Currents and Voltages 26

3.2.2 Converter Voltages 27

3.3 PSCAD/EMTDC Simulation Demonstration of AC Side 31

Harmonics Canceliation

CEUW3R 4 DC HARMONICS MANAGEMENT 33

4.1 Ongin of 3" Harmonies on DC Lînk Volîage 33

4.2 Elimination of 3d Harmonic on DC Liak Voitage 37

43 Elimination of 6" Harrnonic on DC Line Voltage 39

CHAPTER 5 GTO RATINGS 5.1 Introduction

5.2 Convener Current Harmonics

5.3 Convener Current RMS Value

5.4 Suggested Operation Range

CHAPTER 6 VOLTAGE TOTAL HARMONIC 46

DISTORTION AND STATCOM MVA

RATIIÿG

6. I introduction

6.2 STATCOM Open C i t e d Voltage THD

6.3 Equivaient Thevenin Circuit of The System

6.4 Shunt STATCOM Voltage THD

CBAPTER 7 CONCLUSIONS

O TABLE OF CONTENTS vi

REFERENCE 53

APPENDM A SYSTEM PARAMETERS USED FOR 56

SIMULATIONS

APPENDM B SCHEMATIC DRAFTS 57

APPENDIX C SIMULATION WAVEFORMS -.

60

LIST OF FIGURES

CEAPTER 1

Fig. 1.1: 2-Level Voltage Source Converter

Fig. 1.2: 7-Level Diode-Clampcd Voltage-Source Converter

CHAPTER 2

Fig. 2.1:

Fig. 2 2

Fig. 2.3:

Fig. 2.4:

Fig. 25:

Fig. 2.6:

Fig. 2.7:

Fig. 2.8:

Fig. 2.9:

Fig. 2.10:

Fig. 2.1 1:

Fig. 2.12:

Fig. 2.13:

Fig. 2.14:

Roposed Shunt STATCOM

3-Level Diode-Clamped Converter

3-Levei Converter Waveforms

STATCOM Voltage Magnitude - vs -V,,

Simplified Shunt STATCOM S ystem

Basic Operation of Shunt STATCOM

Eipivdent Line Voltage and AC-Side Current of Converter

Modules

Equivdent Circuit Mode1 of Shunt STATCOM

Charge and Discharge DC Capacitor (Capaciùve Mode)

Charge and Discharge DC Capacitor (Capacitive Mode,

ieading Sbifted)

Charge and Discharge DC Capacitor (Capacitive Mode,

Lagging Shifted)

Charge and Discharge DC Capacitor (inductive Mode, Leading

Shifted)

Charge and Discharge DC Capacitor (Inductive Mode, Lagging

S hified)

Converter Interna1 Control Schematic

CHAPTER 3

Fig. 3.1: Phasor Summation of Fundamental Voltages/Currents

LIST OF FIGURES viii

Fig. 32: Wyefwye and Wyddelta Connected 3-level Converter

Fig. 33: Phasor of Fundamental Converter Voltage

Fig. 3.4: Phasor of 5' Harmonics of Convener Voltage

Rg. 3.5: Phasor of 7' Harmonics of Converter Voltage

Fig. 3.6: Pbasor of 1 1" Harmonics of Converter Voltage

Fig. 3.7: STATCOM Voltage and Current on AC-Side

Fig. 3.8: Spectnun of Line Current I,h

Fig. 4.1:

Fig. 4.2:

Fig. 43:

Fig* 4.4:

Fig. 4.5:

Fig. 4.6:

Fig. 4.7:

Fig. 4.8:

Fig. 4.9:

Schematic of 3-Level Convener

3-Level Convener AC-Side Voltages/Cunents and DC-Side

Currents of Module #1

Summation of expb2trk(t-nT/3) 1, n= 1.2.3

Summation of expQ2trk(t-nT/6)], n= 12.. -6

Wyelwye connected &Phase 3-Level Converter

DC-Side Currents of Module#l and #3

Phasor of Convener AC-Side Cunent

DC-Side Currents and Voltage Waveforms

Spectnim of DC-Side Currents

CHAP'rER 5

Eg. 5.1 : Converter C m n t Harmonics

Fig. 5.2: Converter RMS C m n t

CHAPTER 6

Fig. 6.1 : Voltage THD-vs-V,

Fig- 6.2: Equivalent Thevenin Circuit of &e System

Fig. 63: Voltage - vs - Xa/ Xe

LIST OF FIGURES ix

APPENDIX C

Fig. A-1 Schematic Draft of Shunt STATCOM Power Circuit

Fig. A-2 Schematic Dtaft of Gating Signal Generator

Fig. A-3 Schematic Draft of DC Voltage Feedback Control

Fig. A-4 Schematic of UPFC Power Cmuit

Fig. A-5 Shunt STATCOM DC Voltage Regdation

Fig. A-6 STATCOM ac-side voltages and currents

Fig. A-7 DC-side Currents and Their Spectnims

Fig, A-8 Unity Power Factor Operation of UPFC

LIST OF MAIN SYMBOLS

Phase angle of AC voltage

Trigger angle in degree of a gating signal

Angular kquency of a signal

Central fiequency of PLL

dc voltage error

ka Fourier Coefficient

ac current

Power system current

STATCOM line current

Converter ac-side current

Converter dc-side current

Resistor

Reactance

Voltage

Power system voltage

STATCOM voltage

Converter voltage

dc capacitor voltage

Thevenin voltage of AC system

Puise width in degree

Transformer reactance

Thevenin reactance of AC system

LIST OF ACRONYMS

AC,=

FACïS

GTO

IEEE

MVA

UPFC

P 1

P U

P m

STATCOM

svc SSSC

THD

VCO

Alternative Curreat

Fiexile AC Transmission System

Gate Turn-Off Thyristor

Institute of Electrid and Electronic Engineers

Mega Volt Ampere

Unifïed Power Flow Conu0Ue.r

Proportional and htegral

Phase Lock Laop

Pulse Width Moduiation

S tatic Compensator

Static VAR Compensator

Static Synchroaous Series Compensator

Total Harmonic Distortion

Voltage Conrroiied OsciUator

INTRODUCTION

1.1 SUCCESSFUL LMPLEMENTATION OF SHUNT STATCOM

The two milestones in implementing shunt STATCOMs for elecuic power

transmission systems, based on the Zlevel Voltage-Source Converters (VSC), are:

(1). 280 MVAR Static Var Generator applied to 154 kV power system at Inuyama

Switching Station of Japan and has been supplying commerciaI operation since May 1991

by the Kansai Eiectric Power Co. inc. and Mitsubishi Electric Power Corporation [Il.

(7). ,100 M'VAR STATCON commissioned for the Tennessee Valley Authority at

161kV Sullivan Substation in North-Eastern Tennessee by the Westinghouse Electric

Corporation at United States in 1995 [2,3].

These STATCOMS have k e n instaiied to improve voltage regdation and to

increase transient stabity and damping. The developrnent efforts have demonsmted the

viability of the 2-level Voltage-Source Converter topology, and the mastery in applying

GTOs (gate-tum-off thyristors) for high power applications. Meanwhiie, there are other

related pubfications on the Rcsearch and Development of the same Zlevel Voltage-

Source Converters for other utility applications, such as Static Synchronous Series

Compensator (SSSC) [II] and Unified Power Flow ControIier (UPFC) [5,6], by the same

group of authors of Westinghouse, USA.

Fig. 1.1 2-level Voltage Source Converter

The two implementations of the STATCOMs. which have been referred as

milestones, are based on eight module of 2-level CrrO voltage-source converters

switching at Iine frequency. Fig.l.1 shows the schematic of one Zlevel voltage source

converter with one GTO symbol representing each switching valve unit which consists of

3 and 5 GTOs in senes. in order to meet the current and voltage harmonic distortion

standards imposed on the h e side, multiple converters feeding into interface

traasformers with specificd phase shifts are used, and low order hamionics are

eliminated. This topology ensures (a) controiiable Var injection, through dc capacitor

voltage control; (b) power sharhg between the converter moduies; and (c) improved ac

curren t and voltage wavefom quality.

12 M U L T ' V E L CONVERTER AND THE STATCOM TOPOLOGY

PROPOSAL

An alternative approach to meeting the high voltage requirernents in dismbution

voltage STATCOMs is to use mdti-IeveI converters [7-161- Arnong the topIogies

Chapter 1 Introduction 3

Fig. 1.2 7-level Diodeclamped Voltage Source Converter

investigated for potential application to power systems are the diodeclampi, multi-level

conveners [7,8].

Fig.1.2 shows the schematic of one 7-level, diode-clamped converter. Ideally any

higher voltage level cm be achieved by increrising the switch modules in each Iimb of the

three phases. By designing the tum-on and the tum-off instants of the GTOs so thar the

dc capacitor voltages, belonging to the different levels, project square wave voltages of

the appropriate widths which add up as a staircase voltage waveform. the 7-level, diode-

clamped converter produces a better approximation of the sinusoïdal voltage wavefonn

on its ac side.

The Clamping Diodes ensure that the voltage stress across eacb GTO &vice in its

OFF-state is dc voltage of the capacitor to which it is connecte& This voltage can be

designed within the Iimit of GTO device voltage rating. In the topology of Fig.l.2, since

each GTO has a maximum voltage which is the dc capacitor voltage, there is no

possibiiity of failure due to over-voltages arising h m unequal sharing of voltages when

GTûs are co~ec ted in series to increase the total voltage rating. In addition, this

topology eliminates the special concern of gating control of GTûs to ensure that the

GTûs in series have to turn-on and turn-off simdtaneously.

However, an important aspect of this topology is the requirement balance the

capacitor dc voltages of the different levels, siace there is no mechanism for the self-

equalization of these voltages. Active balancing of the dc capacitor voltages is

accomplished by using inner fetdback control loops [12].

The work on rnulti-level, shunt STATCOM [9-131 bas been foiiowed by

investigation of the same convener sinicnuies for series co~ec ted STATCOM at McGilI

University [14]. The combination of shunt and series STATCOMs allows the

implementation of more complex FACTS devices, such as the UPFC [lS].

An important feature of the multi-level, diodeclamped converters is that the dc

link voltages contain large 3& harmonies, which interfere adversely with the outer dc

voltage regulation Iwp and the inner dc voltage equalization lwps [12]. One solution is

the use of sufnciently large dc capacitors to flter out tbese haxmonics. It has been shown

that the 3d hann~nic currents of any converter can be eliminated by injecting dc currents

to the dc capacitors from a second convener fed h m a negative set of ac voltages

obtained h m transformer secondary with the oppsite polarity [13].

The dc voltages of the "&phase ac system" have a residual dc bus 6& harmonic.

The 6' harmonic can then be removed by 30" phase shifhg, obtainable by the standard

wye/wye and wyddelta, >phase transfonners. Thus a Cmodale set of multi-level diode-

clamped converters in conjunction with a 12-phase ac transformer scheme cm eliminaie

the 6 biwonics, leaving a residual 1 2 ~ harmonïc dc voltage. The capacitor sue can be

reduced by a factor of 16. In addition, the 30" phase-stiift, obtaiaed h m the wyehvye

and wyekieIta transformer arrangement, also elimifiateî the 5' and 71h hannonics on the

ac side. With a STATCOM MVA rated at a fraction of the ac transmission systern MVA,

for example 20%, the Total Hannonic Distortion m) nquiremtnts in both the voltage

and cunent couid bc satisfied by using only Zlevcl converters switching at line

frequency.

It should be noied that the wyehvye and wye/delta 3-phase transformer

arrangement to accomplish a 30" phase-shift is a standard practice in HVDC and high

p w e r rectifier systems. However, the proposed system is based on the voltage-source

topoiogy (as is [17] dso ) and not on the curent-source topology, and aithough the

harmonic cancellation principles are conceptuaily similar, they interact in the circuit in

the sense of the "circuit tbeory dual". For this reason, this thesis is written in part as a

tutonal showing that aithough there are similarities with conventionai HVDC, the

transfomers in the circuit perfonn "circuit dual" functions.

As there are aIready several pubiications on multi-level STATCOMs [9-13, 181,

and readers are already familiar with their generaI performance characieristics. This

thesis focuses on the issues of how the standards on Total Harmonie Distortions can be

W e d by using only Ilevels and how the cost of the dc Iink capacitors can be reduced.

The proposed STATCOM power circuit topology is introduced in Chapter 2. For self-

sufnciency, chapter 2 also exptains the basic operation and control of the 3-level, diode-

clamped converter. The main issues, which are harmanics management, are discussed in

Chapters 3 and 4. GTO device rating issues are discussed in Chapter 5. Chapter 6

addresses the handling of residual hamionics to s a w THD standards, and in Chapter 7,

one 6nds the hai conclusions. The materiais in Chapter Z to Chapter 6 will appear in the

publication (191 CO-authored with Dr. B.T. Ooi and Dr.G. Joos.

The virtue power sysrem simuhion s o h , PSCADEMTDC~', Version 2.0,

running on the UNlX platforni on Sun Sparcstation 10 has proved the concepts of this

proposal. in fact. a LTFC based on a combination of the shunt STATCOM and the series

STATCOM has been proven successfully, this thesis presents the shunt STATCOM aione

as a fint s e p of this research.

For the convenience of word processing, the related PSCAD simulation resula are

collected in Appendixes for reference. The graphics illusmted in the following chapters

are either represented waveforms or specmuns h m output data files of PSCADEMTDC

simdation because of the difficulties of PC for retrieving postscript file (.ps) generated

by PSCAD. or figures generated by MATTAB simulation for conceptual illustration. The

continuity of the contents is rnaintained.

DESCRIPTION OF PROPOSED STATCOM

2.1 SHUNT STATCOM SYSTEM CONFIGURATION

The proposed shunt STATCOM is shown in Fig. 2.1. The 4 basic converter

modules are coanected in paralle1 and coupled to the power system through transformer

primary windings. The tramformers are used for voltage matchhg and hannonics

cancellations. Modules #l and #3 are connected to wydwye transformer, while modules

#2 and #4 are connected to wyeklta tramformer. This wyelwye and wyefdelta

Fig2.l Roposed Shunt STATCOM

Chapter 2 Description of Roposcd STATCOM 8

arrangement implements a 30" phase-shift which eliminates the 5' and 7" harmonies on

the ac ride (SM Chapter 3) and the 6' harmonic on the dc ride (set Chapter 4). Using the

transformer dot convention, one sees that there is a 180" phase difference in the

secondary voltages between modules #1 and #3 and between moduie #S and #4. As will

be explained in Chapter 4, modules #1 and #2 form the "positive set" and their 3' dc

harmonic currents are eliminated by the injection of equal and opposite 3d harmonic

currents h m the "negative set" made up of modules #3 and #4. The notation in the

subscript i=1,2,3,4 refers to the voltages and currents of the four modules.

2 2 BASIC 3-LEVEL VOLTAGESOURCE BRIDGE CONVERTER

The circuit schematic of one 3-Ievel bridge converter module, with Ihbs A. B

and C, is dram in Fig. 2.2, With the capacitor center tap N connected through diodes,

each ac node has three voltage levels, +OS Vk, 0, and -05 Vk, the upper and lower

-

Eg22 IleveI Diode-Ciiunped Converter

Chapter 1 Description of Pcopostd STATCOM 9

Fig.2.3 Xèvel convener w v e f o m (a) gUng logic si&. (b) voltap of -4 respect to iV.(c) merhod olderermining swi tchg h a n t (d) voltage of A respect to B ( V,, = 0.77 pu)

capacitor voltages being reguiated and equalized at O.jVd, by an outer dc voItage

féedback regdation Ioop and an inner dc voltage equaiization feedback loop[E]. n i e

phase voltage at the ac temiinal A, EM, with respect to the capacitor center tap, is

detemined by the ON and O f f sates of the 4 nvitches Q4,. &, QU and QI4.

A mica1 pattern of the 4 gating Logic signais to the switches is show in Fig.

24a). Logic State I signais the turning-ON and logic O signais the tuming-ûFF. The

gating pattern is desiped to produce the quarter cycie symmetricai waveform in the ac

t e d voltage EolN shown in Fig23 (b). The path for the flow of the ac cuneng I A

ttuough the 4 switches is dehed by the same gating pattern.

2.3 LlNEAR CONTROL OF THE MAGNITUDES OF AC VOLTAGES

The pulse width "w" in Fig.2.3 (b) determines the magnitude of the fundamentai

Fourier component of the waveform. Assuming the ngulated DC voltage level, the

Fourier Series of the converter phase voltage Eu, eq(2-1). is

The switching angle 8 determines the Fourier Coefficients

STATCOM conml is designed to have a linear relationslip between the fundamental

Fourier component of the ac voltage with respect to the control signal V, as Uustrated

in Fig.2.4. V,, in Fig.2.3 (C), is the variable which controls fundamental magnitude as

shown in eq.(2-1). From eq.(2-1). the fundamental component has the coefficient

The linear relation is obtained by the scheme of producing the gating logic signais

Fig2.4 STATCOM Voltage Magnitude -vs- V ,

Chapter 2 Description of Roposcd STAT COM I l

based on the intersections between the cosine waveforms and (17:) - as Uutrated in

Fig23(c). The converter output line-line voltage is obtained by subrracting two phase

voltages. A typical h e voltage EcAs (= EcAN - E ~ N ) is show11 in Fig. 23(d). For V, = 1

pu and larger, the puIse width 'k" in Fig.3 (b) is L8û". For other values, the output is

proportional to V' of Fig2.4.

2.4 CONTROL OF TKE P M E ANGLE OF AC VOLTAGES

2.4.1 GENERAL COMPENSATION PRINCIPLE

There aùeady exist pubIicacions expiainhg system control scheme of Advanced

Static Var Compensator implemented by solid state synchronous voltage source (20-23).

The proposed Shunt STATCOM faiis in the same category as PWM type STATCOM and

foiiows the general principle of control schemt. There are both extemal control and

interna1 control functian blocks for controllhg the synchnous voltage sources operated

as a (reactive or real power) shunt compensator. To focus on tfie synchronous voltage

A B C

Fig25 Sünpiified Shunt STATCOM S y stem

Chaprer 2 Description of Roposed SïATCOM 12

Fig.2.6 Basic Operation of shunt STATCOM (a) capacitive mode, (b) inductive mode

source interna1 control scheme, some basic compensation principle will be presented in

this section.

Fig.2.5 simplifies the compensation system with the Iumped inductance X,

representing leakage inductance of couphg transformer, V, representing the equivaient

ac terminal voltage of the converters viewing h m the primary of coupiing transformers.

When the ac terminal voltage Vc is in phase with the iine voItage Vs, and when the

magnitude is greater than Vs, the STATCOM supplies reactive power, acting as

capacitive power source, Fig. 2.6(a). The voltage dV is the voltage drop across the line

reactance jXb so that the current Ic musc be Ieading Vc. This makes the converter into an

equivaient capacitor. When the magnitude of Vc is less then that of Vs, STATCOM

absorbs reactive power h m the system, having inductive reactance property, Fig.2.6 (b).

As shown in Fig.2.6 (b), the current Ic Iags Vc, so that it acts as an equivalent inductor.

24.2 DC VOLTAGE

As required by the equaiity of instantaneous real power at the ac side and the dc

side, as shown in Fig.2.5, the STATCOM has power balance equation:

V A -id +Y& -id +v& -icC =ide -var (2-2)

Chapter 1 Desnipaon of Proposed STATCOM t 3

The right-hand-side of eq(2-2) can be substituted with

and eq.(2-2) becomes

~ - Assuming the STATCOM draws a smooth Lie current 6om the ac systern, the Iine

current Id is shown as pure sinusoicial waveforrn in Fig.2.7, the instantaneous power at

the right-hand-side of eq.(l-3) wil! fluctuate because of the staircase waveforrn of the

convener voltases as depicted in Figl .7 . This will cause the ripple current injection to dc

capacitors and thus the ripple voitaee uvemdes on average capacitor voltage Vdc. The dc

capacitor is itself a harmonics filter so diat hi@ order harmonic current will be removed.

The voltage and current hamonics on both ac and dc side will be explained In details in

Chapter 3 and Chapter 4.

imaçjng there is infinite number of stairs in convener voltage and its waveform

will approach pure sine wave as the doned line curve shown in Fig.2.7. The ripple cment

Fig7.7 Equivaient Line Voltage and acSide Cumnt of Convatcr Modules (V, = 0.98 pu)

Chapter 2 Description of Roposed STATCOM 14

of il, will becorne zero. in addition when Id Ieads V,AN by 90°, the instantaneous real

power of converter from ac side to dc side WU ideally be zero. In this case, the lefi-band-

side of power balance equation eq.(2-4) becornes the surn of the balanced 3 - p h curent

and voltage production of their fundamental components. It is known that for balanced 3-

phase the instantaneous power equates to its average power. The DC voltage on ihe right-

hand-side of eq. (2-4) accordingly is the average voltage V&. When Y& equais constant,

2 the term - dY* cquals zero. ûne concludes that to ensure the reactive property of

dr

STATCOM voltage, the average value of the dc capacitor voltages should be regulated to

a desired constant level.

2 4 3 QUALITATIVE ANALYSIS OF TOTAL DC VOLTAGE REGULATION

Practically, the STATCOM converters and the coupling transfomers have losses

which include transformer copper and iron losses, switching device conduction losses and

switching Losses, (even though this item is already minimized with fundamental

switching metbod of gating 3-level converter), and dc capacitors leakage losses, etc. To

inciude the power dissipation, the STATCOM can be modeled by the simplified

schernatic of Fïg.2.8. To replenish the relatively s m d amount of power dissipation

necessary for maintaining the operation of the STATCOM, converter modules are

controlled by phase delaying the complete balanced 3-phase converter square wave

voltages by a smaü angle 6 with respect to the Thevenin Voltage representing the ac

system to which STATCOM is comected.

Chaprer 7 Description of Proposcd STATCOM 15

Fig.l.8 Equivalent Circuit Mode1 of Shunt STATCOM

The underlying goveming relation of real power exchange with respect to phase

shift angle 6 is Qiven in eq.(l-5) and eq.(l-6)

P = real(Vc - IC)

where the right-hand-side of eq.(2-5) can be deduced as

Vc (V, cos 6 - Vc) R + VcVsX, sin 6 Re d(VC . I , ) =

7 1 (2-6) R- 0 ,Y,,

in viewing of hi@ power application. the losses take a very srnail portion of MVA rating

of STATCOM, the phase angle 6 in radian is essentially very smail. Considering the

trigonometric function sin6 and c o d c m be expressed in sum of alternathg series as :

and thus sin8 = 6 and cosd= 1 when 6 approaches zero and V, rV, equation (2-6) can

be iinearized as

in such case the reai power shows monotonie increase property against phase ande B

Chapter 2 Desniption of Roposed STATCOM 16

2.4.4 EQUALIZATION OF CAPACITOR VOLTAGES AND THE STATCOM

OPERATION MODE

Previous research 112, 181 has shown that the dc voltages of the dc capacitors in

the multi-levels of the converter become unequal very quickly because there is no

inherent balancing mechanism. The asymmetric charging of the capacitors during

transients, the unequal leakage currents in the capacitors, and the parameter deviations in

the capacitors are contriiutors to the voltage unbalance. In the 3-level converter of this

thesis, there are oniy the upper level and the lower Level capacitor voltages to balance.

The purpose of this section is to ilhstrate the method of advancing or retarding the gating

signals of GQl, GQz, GQJ and Gw to equalize the capacitor voltages.

Fig2.9 Charge and discharge dc capador ( Capacitive mode) (a) ac-side voltage and currcnt (b) c m n t pulse (c) v*,

Chapter 2 Description of Proposed STATCOM 17

Figure 2.9(a) shows that under capacitive mode operation, the upper capacitor

voltage of the converter, v k ~ is precisely lagging the current by 90'. in such a condition,

the current charging the upper capacitor is shown in Fig.2.9 (b). As shown in Fig29(c),

the positive current charges the capacitor and the negative current discharges it. Since the

positive area of the current in Fig.2.9(b) is the same as the negative area, the dc voltage in

Fig.2.9(c) after increasing to a peak r e m to its initial voltage. Fig.2.10 and Fig.2.11

show the same set of cunent and voltage wavefonns but for tbe case when the conduction

windows are phase shifted by incremental lead and lag with respect to Fig.2.9. Note that

the phase-shifted voltages are shown in bdd lines. Obviously the leading shifted

converter voltage will drive the voltage of the capador above its initial level and thus

individual capacitor voltage incnases as shown in Fig.2.l0(c). In the lagging condition.

when the convener voltage is phase shifted to lag the Line current incrementally, the dc

voltage will decrease, as shown in Fig.2.l l(c).

By contrast, when converter operates in the inductive mode, the effect of phase

shifting the conduction window on the dc voltages is just the opposite of the capacitive

mode operation, This is demonstratecl in Fig.2.12 and Fig.2.13.

The above iliustrations explain the reason why the "Var Sign" will be applied in

the individual capacitor voltage replation of the convol scheme descriid in the next

section.

Chapter 2 Desctiption of Roposcd STATCOM 18

Fig.2.10 Charge and discharge dc capacitor (Capacitive mode, leading shifted) - (a) ac-side volta& and &nt (b) a k n t pulse (c) vk,

-

I I 1

Fig.2.11 Ch- and discharge dc capacitor ( Capacitive mode. lagging shifted) fa) ac-side voIiage and current (b) m n t pulse (c) vkl

Chaptcr 2 Description of Roposed STATCOM 19

............................................... (cl

Fig.2.12 Charge and discharge dc wpacitor (inductive mode, leading shifted) (a) ac-side voltage wd current (b) current puIse (c) vk,

Fig.2- 13 Charge and discharge dc wpacitor (inductive d e , lagging shifted) (a) ac-side voltage and curent (b) current pulse (c) vk1

2.5 STATCOM CONTROL SCXEME

Fig.2.14 shows the schematic of the STATCOM Controls. Three feanues are

controiied by negative feedback: (1) the quadrature condition between voltage and

current, (2) the equalization of the upper and lower dc voltages, (3) the ac voltage

magnitude.

2.5.1 QUADRATURE CONDITION

Referring to fig.2.1, the quadrature condition is acbieved by phase-shifüng the

converter voltages E o t ~ with respect to the voltages, VM at its connection to the

transmission line. When the line currents Id are perpendicular to the voltages EeANI the

real ac power of the converters are zero so that the dc capacitors are neither charged nor

3-level Conveners

4

I Cosine Funcrion Look-UD Table 1 I

Fig.î.14 Convener Interna1 Conml Schernatic

Chaptcr 2 Dcsniption of Ropsal STATCOM 2 1

discharged This quadranire ptoperty is obtained by ushg the wter feedback hop of Fig.

2.14. in the outer feedback, Vk, the dc voltage across both the capacitors, is measured

aud compared with the reference, V k ~ . The error, mk, is applied to control S, the

voltage angIe of Eu. In changiag 6, the amount of rcal power admitted into the

converters are changed according to eq.(26). When the negative feedback of the outer

lwp nulls the emr, the quadrature coadiuon, when the iine currents Id are perpendicular

to the voltages Eu, has been teached,

The outer fedback loop of Fig3.14 bas a Phase iock h p (PU) which

synchronizes the frequency of the converter voltages to the utility frequency. In the hem

of the PLL is the Voltage Controiied Oscillator (VCO), wbich outputs pulses at a rate

which is proportional to its input. Its input is K ~ ( f 2 ~ - K3wk), where Kt and K3 are gain

constants, is a central frequency adjustment and && is the dc voltage error.

The puises ftom the VCO are counted in a binary COUNTER. The output of the

COUNTER is added io the binary rneasurement of KI&&. Their digital sum is recorded

in the Lower Address Register and the Upper Address Register. These Registers point to

tbe Addresses of Look-Up Tables which contain cosine functions in their mernories. As

the VCO keeps counting, the sequentid addressing of the Look-Up Tables produces the

cosine wavefonns shown in Fig. 2 3 (c). The intersections of the cosine waveforms with

Y, determine the instants of gating signais of Fig. 2 3 (a). In Fig. 2.14, the Block

containing "Gating Pulse Generators" switch the devices of Fig. 2 2 ON and OFF, and

the voltage pulses in nini determine the magnitude and phase angle of the converter

voltages Ed.

The input K2& to the VCO is n o d y set so that the converters produce

voltages at 50Hz or 60 Hz of the standards. The outer feedback loop e m r mk has the

effect of changing the phase angle directly through Ki-, and the fiequency through

K2K3m,. As angle is the t h e integrai of frequency, one c m look on KI as the

Proportional Gain and K2K3 as the Integral Gain.

2.5.2 CAPACITOR VOLTAGE EQUALIZATION

When the outer feedback loop e m r && is nuIIed, the voltage across both

capacitors of Fig. 2-14 wiii be V&=V&,+ However, there is nothing to guarantee that

each of the capacitors will have a voltage equai to 0.5 VkDF For this teason, there is an

inner feedback loop for the Upper Capacitor. As iiiustrated in Fig. 2.14, the voltage of the

Upper Capacitor, VkI, is measured and compared with the b e r Loop Reference

0.5V' The error, after passing through a PI Block containhg Proportionai and

Integrai Gain constants, is converted to an incremental binary number whicti is added to

the contents aiready in the Upper Addtess Register. The incremental binary number

effectively shifts the conduction windows to the positions assumai by the bold lines of

Fig.2.10 to Fig. 13. Depending on the polarity sign of the e m r and depending on the "Var

Sign", the negative feedback incrementaiiy charges or discharges the Upper Capacitor

until the error is nuiied, whereupon V&l=Vu

Chapter 2 Description of Roposcô STATCOM 23

2.53 AC VOLTAGE REGULATION

For the reactance condition determined by the Outer Feedback Loop discussed in

Section 2.5.1, the magnitude of the ac voltage is determined by V,, in Fig.23 (c). As

üiustrated in Fig.2.14, the AC Voltage Regdation h p begins with the reference VCJr~

The magnitude of the lùie voltage is measured and compared with the reference. The

error after passiag through a PI Block, containhg Proportional and Integrai Gain

constants, is applied to the V , control in Fig.23 (c). As V, increasa for example, its

intersection with the cosine function produces a broder voltage pulse width "w" for EN

in Fig. 2.3(b), effectively increasing the converter voltage.

AC HARMOMCS MANAGEMENT

3.1 LINE SIDE BARMONICS AT (drn-1) AND (6m+I)

The voltage wavefonns do not contain even nor ûiplens hannonics because of the

quater-wave symmetry of Fig. 2.3(b) and because the transformer secondaries are in

open-wye and delta. The residual hvmonio are the 5'. 77 11: 13'. .... 6m-1 and

6m+ 1 ... Since the single degree of &dom in designing the switching instants has been

devoted to the magnitude control of Fig.2.4, the 3-level converter has no capability to

elirninate any of the residual harmonies.

Fig. 3.1 Phasor summation of fundamental voItagcs / cumnts

In pnnciple, some of the residuai hannonics can be eliminated by combining

several 3-leveI converter modules with identicai waveforms which are properly phase-

shifted, so that they build up a stairase wavefom which approximates the sinusoidai

waveform more closely. In practice. he objection is that their totai MVA becomes

Chapter 3 AC Harmoaics Management 25

harmonic component of either the voltage or the current (as üiustrated in Fig. 3,l(b)) to

be las than their arithmetic sum (which is their coliinear resuitant as üiustrated in Fig.

3.1(a)).

Phase-shifting transformers can recover the otherwise lost MVA. When the

phase-shifting transfonners play the additionai role of stcpping-up the ac voltages of the

conveners to match the transmission line voltages, ihey are not added cost items. Unlie

complex phase-shifüng which requires custom designed transformers with tertiary

windings, the wye/wye and wyeidelta connection of 3-phase transfomers as shwon in

Fig.3.2, which accomplish a 30" phase-shift, are based on standard winding transfomea.

(They ody ~ q u k the weU-known &N :Itums-ntio in the wyeiwye conneciion and

N : 1 ratio in the wye/delta connection) Although a total of 12 single-phase transfomers

are required, the large number does not represeat any serious cost increment since their

cost is detennined mainly by their totd M'VA. The cost could be low if the transformer

can be found in the standard stock of ihe manufactures.

The two tasks of: (1) presenring the atithmetic sum of the MVA of the individual

converters, while (2) elimiaating the 5' and the 7' harmonies will be analyzed and

demonstrateci by simulating the shunt STATCOM of Fig, 2-1 using the PSCAD/EMTDC

P*iW=-

Chapw 3 AC Harmonies Management 26

3.2.1 ANALYSES OF AC SIDE CURRENTS AM, VOLTAGES

The wydwye imd wyetdelta comected 3-level converters enabk the 5' and 7'

harmonics to be cancelled on the ac side. The connections of the transfonuers to

converter #1 and #2 are depicted in Fig.3.2. Being shunt comected to power system, the

ac side current harmonics of the STATCOM are of more interest. Assuming balanced

impedance of each phase of the h e and equal impedance in the wye/wye and wyddelta

transfomer, the A-phase phase line-side current I1u and Ilu and voltage are d e s c r i i as

eq (3-la) for hindamentai component and as eq (3-lb) for na harmonies.

where ml) and Wr(n) refer to the transformer impedance, which is mainiy leakage

inducuve reactance, at fundamental frequency and n" harmonic Eiequency respectively,

A B C

Fig.32 wyelwye and wyddelta connecteci 3-level convexïer

Chapter 3 AC Harrnonics Management 27

wherc VcA is A-phase converter voltage after transformation to the primary side. The

notation of 1 and n in bracket refer to harmonics order. For the wye/wye transformer

connection, the primary side phase voitage V d is proportional to and in phase with

secondary side phase voltage EM- For the wyeldelta transformer comection, the

primary side phase voltage Va is proportional to and in phase with secondary side line

voltage Em. Considering the piimaiy to secondary tums ntio to be &N : 1 and N : 1

for wye/wye and wyefdelta C O M ~ C ~ ~ transformer respectively, the above relations can

be described as eq.(3-2a) and (3-2b)

vdl (Pt) = fi%&w (dl (3-2a)

Vu12(aIl) = N E a 2 ( @ ) (3-2b)

Clearly the curent harmonics can be caiculated only by studying converter

voltages harmonics, including both magainide and phase.

3 3 3 CONVERTER VOLTAGES

As described in Section 2.2, the gating signals to the GTO switches in the 3-Ievel

converter #1 and #2 are of identical panem, but phase shifted by 30'. Consequently, the

converter phase voltages are also identical and phase shift by 30". The Fourier Series of

the transformer secondary A-phase voltages are expressed in eq.(3-3a) and (3-3b).

*ter 3 AC Harmonies Management 28

To further analyze line voltage E- of converter #2 , eq(3-3b) c m be simplified as :

The term inside the b e r bracket of the right-hand-side tenu of eq.(3-3b') has different

values with respect to harmonics order k. They are

.Ln .5kn -1 - - 1 6

e 6 -e =fi when k=l.l1,13.23.25. ....12m*l(m=0,1,22.2) (3-4a)

=-& whenk=5,7.17.19 ...12m+5(m=0,1,222.)(3-4b)

These explain that by substituting eq.(3-3b') to eq.(3-2), the primary side converter

voltages become

" rh which describe tbat the phases of the 5 , 7 , 17., 195 ... harmonics of converter voltage

#l and #2 is 180 O apart, however the fiindamental and the 1 1", 13', 23d,

25". . . hmonics are in phase.

Fig.3.3. Fig.3A Fig.3.5 and Fig.3.6 show the phasors of fundamentai, 5" .7" and

1 1" harmonies voltages ~spectively. These components of converter #l and #2 are of the

same magnitude ideaiiy. When substituting eq.(3-5a) and (3-Sb) into he-side current

equations eq.(3-la) and (3-lb), one sees that ac si& current I,u and Ia have the same

Chapter 3 AC Harmonies Management 29

phase relationship as STATCOM voltage Va and V'- The total positive set shunt

th th STATCOM ac side -nt I,u + IIm will have 5 , 7 , 17'. 19" . . . harmonics cancelled,

wbik fundamental components will have addition without causing de-rating.

Ftg3.3 Phasor of fundamental converter voltage (a) of convener #l,(b) of converter #2

Fig3.4 Phasor of 5" harmonics of converter voltage (a) of converter #l,(b) of converter #2

Chapttr 3 AC i-iimwnics Management 30

Fig.35 Phasor of 7" hannonics of convem voltage (a) of converter # 1 . 0 of converter #2

Fig.3.6 Phasor of 1 I& harrnonics converter voItage (a) of converter #l,(b) of converter #2

33 PSC- SIMULATION DEMONTRATION OF AC SIDE EIARMONICS CGNCELLATION

By sirnulating the shunt STATCOM of Fig.2.1 using PSCAD- program,

the underlying principles will be pcesented in a graphical form in Fig.3.7. The Iabels of

the voltages and currents are shown in Fig. 2.1.

As the starting point, Fig3.7 (a) sbows the lint voltage V d on the transformer

primary side. The correspondhg open-circuit, secondary- side voltages VcMl and Vm

in Fig. 3.7(b) show the 30' phase-shift accomplished by the wydwye and wyeldelta

transformer connections.

On the secondary side of the transformers, the converters of modules Y1 and #2

are designed to switch with a 30' phase-shift between them and the feedback control of

Fig. 2.14 aligns the phase angles of k i r h e voltages E-1 and Em as shown in

Fig.3.7(c) with hose in Fig. 3.7(b). Since the matched impedance between the voltages

of Fig. 3.7(b) and 3.7(c) consist mainly of the balanced transformer Ieakage nactaace,

the converter currents lcAl and IcU are also baianced and they also have the s m e 30"

phase-shift, as the simulation resdts in Fig.3.7(d) show.

On the transformer pRmary side, the converter currents are f , ~ and I,u shown in

FÏg. 3.7(e). The opencircuited, prirnary-side converter Iuie voltages correspondhg to

Edl and EcAW are Vu and V- s h in Fig3.7 (f). On the pnm;trY side, the

wyelwye and wyddelta transfomer connections have aligned the voltages and the

currents, which on the secondary si& are 30' a p a

Chapter 3 AC Harmonies Management 32

(s)

0i)

(9

O 0.005 0.01 0.015 0.02 0.025 0.03

Time (s)

Fig- 3.7 STATCOM current and voltage on ac-si&

Chapter 3 AC Harmonies Management 33

Fig. 3.7 (g), @) and (i) show the fundamental. the P and 7' harmonic

components of the primary side currents IsM and Ism . AS the fundamental components

of Fig.3.7(g) overlap, we have deiiberaiely dispiaced them slightly to remind readers that

there are two components which are in phase. Fig. 3.7(h) and (i) show that the and 7'

harmonics of the two branch cunents I,u and Im are 180° apart,

The bmch currents h m converters #1 aad #2 merge to fonn the total ihe

current as show in Fig,3.7(a). From Fig.3.7B) and (i), the 180" phase shifts mean that

the and 7' hannonics are self-cancebg. The frequency spectnim of Id =Ihl +lJM in

Fig. 3.8 shows that the residual harmonics are the Ilh and 13".

Fig.3.8 Specuum of line current Z,h

Seen from the primary-side of the transfonuers, the converters #1 and #2 appear

as two nearly in-phase fundamental voltage-sources which are connected in paraiiel.

Since their fundamental harmonic currents are in phase, they add in the arithmetic sense

of Fig3.1(a), without i n c h g the degradation in magnitude, as illustrated in Fig3.2@).

Thus the MVAs of the individuai converters are preservd

DC HARMONICS MANAGEMENT

4.1 ORIGIN OF 3d BARMOMCS ON DC LINK VOLTAGE

For convenience, the schematic of the 3-level converter is re-drawn below in Ftg.

4.1. The voltages and currents of A, B and C phase of converter #1 are iiiustrated in

Fig.4.2 (a), (b) and (c) respectively. For simplicity. only ifie fundamental components of

the converter currents are shown. in each phase, the cunent is injected to the upper dc bus

oniy at the window p e n d of the conduction of the GTOs. This window coffesponds to

the times of the positive voItage level, Le. + V , in Fig. 4.2, The ac current is admitted

through the A-phase when QJ conducts. The waveforms of pulsed current from each lirnb

are labeled in Fig.4.1 as IA1, IBJ and Ici. There are 3 identical current pulses h m each of

the 3 phases, which have a 120° phase delay between them.

fig.4-l Scbematic of EIeveI Converter

C h p m 4 DC Harmonies Management 35

Fig.4.2 Elevel converter ac side voltages/current and dc side currents of Module #l

Under the gating pattem of Fig.2.3 (a), the upper GTO switches, QI and Qz admit

ac c m n t I d through the upper haif of the bridge to charge the upper dc Iink capacitor

during one half cycle and through the GTO @ and Q d at the lower half of the bridge, to

charge the lower dc link capacitor during the second half cycle. In one cycle of the ac

supply. the dc bus current injection to one haif of the bridge is repeated 3 times, once

fiom each phase of the Iphase converter- Thus the im (up) has the pattern as shown in

Chaptcr 4 DC Harmonies Management 36

Fig.4.2 (g). It consists of the current waveforms of Fig.42 (d), (e) and (f). Fig.42 (h)

shows the waveform of ikl (iow).

The quantitative anaiysis of the dc bus current appiies for ik, (up) ody. However,

the conclusion aiso works for lower dc link current, ikl (iow).

Since the phase currents are identicai except for TB tirne delays T 2T

idcl (up) = iAl (1) + iAI (t --) + iA1 (t --) 3 3

Generally, any periodicai waveform can be written in Fourier Series as:

L J

where the Di is the complex Fourier Coefficient of the k' harmonic.

T i e shiit by TB of periodicai waveform corresponds to phase shift by 2d3 for

fundamental component. For each of the k' harmonic of the Fourier Series in eq.(4-7).

= 3 d k d when k=3m for m=I .2 ,R. . (Ua)

= O when kdrn /or m=I.2.3. ..(44b)

t where ant = 2x-. In other word, the phasors of the 3& hamionic a d ail tripIens become

T

aligned as ïiiustrated in Fig.43 (b). The remaining phasors wili be baianceci 3-phase in

Fig.4.3 Summation of exp[j2nk(t-nT/3)], n = l U . (a) k c 3m, Cb) k = 3m m = 12 -..

360" as shown in fig.43 (a). Th& s d o n Ieads to cancellation.

Since the dc capacitor voltage is the tirne integrai of the injection current of eq.

(4-2), one can conclude thaî the dc bus voltage of 3-level converter will have 3"' and

triplen harmonics.

1 v&dt) = - C f J ' , i l ( t ~ (4-5)

This analysis applies to the dc voltage of the lower capacitor Vk3.

4.2 JCLIMINATION OF 3d HARMONIC EN DC LINK VOLTAGES

It is found that the upper dc bus c m n t consists of injected pulses from a Gphase

ac system. The summation of the 6 identical pulses. each of which is phase shifted by

Tl6, is:

Similar to the anaiysis in section 4.1. the Fourier Series of the above periodic waveform

makes the summation of terni exp~2xk(t-nT/6)] (n=I,2,..6) which are shown in phasor

diagram Figd.S(a) when k # 6m and F1g.45 (b) w k n k = 6m for m=1 ,2,3... The

summation of the Fourier Series t e m yields zero when k # 6m and 6& when k = 6m.

rd th The lowest order harmonic remabhg is 6. The 3 .9 , 1 5 ~ . . . harmonics are canceiied.

Fig.4.4 Smnmation of exp[j2nk(t-nT/6)1, n= LA. . .6 (a) k t 61x1, (b) k = 61x1, m = 1.2 . . .

Chaptcr 4 DC Hannonia Management 38

A B C

Fig.45 wydwye connected 6-phase 3- levei convencr

The principle can be applied to the STATCOM for hannonics canceiîation by

using two identicai 3-level converters both connected to the same dc buses as illustrated

in Fig.4.5, which forms a member of the "negative set". Fig.4.5 is extracted from Fig.2.1.

The ac power is derived h m 2 identicai sets of 3-phase transformers. The phase of the

"negative set" is 180' apart h m the ''positive set9*, which is obtained by reversing the

polarity connections of the transfomer secondary. In Fig. 45, module #3 is the negative

set of the wye/wye mochile #1. Note the reversal of the position of the dot in the

secondary, using the dot convention. For cornparison, the operation of converter #3 is

iiiustrated by showing the wavefom in Fig.4.6.

Fig. 4.6 (c) shows the elimination of the 3d harmonic m the combineci outputs

(&icW) of the positive Fig.4.6 (a) and the negative set Fig. 4.6 (b). The elimination of

the 3d, 91h, 15' ... harmonics Ieave behind the 6& harmonic and the harmonies which are

integral multiples of 6.

Fig.4.6 DC-side Currents of Module #1 and #3

In Fig.2.1, module #4 is the negative set of module #2, for the modules connected

&y the wyddelta transformer. The combined output of i& is devoid of the 3"

harmonies aiso.

4 3 ELIMINATION OF 6" BARMOMC IN DC LiNK VOLTAGES

By combining the 30" shifted outputs of the wyetwye and wyeldelta transformer

p u p s of positive and negative sets, a lZphase, 3-level converter systern is obtained.

Fig.4.7 phasor of converter ac-side cunent (a) nnit#l, (b) unit#l& 3. (c) unit M.2.3, & 4

Chapm 4 DC Harmonies Management 40

Time (s)

Fig.4.8 dc-side currents and voltage waveforms

Fig. 4.7(c) shows the phasors of the 12-phase system. Fig.4.7 (a) and (b) show the

pbasors of unit #1 and the combination of unit #1 and #3. Fig.4.7(c) shows the phasors of

units WL and #4 interposed between the phasors of Fig.4.7 (b). Fig.4.8 summ&es the

management of the dc side harmonies. The currents originate on the ac side and Fig.4.8

(a) shows a typicai phase current. Fig.4.8 (b) shows the dc-side current for converter #1.

Essentiaily it consists of the summation of 3 current pulses, one h m each phase.

Fig.4.8(c) shows the elimination of the large 3d hannonic by having a ncgative converter

#3 but large 6* harrnonic rernains. Tbe 6' barmonic is eliminated by have a 30' phase

Cbapm 4 DC Harmonies Management 41

I L ' I I 8 r - 8 r

8 8

Fig.4.9 Spectmm of dc-side currcnts: (a) ikl, (b) ikI+iM, (c) ikl+iM+iM+iw

shift from the wye/wye and wyddelta transformer arrangement. Fig.4.8 (d) shows the dc

current h m converten #1. #2, #3 and #4 in which the large 6' harmonie in Fig.4.8(c) is

eliminated leaving a large residuai 12" harmonie. Their hquency specuums are shown

in Fig.4.9. The frequency spectnun of Eig.4.9 (c) shows residuai harmonies which are

numbered in integral multiples of 12.The size of the dc capacitor needed to filter out the

12" hannonic current ripple is reduced Fig.4.8 (d) shows the dc Linlr capacitor voltage

ripple with the 12' hmonic present

CHAPTER 5

GTO RATING

5.1 INTRODUCTION

FoIiowing the explanaiion in Chapter 4, although current harmonics are cancded

on the power system side, the converters sri11 have to cope with rheir presence. The 3-

level voltage waveform of converter will be the source of harmonic currents, which eiher

flow to the power system, or are canceiied. The canceiied harmonics circulate between

phases of the converters, In each 3-level converter unit, the GTO devices are of unequa1

current rating due to the different conduction duty at each cycle. The utter GTOs QJ and

Q, conduct ody when the phase voltage is + V d 8 and -V& respectively. However, the

inner GTOs, @ and a, conduct for the whole half cycle. The ciifference wiiI be directiy

determined by conduction pulse width w as defiaed in Fig.23. If the converter designer

chooses the rating of the GTO according to the duty of inaer ones, the outer device wiIi

be oversized. As the savings made in not oversizing the outer GTOs do not compensate

for the savings in using identical GTOs throughout, the remainder of this section wiU

assume that ail GTOs wiil be rated the same. An important factor in deciding to use

identicai GTOs is the necessity to stock spares in the event of funire failures. It is more

expensive to stock spares for different categories of GTOs.

The rating of the GTO is determined by heating los. The heating loss cornes from

the conduction voltage multipiied by the conduction cunent

Since the conduction voltage is constant, the variable factor is the conduction

current which is a function of the angle 8= (180"-w)/2.

Fig. 5.1 shows the fundamental, the 5' and the 7 " hmonic plotted against the

angle 0 = (180-w)/2, where 8 and w are defined in Fig.2.3(c). The plotted points in

Fig.5.1 are taken h m EMTDCPSCAD simulations. For example taking X , = 0.1 pu, for

w = 180" or 8 = 0.0". the 5" and 7' harmonies can be as high as 40% and 20% of the

fundamental. Table 5.1 lists the measud parameters h m EMTDCPSCAD simulations.

The peak currents are listed as data for the selecuon of CXO size. The System rating used

in simulation can be found in Appendix A.

Chapter 5 GTO Rating 44

53 CONVERTER CURRENT RMS VALUE

The RMS value of conduction current is the variable for selecting the GTO rating.

Knowing that harmonics cunent present are only of 6&I, m=l,23 ... the nominal RMS

values are caiculated and ploned together with the fundamentai current as the line curve

in Fig.5.2 The RMS values taken h m the simulation results are plotted as points. The

RMS values are the same as those in TabIe 5.1.

1 I I

DC Harmonie Analysis on Con

5.4 SUGGESTED OPERATlON RANGE

From Fig.5.1, one sees that 5" harmonics magnitude is minimum when 19 =18".

The RMS current curve has the ciosest point at 8 =lao to the fundamentai current cuve

Chaprer 5 GTO Rating 45

e (degree)

Eig5.2 Convener RMS current

in Fig.5.2. in order to reduce the undesirably Iarge hannonic cunents and not to over-size

the GTOs, Bis restricted to the range, h m 18 O to 38.9'.

Reducing 8 fiom O" to 18" rnem a de-wing of the MVA by 4.8%

i=( cos O" - cos 18"

x 100 ). At 8=18.0°, 30.1 O and 38.9". the converter output voltages COS 0°

are chosen to be 1.1 pu, 1 .O pu and 0.9 pu respectively. The GTOs are rated at 1.0 pu

capacitive current when 8= 18", at which the 5" and 7' barmonic currents are 0.0% and

11% respectively. The selection of GTO rathg is based at 8 = 18", when the RMS

current is 1.006 pu. As the STATCOM decreases fiom 1 .O to 0.0 pu capacitive current,

the 5& hannonic increases and the 7' bannonic varies, but the RMS cunents remain

within the safe limit of the chosen GTOs.

VOLTAGE TOTAL HARMONIC DISTORTION AND STATCOM MVA RATING

In this chapter, the objective is to show that the THD standards cm be met when

the MVA of the STATCOM is small compared to the MVA of the system to whicb it is

connected. It is obvious tbat current THD is the easier standard to satisfy. When the

current injecteci by the STATCOM is only 20% of the line current, for example, the

current THD of the STATCOM becomes lowered by one fifth, when considering the

current harmonies in the total line current. The focus is placed here on the voltage THD.

The quantitative measurement of voltage THD will be presented in Theveinin equivaient

circuit models.

6 . 1 STATCOM OPEN CIRCUITED VOLTAGE THD

Fig.6.I shows the voltage THD of the open circuited voltage of the STATCOM

pIotted as a function of the magnitude controt V,. In the control magnitude range from

V- 0.6pu to I.Opu, the voltage THD does not exceed 0 . 1 6 ~ ~ . The objective is to show

that the voltage THD at the terminais can decrease below the 0 . 0 5 ~ ~ and Iess, tequired by

the standards. The THD calculation follows tk f o d a as foiiows:

Cbapter 6 Voltage Total Hannonic Distortion And STATCOM MVA Rating 47

where Vk is the RMS magnitude of k' harmonic and Yi is RMS magnitude of

fundamental component. The harmonies magnitude cornes from the Fast Fourier

Transfocm of the line-to-line voltage waveform measured in EMTDUPSCAD

simulation. The open circuit operation was simulated by series connecihg a I M R resistor

between primary winding of transformer and neutral ground.

Fig. 6.1 Voltage THD-vs-Vnrog

6.3 EQUIVALENT THEVENIN CIRCUIT OF THE SYSTEM

The shunt STATCOM and extemal power systems are rnodeIed in equivalent

Thevenin circuit shown in Fig.62. The shunt STATCOM is represented by an ided

voltage source Ed behind the reactance jk& . where k is the harmonic number, Ed is the

Cbaplcr 6 Voltage Total Harmowc Ditortion And nATC0M MVA Rating 48

kP' harm~nic c~mponent of the converter voltage wavefomi and X, is the transformer

leaicage reactance. The external power system is represented by the Thevenin Voltage V ,

(which exists ody for k = 1 only, as VI = 0.0 otherwise) in seties with reactance jHrh ,

where Xi* is the Thevenin Reactance. in the single-üne diagrarns, Fîg.6.2 (a) is for the

fundamentai kquency and (b) for the hannonic.

6.4 SEIUNT STATCOM VOLTAGE THD

Sbunt STATCOM voltage THD is computed from Vc at the output terminals of

the STATCOM. From Fig. 6.2 (b), the voltage divider effect has the result that the total

mot-mean-square of the voltage harmonies at the terminais is decreased by the factor Xh

.4 X, + X, 1, eq46-3)

Chaptcr 6 Voltage Total Harmonic Distomon And STATCOM MVA Rating 49

The fundamental hannonic voltage does not decrease because that it is in part supported

by the Thevenin Voltage VI in Fig. 6.2 (a), eq.(6-2).

To simpl3y the computation of the voltage THD, it is assumed the fundamental

voltage at the output terminal, which the denominator of the THD definition, is the same

Ecl . Vcl " Ecl

so that there is no mgnitude decrement by the voltage divider.

Fig. 6.3 displays the voltage THD* (the symbol * king the reminder of the definition in

which Ecl is used in the denominator of eq. (6-1)) as a fwiction of the ratio Xh /Xi , , for

the case V,, = 0.8 pu. From Fig.6.1, one sees that the voltage THD does not Vary much

in the V' range h m 0.6 to 1.0 pu. Conceivably, the designer can choose Y, = 0.8 pu

to be cross-over magnitude from capacitive to inductive reactance operation, with a

control range of 0.2 pu. From Fig.6.3. 2% voltage THD is obtainable for Xh / Xw ratio

of about 02. For STATCON whose MVA rating is l e s than 20% of that of the

compensated transmission line, the Xh / Xe ratio is less than 0.2

CONCLUSIONS

This thesis has presented a novel shunt STATCOM based on fout modules of 3-

level, diode-clarnped converters coupled to the ac system through wyeiwye and wyddelta

transfomers.

The STATCOM of this proposal lus the same minimum switching loss as the 2-

level STATCOMs of [l, 21, so tbat cornparisons with them are meaningful. The cost

advantages corne from the use of conventional 2-winding tramformers to accomplish a

30" phase-shift, instead of custom desigaed transfomers with tertiaries to accomplish

phase shifting of more compIicated angles. Only one magnetic stage is necessary, as the

wye/wye and wyetdelta transfonners serve the duai functions of voltage matching and

hannonic elirnination. In contrast, tbe STATCOMs of [l, 21 require one stage of interface

magnetic for hamonic elimination foiiowed by a second stage for voltage matching.

Performance advantages corne from the fast ac voltage magnitude controiiabiiity

from the GTO switching in the 3-ievel converters (in contrast to dc capacitor charging in

[1,2]). Actuaiiy, the faster response is ody a marginaI gain in the STATCOM. However,

the related research work in reaiizing the UPFC using two STATCOMs, see schematics

in Appendix, shows that as ac voltage magnitude control is not dependent on the charging

of the dc iink capacitor voltage, each of the two STATCOMs has independent freedom of

magnitude and phase ande control. Thus, the UPFC based on the STATCOMs of this

thesis can operate with its W1 3 independent convol degrees of &dom-

Chaptcr 7 Conclusion SI

No less an advantage in the design of Fig. 2.1, is the fact that it serves as a

building block for a f a d y of FACï'S controllers. In this thesis, it has been presented as a

shunt STATCOM. The series STATCOM and the UPFC can be realized by rearranging

the connections of the building block(s). FACTS controllers can gain faster acceptabiiity

when they are seen to belong a famiIy, so that their mode of operation and their familial

characteristics can be understood together more easily.

in comparing the STATCOM of this thesis with all other muiti-level STATCOM

designs, the advantage cornes from the much d e r dc iink capacitor size. The srnalier

size is obtained by using converters fmm the 'hegative setn(fed from transformer

seconciary which are 180" apart from the "positive set") to cancel the 3" harmonic dc

currents. Tbe incorporation of transfomers runs counter to the current trend in which the

prime objective of many resevchers is to use the multi-level concept to do away with the

transfomers in reachiag a bigher ac voltage and hence arrive at a cheaper STATCOM for

distribution level voltages. AcmaUy, there is no contradiction because this thesis

addresses STATCOMs for the very high transmission voltages (and not distribution

voltages) where transfomers are unavoidable. The voltage matching transfomers are

gainfuliy employed to remove the 5& and 7" harmonics on the ac side and the 3* and 6'

harmonics on the dc side. Tbe quality of waveform in this thesis is equivalent to the 7-

level convener.

Except for the 3-level converter, the higher level diode-ciarnped converters cannot

form a comprehensive family of FACTS controllers as the UPFC cannot be realized

economicaiiy because their back-to-back &er/ mverter pair has inherent voltage

instability in the dc link and requires chopper stabilization circuits [ 1 S].

Chaptcr 7 Conclusion 52

In addition to presenting a novel and promishg STATCOM design, this thesis has

made contn'butions in:

(1) Explaining the d e s played by the n'yelwye and wye/delta transfomers in eliminating

ac harmonics while preserving the arithmetic sum of the MVAs of the converters in

the voItage-source converters.

(2) Explaining the method of eliminathg the 3" and 6' harmonies on the de side.

(3) Explaining the conditions in which residual harmonics can meet the THD standards.

--

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APPENDIX A

SYSTEM PARAMETERS USED FOR SiMüLATIONS

Power system voltage base: 1 1jkV

Power system MVA base: 1200 MYA

STATCOM MVA base: 120 MKAr

Z base: 11.02 R

Transmission line reactance: 0.2 pu

Transmission line resistor: 0.002 prt

DC capacitance: O. 76 pu

Transformer leakage reactance: 0.1 pu ( based on 1OWA rating )

Transformer turns ratio: j.6: 1 ( for wydwye ) 3.23: 1 ( for wddelta )

DC voltage reference: 30kV

Total DC voitage regdation PI controIler parameten:

Kp - rural = 1 O degree / kV Ki-mal =750 degree / kV

hiividual DC voltage regulation PI controller parmeters:

Kp-I = -I degree / kV Ki - 1 = -20 degree / kV (inductive mode)

K@ - I = l degree/kV Ki-1 = 20 degree / kV (capacitive mode)

Schematic dtafts of PSCADEMTDC simulation are Listed as folIows in Appendix B:

Fi@-1 Shunt STATCOM Power Circuit

Fig. A-2 Shunt STATCOM Gating Control

Fig A-3 DC Voltage Feedback ConmI

Fig. A 3 UPFC Power Circuit

McGiii University

Appendix C 6 1

O 0.1 0 2 0.3 0.4 Ob 0.6 O.? 0.8 0.9 1

- V& 1 . . . . . . v u

O O. 1 0.2 0 3 0.4 0 5 0.6 O.? 0.8 0.9 1

Fig. A-5 Shunt STATCOM DC voltages regdation

Fig. A-6 STATCOM ac-side currents and voltages

t.2- - 2 0.9 - -- i ; - - : - - A , . ..-.--- y-.- -.----- (Cl 3 0.6 - --

4 0.3--- - I 1 I Z r 1 I 1 . m 1 8

Appendix C 64

Fig. A-8 Unity Power Factor operation of the UPFC