si l 1/sqrt(lw) [um]
TRANSCRIPT
Workshop November 5, 2010
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Acknowledgement
Sponsored by Applied Materials, ASML, Ebara, Global
Foundries, IBM, Intel, KLA-Tencor, Marvell, Mentor
Graphics, Novellus, Panoramic Tech, SanDisk,
Synopsis, Tokyo Electron and Xilinx with matching
support by the UC Discovery Program.
IMPACT Integrated Circuit Variability Modeling and Statistical Transistor Parameter Extraction
Kun Qian, Prof. Costas J. Spanos, University of California, Berkeley
Motivation
Decomposing Random Variability Capturing Systematic Effects Statistical Compact Model Extraction
Testchips in 22/16nm FDSOI and 45nm Bulk 2010 Main Objectives
Parameter Selection Example:
Single 65nm chip I-V data Experimental Results Systematic Spatial Variation
BSIM3v3 Batch Sequential Extraction Future Goals Correlation Structure
Goal 1
Goal 2
Funded by
YOUR
IMAGE
HERE
Sub-wavelength lithography:
Resolution enhancement techniques are
costly and increase process sensitivity
Design
Mask
Wafer
250nm250nm 180nm180nm
OPCOPC
90nm and Below90nm and Below
PSM
0°
180°
PSMPSM
0°
180°
0°
180°
OPC
0°
180°OPCOPCOPC
0°
180°
SiO2 Gate
A. Brown et al.,
IEEE Trans.
Nanotechnology,
p. 195, 2002
Source Drain
A. Asenov, Symp. VLSI Tech. Dig., p. 86, 2007
Gate line-edge roughness (LER):
Does not scale with gate length photoresist line
Random dopant fluctuations (RDF):
Atomistic effects become significant in
nanoscale FETs
Gate work function variation (WFV)
22/16nm Test Chip Design
– Random variability decoupling structures
– Systematic variability capture plan
Variability-Aware Compact Model Extraction
– Algorithmic analysis of parametric observability with
iterative (step-wise) parameter selection
– Implement a sequential parameter extractor that performs
optimization for large number of transistors.
Characterize random and systematic variability - Local and spatial variation
- Process and layout-induced variation
- SRAM and ring oscillator performance
22nm fully-depleted SOI process suppresses
random dopant fluctuation (RDP) and short channel
effect (SCE)
Padded-out SRAM
DUT-Tiles
Pad Ring
DRAM
C-V
Resistor
Ring Oscillator
NMOS
I-V
PMOS
I-V
45nm die photo
22/16nm target chip layout
Ultra-Thin Body
(UTB)
Buried Oxide
Substrate
Source Drain
Gate
tSi
Lg
tSi < (1/4) Lg
3D TCAD simulation results:
Without RDF, Tsi variation is
dominant at large gate lengths, and
both LER & Tsi at short gate lengths
Then LER & Tsi can be further
decoupled
Design for decomposition of
different sources of random
variability:
Low-temperate I-V measurement to
de-activate dopant atoms
Choice of W, LOD to eliminate
narrow width effect and stress-
induced variation, respectively.
0 5 10 15 20 25 30 35 400
5
10
15
20
25
30
35
40
LER + Tsi + RDF @ 50mV of VDS
LER + Tsi + RDF @ 1V of VDS
Avt = 1.06 [mV x um]
sig
ma(V
TH)
[mV
]
1/sqrt(LW) [um]
LER/Tsi/RDF
LER+Tsi
LER/Tsi/RDF
LER+Tsi
Avt = 1.21 [mV x um]
0 5 10 15 20 25 30 35 400
5
10
15
20
25
30
35
40
LER + Tsi + RDF @ 50mV of VDS
LER + Tsi + RDF @ 1V of VDS
Avt = 1.06 [mV x um]
sig
ma(V
TH)
[mV
]
1/sqrt(LW) [um]
LER/Tsi simulated
LER/Tsi estimated
LER/Tsi simulated
LER/Tsi estimated
Avt = 1.21 [mV x um]
Vt .SCE2 VDS 1V
2 VDS 50mV2
Vt
L L
2
Vt
TSiTSi
2
Systematic variations are just as
important as random variations
– Spatial variations at different
hierarchical fabrication levels:
non-uniformity in CVD, PVD,
plasma etching, post exposure
bake (PEB), CMP, …
– Layout dependent effects (litho
proximity, CMP, etch loading, …)
Vertical STI size
Length of Diffusion
Horizontal STI size
Sample layouts for stress effect
Not every compact model parameter is suitable for describing
device variability.
Use a stepwise selection scheme to find proper parameters for
statistical extraction
Convert parameter statistics to a systematic + random
hierarchical spatial model
Parameters
Suitable for
Statistical
Extraction
SPICE
Model
Parameters
Check:
Fitting Quality
Extraction Quality
ADD
REMOVE
Distribution of
Electrical Data
Distribution of
Model Parameters:
Systematic + Random
Optimizer
vto, kp
vto, kp, lambda
vto, kp, lambda, ucrit
step2 step3 step4 step1
Full-set
Die-to-die variation
modeled as a
deterministic
parabolic function +
correlated
Gaussian random
variables
Fitting residual
45nm Padded-out SRAM data
Die-to-die variation
of extracted model
parameters are
fitted using a 2nd
order polynomial
spatial function
Experiment vs. prediction by statistically extracted model parameters
Experimental
SPICE
Variability-Aware Compact Model Extraction
– Study the effects of different parameter selection
scheme for given device parameter correlation
structure.
Explore key applications such as custom “corner”
generation, etc.
Non-linear least square optimization is not always accurate.
0.26 0.28 0.3 0.32 0.34 0.36 0.380.26
0.27
0.28
0.29
0.3
0.31
0.32
0.33
0.34
0.35
0.36
Extr
acte
d V
TH
0
"Actual" VTH0
0.3 0.32 0.34 0.36 0.38 0.4 0.42 0.44
0.31
0.32
0.33
0.34
0.35
0.36
0.37
0.38
0.39
0.4
Extr
acte
d K
1
"Actual" K1
1 2 3 4 5 6 7 8 9 10 11
x 10-3
0.008
0.01
0.012
0.014
0.016
0.018
0.02
0.022
"Actual" K2
Extr
acte
d K
2
0 1 2 3 4 5 6 7 8 9 10
x 1018
7
7.5
8
8.5
9
9.5
10
10.5x 10
17
"Actual" NCH
Extr
acte
d N
CH
Transistor data
simulated using
90nm BSIM3
NCH = NCH0+r1+k1*e1
VTH0=VTH00+r2+k2*e1
K1=K1+r3
K2=K2+r4
r1, …, r4, e1, e2 are
Gaussian random
variables
Artificial strong correlation between VTH0 and NCH induced by
the fitting process.
7 7.5 8 8.5 9 9.5 10 10.5
x 1017
0.26
0.27
0.28
0.29
0.3
0.31
0.32
0.33
0.34
0.35
0.36
"Actual" NCH
"Actu
al"
VT
H0
0 1 2 3 4 5 6 7 8 9 10
x 1018
0.26
0.28
0.3
0.32
0.34
0.36
0.38
Extracted NCH
Extr
acte
d V
TH
0
C-V data Fit NCH I-V data Fit VTH0,
K1, K2