I R, Havasy C,evice LeU, 17

ics, 45 (2001)

stor Modelingew York. 268-

/ices", Fourth

nodo C et al.,) 2221.l) 1339.tans Electron

ciples", John

icentelli A S,, C.A, 1994.1(1978).on Electron

Simulation-

erization ofe, Norwood,

r

Silicon drift detectors with integrated JFET: Simulation and design

Pourus Mehta, Vijay Mishra & S K KatariaElectronics Division, Bhabha Atomic Research Centre, Mumbai 400085

Received 13 July 2004; revised 1 July 2005; accepted 11 July 2005

High resolution, lew energy X-ray spectroscopy systems have been developed recently using the Silicon drift detector(SDD) with in-built Junction field effect transistor (JFET). A comprehensive simulation study of the SDD and integratedJFET with a view to formulate the design flow has been carried out. An optimized process flow for fabricaticn of SDD andintegrated JFET on high resistivity detector substrate is presented. Based on these studies, several mask layouts for the SDD,JFET and reset MOSFET have been designed.

Keywords: Silicon drift detectors, MOSFET, Junction field effect transistor, X-ray spectroscopy

IndianJournal of Pure & Applied PhysicsVol.43, September 2005, pp. 705-713

IPC Code: HOIL31100, HOIL291772

1 IntroductionThe Silicon drift detector (SDD) is based on the

principle of sideward depletion and lateral chargetransport in the fully depleted bulk of the detectorproposedby Gatti and Rehak]. SDD is essentially a 2-sideddiode detector in which high resistivity n-typesubstrate is used to fabricate p-n junctions on bothsidesof the substrate. PN junctions on the front sidearein the form of segmented strips, which act as fieldcathodes whereas a uniform, p-n junction forms theback-contact. Proper biasing between the anode andbackp+ diode fully depletes the bulk. High voltagegradient is applied to the field shaping electrodeswhichcreates a deep potential well that attracts freeelectrons produced by the passage of ionizingradiationthrough the detector. The surface electrodesare symmetrically connected to a voltage dividernetwork that produces an independent electrostaticfieldparallel to the surface of the wafer. This fieldtransports the signal electrons collected in the localpotentialwell towards the. anode of the detector wherethecharges are collected.

The most advantageous feature of SDD is smalloutput capacitance independent of its large activearea.This makes SDD best suited candidate for highresolution and high count rate X-ray spectroscopy/ forXRF analysis etc. Commercially available SDDs giveenergy resolutiorr'" of the order of 160 eY FWHM at

Tel.No.: +91-22-25505212; Fax. No.: +91-22-25505150, +91-22-25505152E-mail:eld@magnum.barc.ernet.in

5.9 keY at -200 C. These detectors also find widespread use in high energy physics for tracking and arebeing used in severalexperiments" of Large HadronCollider at CERN.

As these detectors are used for low energy X-rayspectroscopy, it is essential to integrate the inputdevice of the pre-amplifier with the detector so as toavoid stray capacitance and microphonism arising dueto traditional bonding between them. The integrationof JFET onto the detector also facilitates bettermatching between detector and transistorcapacitances. SDD and p-n charge coupled devicedetectors have been fabricated with integratedjunction field effect transistor onto the detectorsubstrate by several groups. We have carried outprocess and device simulation studies for developingn-channel Junction field effect transistor (NJFET) onhigh resistivity silicon substrate. The processing stepsi.e. implant scheme, diffusion temperature cycles etc.are compatible with the PIN diode detectortechnology". Technological issues involved in thedevelopment of JFET on high resistivity siliconsubstrate and the process simulation results arepresented in this paper. The device simulations havebeen carried out to finalize the device structure ofNJFET. The schematic diagram of radial cross-sectionof the SDD with integrated JFET is shown in Fig. 1.

A key feature of the detector system is its resetmechanism. The integration of reset device (activefeedback resistor) and feedback capacitor along withthe input JFET transistor and various types of resetdevices to be integrated with JFET have been studied

706 INDIAN J PURE & APPL PHYS, VOL. 43, SEPTEMBER 2005

['-Well

i.s k r2-<1Il N-.yp"tHO Silicon

P -~gi.lI forbI >sin 9 rosislor

~

I

II

300um,

IJ+ B ~\cl~C.lfltOtlt

II-t

.sov

Fig. l-Schematic of the SOD structure used for device simulation study. The structure is radial cross-section of the detector. It includesan on-chip JFET fabricated in a low resistivity p-well region

by the researchers recently. Among different deviceslike Pentafet", Bipolar junction transistor'", MOSFET(Ref. 11), the last one has proved be the most suitedone 12 for implementation at Bharat ElectronicsLimited (BEL), Bangalore. The process and devicesimulation for integrating enhancement typePMOSFET with NJFET on high resistivity siliconsubstrate after validating the process at BEL havebeen studied. The process for integration of MOSFETwith NJFET has been simulated drawing inputs fromthe recently standardized PIN fabrication process atBEL (Ref. 13). The various process cycles likeoxidation, implantation, diffusion, etc were simulatedusing the process parameters derived from BEL. Itwas found that the fabrication of NJFET withMOSFET was compatible with the BEL process.

2 Process Simulations for Optimized Process FlowThe purpose of the process simulations is to design

an optimal process flow within the technologicalconstraints associated with the limited processingsteps of the detector and equipment limitations of theconcerned fabrication laboratory. Usuallyimplantation at high energy (- 500-600 keV) isrequired for creating deep p-well and buried channelin the detector substrate". However, no high energyimplanter and no polysilicon processes are availableat associated fabrication lab where PIN diodedetectors with low leakage current have beenproduced using standard Ie fabrication technology'".Therefore, it is essential to design an optimal process

flow with feasible values of process parameters toachieve desired device characteristics.

The technology computer aided design (TCAD)tool was first calibrated with the fabrication lab withexperimental data on sheet resistance and junctiondepth and the results match in close proximity withonly »10% error as shown in Table 1. This practice isvery important in order to ensure validity of theprocess simulation results in relation to realfabrication results. Process simulations have beencarried out to evolve at an optimized process flowwith judicious values of implant energy, dose andthermal budget for fabrication of SDD with integratedn-channel JFET on high resistivity n-type wafer(detector substrate).

Table l--Comparison of experimental results of sheetresistance and junction depth with the simulated values. PI-P7represent different sets of process sequences of doping byimplantation and drive in cycles. The simulated andexperimental values are in close proximity within 10 % oferror

Process Experimental value Simulated value

PI

P2

P3P4P5

1 Sheet resistance

228 nlcm2 229 nlcm2

237 nlcm2 232 nlcm2

9.65 nlcm2 9.9 nlcm2

205 nlcm2 225 nlcm2

211 nlcm2 231 nlcm2

2 Junction depth (p+)

4.79 J.Lm 4.70 J.Lm

4.50 !lm 4.55 !lmP6P7

-4

-2

o

6

8

10o

1E1i

1EH

~ 1E1!-5.81E1 •.,z 1E1:

1E1:

1El

Fig. 2-{:silicon drigate of JFfunction 0

Figurgeneratesteps arsubstratThe doobtainecycles.drive inenergieby hi)implantaroundenergychannel(8E12 (produciThe p-'implan1temper:at 2.5 I

lector. It includes

parameters to

sign (TCAD)ation lab withand junction

.oximity withhis practice isJidity of theion to reals have beenprocess flow~y, dose andith integratedz-type wafer

ilts of sheetvalues. PI-P7of doping byimulated andithin 10 % of

d value

12

12

}2

}2

MEHTA et al.: SILICON DRIFf DETECTORS WITH INTEGRATED JFET

(a)-4

,lOI~

_2~CCHU=u--,Ir-_~ SiOt

• 2

eo -~ 4-

l:J,

Silicon

I

10 20 30 40 50 60 70 80 90 100

Microns

lE17 J I p+gate(b)

lEle .J I A n-channel

~ lEIS'5.8 lE14 11 1 POwell

Q;Z lE13 11 \ substrate

lE12 -lEl1 l.L---,-

2 4 6 8 10Depth,f1I11

Fig,2--{a) Schematic cross-section of NJFET integrated withsilicondrift detector. The anode of the detector is connected withgateof JFET with a metal strip (b) net doping concentration as afunctionof substrate depth along the gate region

Figure 2 (a and b) shows cross-section of the devicegenerated after simulation of all the technologicalsteps and net doping concentration as a function ofsubstrate depth along the gate region respectively,Thedoping profiles in each region of the device areobtainedby ion implantation and subsequent drive incycles. The doping profiles are governed mainly bydrivein temperature cycle and not by ion implantationenergies. The source and drain electrodes are formedby high dose and high energy phosphorousimplantation (lEIS cm-2 @ 80 keY). Gate region isaround 0.5 p,m deep obtained by high dose and lowenergyboron implantation (lE14 em" @ 60 keY). N-channel region is obtained with phosphorous implant(8E12 ern" @ 80 keY) and subsequent drive in cycleproducing the junction within p-well at 1.5 p,m depth.Thep-well region is obtained at low dose and highimplant energy (lE12 cm' @ 80 keY). The drive intemperature cycle forces the p-well junction to centreat2.5 /Lmdepth in the substrate. The p-well separates

707

the n-channel from the underlying fully depleted bulk.The gate length is 10 p,m and the spacing between thegate implant and the source and drain implants is 10p,m each. The peak phosphorous concentration in thechannel is 1.3E16 ern". The generated devicestructure was used in device simulator to obtain thedevice behaviour of the JFET. The observed JFETdevice characteristics are in the range as reported inpublished literature". The p+ gate of JFET and p+strips of the SDD are defined using the same masklayer. Similarly, n + source and drain of JFET and n +

anode of SDD are defined using the same mask layer.

2D process simulation has been carried out tocheck the possibility of fabrication of a p-MOSFETtransistor with the process flow without introducingany additional mask layer and any extra processingstep. The reset transistor is designed within the inputJFET without modifying the anode dimension in theregion by reducing the drain contact of JFET andaccommodating p+ source of the MOSFET. The drainof the enhancement type PMOSFET is gate of theJFET and source is obtained by additional p + implantregion. The generated 2D device structure is shown inFig. 3. The gate oxide thickness is around 160 A.However, it is possible to have gate oxide thickness ofaround 0.18 p,m by small change in the processingsequence and without adding any extra temperaturecycle. The oxide thickness over the anode region is160 A above which is the metal layer to have a MOScapacitor. The feedback capacitor is integrated in thisfashion with one of its plates electrically connected toanode of the detector. The width of the device is at thefreedom of the engineer to design capacitance in therange 100 femto Farad (fF) - 1 pico Farad (pF).

3 Device SimulationsThe device simulations have been carried out for

the SDD, in-built JFET and MOSFET structures. Thedevice structures of JFET and MOSFET generated asoutput of the process simulator, was input for thedevice simulator which solves Poisson's equation andcontinuity equation for a large number of mesh pointsin the device region. The device structure for the SDDwas defined in the device simulator programme withall the doping profile inputs from the processsimulations.

3.1 Silicon drift detectorFig. 4 shows the 2D SDD structure and the input

parameters used for device simulation of SDD.Suitable boundary condition and appropriate physical

708 INDIAN J PURE & APPL PHYS, VOL. 43, SEPTEMBER 2005

--4-

- source-

-2 - -It:r:- -~L~I~n-channel ~ ,Anode

fp-well I

~ET PJFET MOSFET drain

gate gate

-0-

-If) _

52-tl -~ --4-

- 4kO-cm n-type substrate ~-

6----

8- ,..---

I ,

o 60Microns

80 100 12020 40

Fig. ~ Cr6ss-section of the device along the MOSFET structure and feedback capacitor. The structure of the device is generated aftersimulating each processing step in ATHENA. The p" gate of JFET is also the drain of the integrated MOSFET

Implanted Resistors

0

2

enc: 4e0

,.~

296

298

300

4 kn-cm n-type NTD <111> 300).Jm.P+ peak concn = 1E181crn>·Resistor Boren concn = 1E15 Icm3

• Anode VlJidth = 100 urn• P+ strip pitch = 120 (70 + 50) IJm• Jx = 0.5).Jm

p+ Back cathode

o 200 400 600 800 1000Microns

Fig. 4--Simulated SDD structure with input parameters to the device simulator

models arbehaviourThere areshaping eback cath(also MOring). Themost 50structureelectronic

Afterselectionchange inbias condthe end cbiased ondepletionapplied tc1 = -5 V,The detecthe abovecathodes i

-100 V ~C7 get b:between t

FigurestructureFigure 5chain resresistor bbetweencurrent ccDuring tlto produ:generatio:

-20

>: 40]?E~ -6011.

-80

-100 .

Fig.5-Pothe horizoncathode 1 =

generated after

MEHTA et al.: SILICON DRIFf DETECTORS WITH INTEGRATED JFET 709

modelsare given as input parameters for accuratebehaviourof device characteristics as in reference'i'.Thereare 15 electrodes in the SDD structure (8 fieldshapingelectrodes i.e. cathodes 1-8, n+ anode andbackcathode, JFET source, JFET drain, JFET gate(alsoMOSFET drain), MOSFET source, p+ guardring).The used simulation tool allows defining of atmost50 regions and 20 electrodes in any devicestructure enough for simulation of any micro-electronicdevice.

After generating the structure with justifiedselection of grid points, the device operation andchangein its characteristics by simulating differentbiasconditions at the electrodes were studied. Onlytheend cathodes (C1 and C8, back cathode) werebiasedon the structured side to establish sidewarddepletionand lateral electric field. Values of voltagesappliedto the electrodes were anode = 0 V, cathode1 = -5 V, cathode 8 = -100 V, back cathode = -50 V.Thedetector gets fully depleted at around -20 V underthe above mentioned biasing conditions. While thecathodesC1 and C8 are biased externally at -5 V and-100 V respectively, the intermediate cathodes C2 -C7 get biased automatically through the resistancesbetweenthe strips.

Figure 5 shows potential distribution in the devicestructure at the surface and centre (150 f.Lm deep).Figure 5 shows unequal potential drop across thechain resistive regions i.e. it is the highest for theresistor between C7 - C8 and lowest for the onebetween C1 - C2. This corresponds to the bulk <

currentcontribution in the bias resistor chain 'current.During this simulation, bulk properties were such asto produce huge leakage current. When the bulkgenerationcurrent is reduced down to low value in the

Anode-- Surface Potential-- Potential in centre

-20

::: -40

1.60Q.

-60

-100 .

200 800 1000 1200000 600

Distance.~m

Fig. 5-Potential distribution (surface and 150 !Lm deep) alongthehorizontal distance from anode towards C8 when anode = OV,cathode 1 = -5V, cathode 8 = -lOOV, back cathode = -50V

range a few nano Amperes, the non-linearity betweenthe potential drops to negligibly small value. Thehorizontal potential distribution at center of the bulkis smooth and linear. The channel of the signalelectrons lies deep in the bulk along diagonal of thestructure. The electric field along the channel isaround 800 VJcm. Corresponding to this value of fieldand an electron mobility of 1350 cm2J Vs at 300 K,electron drift velocity works out to be 1.951 x 106

cm/s. This implies a detector response time (drifttime) of around 100 nano seconds for a drift distanceof around 1000 urn. Based on these simulations, onecan design a SDD of circular geometry (hexagonal orsquare). Value of resistance between biasingelectrodes is 600 kQ for W = 40 um whichcorresponds to a total chain current of around 25 f.LAunder the biasing conditions. The detector outputcapacitance at full depletion is around 93 femto Faradwhich is flexible enough to play with and tune it withthe integrated transistor capacitance.

Fig. 6 (a and b) shows the leakage current of thedetector as a function of reverse bias applied to

lE-9

\.

(a)

a.~ lE-IO.s

IE-II-100

5.Oxl0·15 ~

4.Ox10.15

Eit 3.0x 10.15

<52.0x 10.,5

1.Ox10.,5

0.0 L----.--40 -30 -20 -10

Reverse Bias. V

o

-00 ~O -40Vca. V

-20 o

(b)

Fig. 6--(a) Leakage current of the detector as a function ofreverse bias applied to C8 cathode. The sudden rise in leakagecurrent at voltages less than full depletion voltage is due tospecific way of applying biasing ramps to other cathodes i.e. Cland back cathode. (b) CV characteristics of a simulated SDDstructure

710 INDIAN J PURE & APPL PHYS, VOL. 43, SEPTEMBER 2005

cathode C8 and the CV characteristics of the proposedSDD structure respectively. As the reverse bias isincreased, the depletion region extends as function of.JV from both sides of the device. The capacitancedecreases to significant low value during initialreverse bias of -5 V when the depletion region fromfirst strip touches the n" anode. Further increase inreverse bias continues to deplete the bulk (and reducethe capacitance) till full depletion is reached at -20 V.Beyond this bias, there is no decrease in capacitancewhich saturates to a low value corresponding to aparallel plate capacitor of area that of anode andspacing between the plates being the detectorthickness.

3.2 Junction field effect transistor (JFET)The JFET device structure generated in process

simulator was exported to the device simulator anddevice characteristics studied. The JFET was biasedin common source configuration with the source atOV and drain voltage of 15 V and gate voltage variedfrom 0 V to -10 V. Fig. 7 shows the Io-Vos (drain)and 10-Vas (transfer) characteristics of the JFET

5.0x 10.3,-----..,...----r-----.---~--_,.(8)

4.Ox10.3

f 3.Oxl0·'...§

vc;,=·lV

having gate width of 190 p,m. The resultant pinch-oilvoltage is Vp = -5 V and the saturation drain currentIS

=3 mA (Fig. 7). The transconductance at 10 = 4 mAand Vos=15 V is gm = 1.1 mS. The channel resistancein the linear region is ~ 1 kO. The slope of the ID• VDS

curve in the saturation region corresponds to anoutput resistance of 7.5 MO. The gate leakage currentis less than a few pA at operating conditions whichwould be significantly small as compared to leakagecurrent of the detector (1 nA). This ensures shot nOisecontribution due to gate current is negligibly smallascompared to the one associated with the detectorleakage current. It was observed that the transistordoes not breakdown even at 50 V of Vos. ID·VDS

curve for Vas = 0 V for Vos up to 50 V. The gatetosource capacitance at operating bias is 200 iF. Thegate capacitance is in such a range that outputcapacitance of the SDD can be matched to get optimalresults.

0,0 1-:-V~.,===4:7V::===::::::r=====:!========::::;iI......-,....•...•..• /

-4.0x 10" •....•••.•••..- "

- 8.0x 10" VGS

~- •• =.:==::::-----:..v ;.6 v -•..•.. - .•.....

Q. _ 12.Ox10"" 00 •••_ ••••- •••. - - •••.• •••

E V•••• 7 V~ -16.0x 10"

- -20.0xl0"

- 24.0x 10"

-28.Ox 10"

- 32.0x 10"2.0xl0·3

VC;S =.) V

Cf'~ ·4 '<Vet-·,··..,

o 2 6 12 14 168

Vos,V

10

5.0m ~--..----..---,.----,------,

4.0m

~~:.::::-JV••• -10 V (8)

(b)·Qm'"1.1 mS

33.0m

2.0m

1.0m

0.0 -l-------

-10 -2 o

-18 -16 -14 -12 -10 -8 -6 -4 -2 0

Vos,V

0.0 Vo• = 15 V

-8

-4.0x 10"

VT·5V

Fig. 7-(a) [o·Vos characteristics ofNJFET with W= 190 urn, (b)[D·Vas characteristics of the same device

-1.0xl0"

~ -2.0x 10""

Iii..9 - 3.0x 10"

-12 -2-10 -8 -6 -4

VGS,V

Fig. 8-(a) Drain characteristics of PMOSFET for differentvalues of Vas (b) [os versus Vas curve for Vos = 15V. The curvesbring out the functionality of the simulated structure withinNJFET as a MOSFET transistor. Vr of the transistor is 5 V. Thisvalue of VT is large as compared to conventional MaS transistors.However, the proposed transistor is to be used in sub-threshodregion so the gate bias has to be always less than 5V

3.3 ResetThe I

functionsFig. 8 sMOSFE1feedbackresistanothermaldevice Ipurpose.a continua de pathlinear delamplifierfaster retdischargeknown texponentsteps".

The IT.

detectorThe mosinput dtcontributsignals fin depththe equiv

where 1/capacitansignifiesworseninConsidersimulatio(typical.value carof the ore

Fromsaturatioiby the ch

esultant pinch-oin drain current'ace at ID = 4channel resistanlope of the 10-VIirresponds tote leakage curreconditions whiapared to leakaensures shot noiegligibly small ;vith the detect,hat the transist, of VDS. 10-VI;0 V. The gates is 200 fF. Thlmge that outpled to get optirn

.>(8)

-6 -4 -2 0

.5V

-4 -2

)SFET for diffenos = 15V. The curvued structure witransistor is 5 V.onal MOS transistoused in sub-threshdthan5V

MEHT A et al.: SILICON DRIFT DETECTORS WITH INTEGRATED JFET 711

3.3 Reset MOSFETThe MOSFET was simulated with a fully

functional JFET and its characteristics were extracted.Fig. 8 shows the characteristics of the simulatedMOSFET. The integration of a simple resistor in thefeedback loop would not be practical as large value ofresistance (z 500 M.Q) would be required due to itsthermal noise considerations. Therefore, an activedevice like PMOSFET should be used for thepurpose. The purpose of the reset device is to providea continuous discharge of the feedback capacitor anda de path for the detector leakage current. Due to non-linear dependence of 10 on VGS, output response of theamplifier would not be exponential, but would show afaster return to zero with respect to an ideal resistivedischarge of same time constant. However, it isknown that output response reduces to an almostexponential function for small values of outputsteps".

The main aim behind integration of JFET on thedetector chip is to achieve low noise performance.The most significant aspect of JFET to be used asinput device of the pre-amplifier is its noisecontribution. The issues relating to processing ofsignals from solid state detectors have been coveredin depth by Gatti and Manfredi 15. An expression forthe equivalent noise charge is as follows:

1

[~1 1)2 J4qkT CD '2 C '2

ENCopr=a to; (~) +(%D) I,CQ

... (1)

(b)

where II = detector leakage, Co = detector outputcapacitance, C, = input capacitance of JFET and roTsignifies bandwidth of the transistor and (l representsworsening factor arising due to actual shaper.Considering the transistor parameters obtained by thesimulations and detector capacitance of - 200 fF(typical for an SDD) and leakage of 1 nA (actualvalue can be much lower), an equivalent noise chargeof the order of 30 electrons has been obtained.

From the noise point of view, a MOSFET insaturation mode would contribute noise determinedby the channel thermal noise given by Eq. (2),

NOiSeSj.MOSFET=4kT%glll=4kT%~2,upCOX : ID '" (2)

In Eq. (2), ID is equal to the leakage current of thedetector. WIL ratio can be made small to reduce thenoise but the technological considerations does notallow going beyond WIL z O.S. Therefore, integratedMOSFET transistor cannot be used in saturation modefor reset purpose rather it is advantageous to operatethe device in the triode region. The dynamicresistance of the channel in sub-threshold region isindependent of Vos and is given by Eq. (3).

• JFET Probe Pad. •Guard Anode

••"o~fII.!t"Willa 0...s,:::; 0in&:

• •(a)

JFET Probe Pad.

• •Guard Anodel

••"~••••-"Willa 0...so•• -'I.!!e1XI0..

• •(b)

Fig. 9 - (a) Layout of SDD in circular shape (b) layout of SDDin hexagonal shape. Only the top metal layer is shown for clarity

712 INDIAN J PURE & APPL PHYS, VOL. 43, SEPTEMBER 2005

1... (3)

For the simulated device, gate capacitance per unitarea, Cox = 2.15 X 10-3 FIllm2, W = 5 11m and L = 1011m, VT = 5 V. The dynamic resistance of the devicefor Vcs ~ VT, is in the range 1 M.Q to around 10 k.Q.Due to minimum linewidth of technology being 4 11mat BEL, W cannot be reduced any further for highervalues of resistance. However, it is possible to do thatif the devices are fabricated at fabrication labs whereminimum features can be lower than 4 11m i.e < 111m.Then the dynamic resistance can be in the rangearound 5 M.Q to 50 k.Q. Also simulations have beencarried out to see the change in the JFETcharacteristics when the integrated MOSFET is biasedto its operational voltages. The results confirm nochange in the device characteristics of JFET withMOSFET biased.

4 Mask LayoutThe mask layout for 4" wafer for fabrication at

Bharat Electronics Limited, Bangalore is beingcarried out. Several SDD structures with integratedJFET have been designed. Fig. 9 shows a layoutconsisting of two SDD structures of active-area 9mm'' having circular and hexagonal geometry with adie size of 5.6 mm x 5.6 mm. The JFET geometry ismaintained circular even in the hexagonal SDDstructure to maintain a high gill. A composite figure ofall layers of circular JFET is shown in Fig. 10.

The die size is 5.6 mm x 5.6 mm for all designs.SDD structures have been designed with implantedresistors for self-biasing and also without implantedresistors and separate probing pads for each biasingstrip. Gate area is 1884.51 11m2 and the correspondingvalues 0(. Ccs = 480 fF and gill = 1.05 mS wereconfirmed: JFETs for high value of gm have beendesigned in comb structures. The anode capacitance is

Fig. lO-Composite layout of a circular JFET showing all the layers of the mask. D, G and S correspond to drain, gate and sourcerespectively

around 50 fF9.2 mm'. Twith many \matching anthe final sta]

5 Conclusn'2D-devicl

order to arriand JFET tthese studiiJFET whicJFET haveassociated 1

high resistresolved. 1design ofconsideratidetectors hout systenintegratingNJFET f,capacitanoleakage cubeen takerof the deprovide usthe varioioptimisedfabricatioiMumbai.

AcknowbThe au

for Prof:

, gate and source

MEHTA et al.: SILICON DRIFT DETECTORS WITH INTEGRATED JFET 713

)r fabrication atalore is beingwith integrated

shows a layout)f active-area 9geometry with a<ETgeometry isiexagonal SDDnposite figure ofFig. to.for all designs.with implantedthout implanted'or each biasinge corresponding1.05 mS were

. gm have beene capacitance is

around50 fF. The active area of the detector is around9.2mm'. The JFETs have been separately designedwithmany varying design parameters for an accuratematchingand design of the SDD with built-in JFET inthefinal stage.

5 Conclusions2D-device simulations have been carried out in

orderto arrive at a design for the silicon drift detectorandJFET together with PMOSFET. On the basis ofthesestudies, the mask layout for the detector andJFETwhich includes various designs of SDD andJFET have been completed. Technological issuesassociatedwith indigenous development of NJFET onhigh resistivity detector grade silicon have beenresolved. The device simulation results for optimaldesign of JFET have been presented. Noiseconsiderations relating to the JFET coupled withdetectorshave been discussed. We have also carriedout systematic process and device simulations forintegrating the reset MOSFET transistor within theNJFET for continuous discharge of feedbackcapacitance and providing de path for the detectorleakagecurrent. All the technological constraints havebeentaken into consideration for practical feasibilityof the device fabrication. These simulation studiesprovideus with the preliminary design parameters forthe various process parameters and these will beoptirnised further by experimental studies at the IC-fabrication facilities at Indian Institute of Technology,Mumbai.

AcknowledgementThe authors would like to express deep gratitude

forProf Dinesh Sharma and Prof Ramgopal Rao of

Indian Institute of Technology, Mumbai for theirguidance and support. The authors wish to thank Dr PP Vaidya, Shri P K Mukhopadhyay, Shri V BChandrate, Dr Anita Topkar for their kind co-operation. We would also like to thank Shri V DShrivastava, Smt Prafulla, Smt R Kaur andElectronics Division for fruitful discussions andsupport in these design studies.

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