simon muff 2018.12files.iccmedia.com/pdf/2018_powercon/bangkok_1630_keysight.pdf · model of the...

Simon Muff 2018.12.04

Business Development Manager, Keysight EEsof EDA

2

P O W E R S E M I C O N D U C T O R F I G U R E O F M E R I T ( F O M )

Copyright 2018 Keysight Technologies, Inc.

Transistor FOM:On resistance (Ron) x gate charge (Qg)

Small FOM = fast dv/dt switching

Sources: Kalfass - Keysight workshop (2015)Catrene (2013)

Switching loss dominates conduction loss in high speed converters

Power Device Switching Loss:Ploss = Rds(on) (ID)2 (rms) + ID VD (Qsw/IG) fs + 1/3 Qds VD fs

Low Ron = low transistor loss

Low Qg allows the device to switch on and off faster

4

Surge V > BV

Circuit Co-Simulation with EM

1.000M

10.00M

100.0M

100.0k

150.0M

-10

0

10

20

30

40

50

60

70

80

90

-20

100

freq, Hz

Volta

ge [d

BuV]

CISPR 25, Class 5 Compliance: Total Noise (peak)

1.000M

10.00M

100.0M

100.0k

150.0M

-10

0

10

20

30

40

50

60

70

80

90

-20

100

f H

Volta

ge [d

BuV]

CISPR 25, Class 5 Compliance: Total Noise (peak)

VRMs and Sinks

12

3

4

D E S I G N A N D L AY O U T C H A L L E N G E S W H Y S I M U L AT E ?

High di/dt High Gbps

Crosstalk, Impedance

EMC / EMI

Power Supply &Thermal performance

Resonances

Via currents

Timing / SI

Temperature

Parasitics

Voltage spikes

No PDN – Ideal VCC

VCC Bounce

494mV

350mV

12

3

4

Temperature View

7

K E Y S I G H T H A S S O L U T I O N S F O R T H E D E V I C E E C O - S Y S T E M

DC- DC+M5M6

Bootstrapdiode

Gate driver

Module Level Analysis

SiC device

Package + Die AnalysisDevice Modeling

8

W E G O W H E R E V E R T H E P O W E R / E N E R G Y G O E S

Native ADS gate driver, analog/digital control loop incl. PWM

Sub-circuit simulation

Finite Element MethodFinite-Difference Time-DomainTechnology

Connector simulation

Method-of-MomentsTechnology

EM-based models: Package and board level parasitic extraction

Center image credit: Transphorm

MMF-flux magnetic circuitsJiles-Atherton saturation/hysteresis model

Non-linear magneticsImport SPICE decks in non-ADS dialects: PSPICE, LTspice, etc.

Device and sub-circuit models for third-party tools

Solves for interaction of temperature rise on device heat output

Electrothermal

Power Device Model GenerationAnd Simulation

IGBT, PowerMOS incl. SiC, ASM GaN

1.000M

10.00M

100.0M

100.0k

150.0M

0

10

20

30

40

50

60

70

-10

80

freq, Hz

Volta

ge [d

BuV]

CISPR 25, Class 5 Compliance: Differential Noise (peak)

EMI/EMC

12

F O U R I E R C O M P O N E N T S O F A 2 M H Z P U L S E

Keysight EEsof EDA - EMC Seminar Vienna

Time domain plots with limited harmonic contents

1000 harmonics

2

5

10

50

Switchers produce relevant harmonics into communications spectrums!

2 MHz silicon MOSFET device

Very Fast Switching Circuits

13

i2i1 i3

291 292 293 294 295 296 297 298 299290 300

1

2

0

3

time, usec

i_1

291 292 293 294 295 296 297 298 299290 300

1

2

0

3

time, useci_

2

291 292 293 294 295 296 297 298 299290 300

1

2

0

3

time, usec

i_3

High di/dt in switched

loop


14

i1i2 i3

When does the layout of the switched loop become important?

Vspike = Lparasitic * di/dtVspike = Lparasitic * Ion/τ

291 292 293 294 295 296 297 298 299290 300

1

2

0

3

time, usec

i_2


16

EM analysis (Layout) Circuit+ EM analysis (schematic) Circuit analysis (schematic)

I N C L U D E E M A N A LY S I S R E S U LT S D I R E C T LY A S S U B C I R C U I T V E R I F I C AT I O N O R A N A LY S I S

Layoutlook-alike model

2 4 6 8 10 12 14 16 180 20

-25

-20

-15

-10

-5

-30

0

freq, GHz

dB(v

ar("

S"))

SnP (S parameter)

Including PC boardeffects

TRANSIENT

VV

HG

LS

HS

LG

VarEqn

I_Probe

Diode_Model

Diode

Gate_driver

VAR

Diode

SwitchV

SwitchV

emModel

L

Tran

C_200u

R

C_10u

V_DC

Converter_layout

I__5

I_in

DIODEM1

DIODE2

VAR1

DIODE1

SWITCHV2

SWITCHV1

I__6

L1

Tran1

X1

R1

I__0

SRC1

_tr=100e-9_fsw=500e3

R=20 mOhmL=1.2 uH

MaxTimeStep=_tr/4StopTime=200/_fsw

Vh=1fsw=_fsw

R=0.4 Ohm

Tdead=50e-9D=0.3tr=_tr

Vdc=12 V

v3v4

vo_p

vin_n

vo_n

v2

v1

vin_p circuit

152 154 156 158 160 162 164 166 168150 170

2.0

1.5

2.5

time, usec

vo_p

-vo_

n

152 154 156 158 160 162 164 166 168150 170

2.0

1.5

2.5

time, usec

vo_p

, V

17

C O - S I M U L AT I O N W I T H I N T E G R AT E D E M R E V E A L S I S S U E S T H AT M AY B E M I S S E D

Increasing Reliability and Efficiency in Next Generation Power Converter Designs

Increased emissionsSurge V > BV

Efficiency Drop

Schematic only simulation

Circuit Co-Simulation with EM

18Copyright 2018 Keysight Technologies, Inc.

• Field solver extracts EM-based model of the layout parasitics

• Method of Moments provides the best balance of speed and accuracy for PCB/packages

• Compact, EM-based model of layout parasitics is added to the familiar transient (SPICE-like) circuit sim

Layout and schematic are tied together

19

S T I T C H I N G B O N D W I R E S O R B O N D W I R E A R R AY S

Drop and Drag Components from Library Insert Bondwire and Select shape to stitch

20

I N 3 D V I E W

21

• EM-model informs the circuit simulation

C I R C U I T E X C I TAT I O N I N F O R M S T H E E M P O S T- S I M U L AT I O N V I S U A L I Z AT I O N D I S P L AY


91.95 92.00 92.05 92.10 92.15 92.20 92.2591.90 92.30

0

10

20

30

40

50

60

70

-10

80

time, usec

Dat

aSw

itchN

ode4

..vol

tage

shift

edsw

Switch node with probe

SimulationMeasurement

23

Simulation with a conventional model

Waveforms don’t match.• Ringing/overshoot are not simulated (flat line)• Timing deviation• Slew rate deviationExact waveform match is critical for noise calculation as waveform contains high frequency components

Simulation with the Keysight math model

Excellent matching between simulation and measurement

What makes this improvement?

Blue: MeasuredRed: Simulation

Blue: MeasuredRed: Simulation

Ids,

AVd

s, V

Ids,

AVd

s, V

Time, μs Time, μs

Time, μs Time, μs

0

800

400

0

60

30

80.8 90.8

80.8 90.8 94.8 95.8

95.8

Time, μs Time, μs80.8 90.8 95.8

Ids,

AVd

s, V

0

800

400

0

60

30

0

800

400

0

60

30Id

s, A

Vds,

V

0

800

400

0

60

30

94.8

Time, μs80.8 90.8 Time, μs 95.894.8 94.8

Source: “Measurement Methodology for Accurate Modeling of SiC MOSFET Switching Behavior over Wide Voltage and Current Ranges”, H. Sakairi, et. al., IEEE Trans on Power Electronics early access,

24

D E V I C E M O D E L

• Modified popular Angelov GaN• To represent SiC or GaN behavior better• Independent of device physics parameters (e.g. Tox) → Everyone (e.g. circuit designer) can use it

tanh Lambda1 × tanh 1 + Lambda2 × 𝑉𝑉𝑔𝑔𝑔𝑔 × 𝑉𝑉𝑑𝑑𝑔𝑔

Added Vgs, Vds dependent parameter to drain current equation to better represent unsaturated drain current

Added body diode to better fit to SiC

𝑄𝑄gs= 𝐶𝐶gspi + 𝐶𝐶gs0 × tanh 02+ 𝐶𝐶gspi + 𝐶𝐶gs0 × tanh 01 + 𝐶𝐶gs0i × tanh 1i × tanh 02

tanh )𝑋𝑋𝑋𝑋(𝑖𝑖 = 1 + tanh 𝐴𝐴 + 𝐵𝐵 × 𝑉𝑉gs + 𝐶𝐶 × 𝑉𝑉ds

Added tanhXX to express a positive bias dependence on charge equation

Source: “Measurement Methodology for Accurate Modeling of SiC MOSFET Switching Behavior over Wide Voltage and Current Ranges”, H. Sakairi, et. al., IEEE Transactions on Power Electronics, Volume33, Issue9, pp7314-7325, September 2018

28

F=100kHz F=300kHz

Current density analysis over frequency using this methodConventional New method

Solid line: simulationDashed line: measurement

Ids

Vgs

Vds

Ids

Vgs

Vds

SimulationMeasurement

Frequency characteristics


Solid line: simulationDashed line: measurement

30

Ciss

Coss

CrssMeasSim

A D S , K E Y S I G H T M AT H M O D E L A N D M E A S U R E M E N T R E S U LT S C A N C H A N G E T H E W O R L D

Dotted: MeasuredSolid: Simulation

Simulation with a conventional model

Waveforms don’t match.Exact waveform match is critical for noise calculation as waveform contains high frequency components

Keysigh math basic current equation

Simulation with the Keysight math model

• Specially developed mathematical model uses tanh in current equation or capacitance equation

• Good convergence• Easy to represent complex IV or CV• Less number of parameters ( < 100)• Generic and applicable regardless of material or

structure

Apply Keysight mathematical model and key measurement data

Polynomial model based on a math model

by DPT (*)by B1506A

* DPT = Double pulse test

I-V C-V

Taken by B1506A

S-parameters for circuit parasiticOn-state C-V through S-parameters

Dotted: MeasuredSolid: Simulation

Excellent matching between simulation and measurement

Vds=1V

Vgs = 0V to 11V(0A to 1.43A)

EM simulation


33

ENA w SMU

Measurement data

W8598BP/BTSimple-use

PEMGADS / EMPro / Momentum

Model parameters

B1506A(B1505A)

by DPT (*1)by B1506A

I-V (*2)

Zero-bias s-parameters

C-V

On-state C-V through S-parameters (*2)

DPT

ENA (E5080A)

Test solutions

Circuit/EM simulation with significantly improved accuracy

Keysightmathematical model

PD1000A software

*1: DPT: Double Pulse Test System

PEMG: Power Electronics Model Generator

*2: Source: “Measurement Methodology for Accurate Modeling of SiC MOSFET Switching Behavior over Wide Voltage and Current Ranges”, H. Sakairi, et. al., IEEE Transactions on Power Electronics, Volume33, Issue9, pp7314-7325, September 2018

W2240 ADS Power Electronics Bundle: Core, TC, PE Lib, Layout, Mom

W2375 Power Electronics Library

34

Paddle

Device 1

Device 2

Single device schematic representation

Foundry process design kit (PDK)

Two devices with different topologies

ADS schematic

ADS layout

35

Mutual cell heating drives up temp

Mutual die heating

Potential sites for premature

failure

>50C iso contoursThermal map with mask

Die temp 36 degrees higher with topology 1

96.3 C peak temp

36

• Co-Simulation is a must in the high di/dt era• Electromagnetic:

• Switching loss optimization• Parasitics control reduces EMI

• Electrothermal• Allows optimizing layout for long endurance• Identifing potential improvements or issues

• Accuracy of results provides key insights• Exact Transitor modeling for high performance devices is a must• Measurement for chracterization (or vendor provision)

• Both Key Insights provides differentiation

W H AT T O R E M E M B E R B E Y O N R U L E S O F T H U M B


41

H I G H S P E E D P O W E R C O N V E R T E R A P P L I C AT I O N A R E A

Hitting the High Speed Wall

42

• On Semiconductor Test Board MoM Mesh

G O O D C O R R E L AT I O N W I T H M E A S U R E D R E S U LT S

91.95 92.00 92.05 92.10 92.15 92.20 92.2591.90 92.30

0

10

20

30

40

50

60

70

-10

80

time, usec

Dat

aSw

itchN

ode4

..vol

tage

shift

edsw

Switch node with probe

91.85

91.90

91.95

92.00

92.05

92.10

92.15

92.20

92.25

92.30

92.35

91.80

92.40

0.0

2.5

5.0

7.5

10.0

12.5

-2.5

15.0

time, usec

Dat

aHig

hGat

e..v

olta

gesh

ifted

Hig

hGat

eDiff

High side gate drive

Red: simulated resultsBlue: measured results

FDMS86181 PowerTrench® MOSFETADS package model

simon muff 2018.12files.iccmedia.com/pdf/2018_powercon/bangkok_1630_keysight.pdf · model of the...

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