sip research iemrc - loughborough university · 2014-04-08 · – 4 academic staff, 5 ra’s, 4...
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System-in-Package Researchwithin the IeMRC
Prof. Andrew Richardson (Lancaster University)Prof. Chris Bailey (University of Greenwich)
LANCASTERU N I V E R S I T YCentre for Microsystems
Engineering
Faculty of Applied Sciences
LANCASTERU N I V E R S I T YCentre for Microsystems
Engineering
Faculty of Applied Sciences
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Project Statistics
• Design for Manufacture Methodology for SiP– Academic partners : Lancaster University & Greenwich– Industrial partners : NXP, Flowmerics, Coventor & Selex– £206K – Nov 2005 – Nov 2007– Focus : Reliability Engineering of SiP assemblies
• Solder ball and assembly reliability modelling• Embedded test & reliability indicators
– Uptake potential :• Through application of knowhow on NXP demonstrator,• capture of code within tools• Generic application of embedded test strategies
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What is System-in-Package, or SiP?
• The integration of several Integrated Circuitsand components of various technologies (RF,analogue, digital, in Si, in GaAs) in a singlepackage, resulting in one or several electronicsystems
• Related key words:– Heterogeneous Integration, System-on-Chip, SoP
Stacked StructuresSide-by-Side Structures
EmbeddedStructures
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Market Trends : Industry moves to WLP
• Both TechSearch and Gartner confirms a significant growthof WLP deliveries
• 70% of WLP applied to Integrated Passives in 2005
Source: Gartner 1Q06 +TechSearch 3Q04
WLP Market Projection
0
2 000
4 000
6 000
8 000
10 000
12 000
14 000
16 000
18 000
2000 2001 2002 2003 2004 2005 2006 2007 2008 2009 2010
Mu
sh
ipm
en
t
Gartner
TechSearch
Gartner 1Q06
CAGR 04-09
33%
TechSearch 4Q04
CAGR 04-09
26%
• Expected CAGR 04-09 > 25%
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Move to full silicon-based SiPs
year
MCM + discretepassives on laminate
MCM + discretepassives on laminate+ Integrated Passive
Multi-Chip Modules (MCM)
100%silicon-based
SiP
1990 1999 2004
Pro
porti
on o
f SiP
year
MCM + discretepassives on laminate
MCM + discretepassives on laminate
+ Integrated Passives
MultiChip Modules (MCM)
100%Silicon-based
SiP
1990 1999 2004
= leadframebased+ WL-CSP
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Integration Trend
Passive/Interconnect dieActive Die
SMDs / Components
Discretes SolutionsPCB
MCM SolutionsPCB
Laminate + SMDs SolutionsPCB
Laminate + SMDs + Passive diePCB
Double Flip Chip assemblyPCB
Wafer Level PackagingPCB
3D WLP SiPsPCB
NXP SiP Platforms Trend
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WL-SiP: challenges
• Larger WL-CSP modules (because SiP are larger than current WL-CSP parts)– Board Level Reliability (solder fatigue issue)
• Larger WL-CSP modules– Board Level Reliability (solder fatigue issue)
• Assembly flow– Final Test– Marking– Packing– Storing
• Customer acceptance– Customers and assemblers (pick & place, under fill dispensing on PCB)– Designers (sockets for evaluation boards)– PCB makers: downwards CTE curve to be supported
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Lancaster University
• Centre for Microsystems Engineering– 4 academic staff, 5 RA’s, 4 PhD’s– Delivered against £3.4M in grant income over the past 10
years– Leads the European Design for Micro & Nano Manufacture
community through the FP6 Network of Excellence(PATENT-DfMM)
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University of Greenwich
• Centre for Numerical Modelling and Process Analysis– 5 Profs, 20+ Post Docs, 40 + PhD’s– One of largest groups in UK
• Electronics and Microsystems– 2 Profs, 3 Post Doc’s, 5 PhD’s– Over £2m of support since 1998 in electronics and microsystems
modelling.
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Modelling Methodology
SiP Data Inputs(Geometry, Materials, Failure Data)
Optimal SiP Structures
High Fidelity Modelling(Multi-Physics)
OPTIMISATION
Sensitivity AnalysisDesign Optimisation
Response SurfaceAnalysis
Reduced Order Models(Multi-Physics)
Design ofExperiments
UncertaintyAnalysis
Man
ufactu
ring
Test/R
eliability
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SiP Structure
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Design Variables
1. PCB thickness (HPCB)2. Board level solder joints stand-off-height
(SOH)3. Passive die thickness (HDIE)
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Design Steps Flow
1. Identify design points2. Simulate responses at each point:
• Joint Lifetime• Package Warpage
3. Construct Reduced Order
1. Account for– Uncertainties in Design Variables– Design for Reliability– Design for Robustness
Design of Experiments
FEA at experimentalpoints
Response SurfaceModelling (ROM)
Sensitivity Analysis
Design Task as OptimisationProblem / Design Solution
Uncertainties
Reliability Robustness
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Finite Element Calculations
1) Warpage of the package: Dw2) Fatigue life of solder joints: Nf
Warpage at 125CSolder Joints Damage
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Step 1: Virtual DoE
• Central Composite Design(CCD)
• 15 Design points• FEA Responses for
• Cycles to failure (Nf)• Warpage of SiP (Dw)
Factorial Point
Axial Point
Central Point
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Step 2: Generate Reduced Order Model
• RoM to represent:– Warpage of SiP– Lifetime of solder joints
• Fast predictions for SiP• Statistical tests for accuracy
– ANOVA– Efficiency measures, etc
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(a) Deterministic Optimal Design
• Design task solved using numerical optimisationtechniques
• Optimal design– Warpage reduced by 22 %– Lifetime Satisfied
Deterministic Formulation
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(b) Probabilistic Design
• Design variables haveuncertainties– Design variables modelled with
Gaussian distribution
• Standard deviations:a) HPCB: σHPCB = 16 um;b) SOH: σSOH = 2 um;c) HDIE: σHDIE = 2.5 um; Deterministic Optimal design
Probabilistic Optimal design
CriticalResponse 1
CriticalResponse 2
Design Variable A
Des
ign
Varia
ble
B
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Design for Reliability
• Constraints re-defined in terms ofprobability of failure
• Monte Carlo simulations– Evaluation of the distribution of the
response values
Probabilistic Formulation
0
200
400
600
800
2640 2660 2680 2700 2720 2740 2760 2780 2800 2820
Fatigue Life (cycles) Uncertanty at Reliable Optimum
Fre
qu
en
cy
95 % of designs haverequired life-time
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0
200
400
600
800
2340 2360 2380 2400 2420 2440 2460 2480 2500 2520
Fatigue Life (cycles) Uncertanty at Robust Optimum
Fre
qu
en
cy
Design for Robustness
• Design for Robustness– design that has minimum uncertainty
(variation) of its responses
• Focus is on life-time
Probabilistic Formulation
± 1σ
σ=14 cycles
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Inter Metallic Layer (IMC)
Solder Ball Reliability
Weibulldistribution
β : Weibull slope parameterη : Characteristic life parameterN : Random thermal life cycles to failureδ : IMC layer thickness
So ACK, Chan YC. Reliability studies of surface mount solder joints–effect of Cu-Sn intermetallic compounds.IEEE Trans Comp Pack Manuf Technol–Part B 1996; 19:661-668.
Objective : Build an Analytic Method of Reliability for Solder Joint in Package
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Inter Metallic Layer Growth
t : Reflow time
Dependence on reflow time (given temperature) :
δ : IMC layer thickness
T : Temperature of reflow
Dependence on temperature (given time) :
Reflow profile
* More accurate than polynomial fitting proposed inHuang W, Loman JM, Sener B. Study of the effect of reflow time and temperature on Cu-Snintermetallic compound layer reliability. Microelectronics reliability. 42(2002) 1229-1234.
Ts : saturatedtemperature
*
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Results : 3D plots
- Low reflow temperature
or avoid the interval[190,240] ???????
- As small a reflow time aspossible
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Further Recent Results
• Effects of process conditions on reliability of lead-freepackages– Solder joint volume– Undefils– Reflow temperatures– Pad Geometries– thermal cycling test (−4 0oC/ + 125oC)
• Twin die stacked packages– Die thickness (bottom and top)– Core thickness– Substrate thickness
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Conclusions
• Work to date focused around silicon based WL-SiP– Embedded health monitoring– Strategies for non-electrical functions– Reliability simulation – structure & assembly
• Investigated effect of underfill on solder reliability• Investigated the impact of moulding process• Developed ROM for specific SiP structures• Software environment developed
• Future Work– Extend to SoP – eg. Ceramic based– Investigate integration into EDA tools
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Acknowledgments
• Dr Nobert Dumas (Lancaster)• Dr Dongsheng Liu (Lancaster)• Dr Nadia Strussavich (Greenwich)• Dr Stoyan Stoyanov (Greenwich)
• And Industrial partners