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1SLVUBB4A–November 2017–Revised February 2018Submit Documentation Feedback

Copyright © 2017–2018, Texas Instruments Incorporated

Power Stage Designer™

User's GuideSLVUBB4A–November 2017–Revised February 2018


Power Stage Designer™ is a Java® based tool that helps engineers speed up their power supply designsas it calculates voltages and currents of 20 topologies according to the user’s inputs. Additionally, PowerStage Designer contains a Bode plotting tool and a helpful toolbox with various functions for power supplydesign. This document describes how the different features of Power Stage Designer can be used andalso explains the calculations behind these functions (for version 4 and higher).

Contents1 Topologies Window.......................................................................................................... 22 FET Losses Calculator ...................................................................................................... 43 Capacitor Current Sharing Calculator ..................................................................................... 54 AC/DC Bulk Capacitor Calculator.......................................................................................... 75 RCD-Snubber Calculator for Flyback Converters ....................................................................... 86 RC-Snubber Calculator ..................................................................................................... 97 Output Voltage Resistor Divider .......................................................................................... 108 Dynamic Analog Output Voltage Scaling................................................................................ 119 Dynamic Digital Output Voltage Scaling ................................................................................ 1210 Unit Converter .............................................................................................................. 1411 Loop Calculator ............................................................................................................. 1412 Additional Information...................................................................................................... 28

List of Figures

1 Main Window of Power Stage Designer Displaying Supported Topologies ......................................... 22 Topology Window for Flyback Converter ................................................................................. 33 Graph Window for FET Q1 of a Flyback Converter Operating in CCM .............................................. 34 FET Losses Calculator Window ........................................................................................... 45 Capacitor Current Sharing Calculator..................................................................................... 66 Bulk Capacitor Calculator for AC/DC Power Supplies Window ....................................................... 77 RCD-Snubber Calculator for Flyback Converters Window............................................................. 88 RC-Snubber Calculator Window........................................................................................... 99 Output Voltage Resistor Divider Calculator Window .................................................................. 1010 Dynamic Analog Output Voltage Scaling Calculator Window ........................................................ 1211 Dynamic Digital Output Voltage Scaling Calculator Window ......................................................... 1312 Unit Converter Window.................................................................................................... 1413 Loop Calculator Window .................................................................................................. 1514 Schematic of a Type II Compensation Network........................................................................ 2315 Schematic of a Type II Transconductance Compensation Network................................................. 2416 Schematic of an Isolated Type II Compensation Network With a Zener Clamp ................................... 2517 Schematic of an Isolated Type II Compensation Network Without a Zener Clamp ............................... 2618 Schematic of a Type III Compensation Network ....................................................................... 27

TrademarksPower Stage Designer is a trademark of Texas Instruments.Java is a registered trademark of Oracle.All other trademarks are the property of their respective owners.

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Topologies Window www.ti.com

2 SLVUBB4A–November 2017–Revised February 2018Submit Documentation Feedback



1 Topologies WindowTo start a power supply design with Power Stage Designer, first select a topology from the start screen orthe Topology menu. The window changes and displays the schematic of the selected topology with a setof input fields and various output values. After entering the parameters of the power supply specification,Power Stage Designer suggests a value for the output inductance to stay below the entered current ripplerequirement. For isolated topologies, the tool also displays a recommendation for the transformer turnsratio (TTR) based on the selected maximum duty cycle and suggests a value for the magnetizinginductance. Users can enter values of their choice and evaluate their impact on voltage and currentwaveforms and other parameters like on-time, off-time, and duty cycle.

Figure 1 shows the main window of Power Stage Designer displaying supported topologies.

Figure 1. Main Window of Power Stage Designer Displaying Supported Topologies

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Figure 2. Topology Window for Flyback Converter

After clicking on one of the yellow highlighted components in the schematic (see Figure 2), a new windowdisplays the voltage and current waveforms for this specific component (see Figure 3). Additionalinformation like the minimum and maximum voltage, minimum and maximum current, as well as root meansquare (RMS), average, and AC values for the current is also provided in this window. The input voltagecan be changed across the entire input voltage range with a slider. For most topologies the load currentcan be altered in the range of 1% to 100% of the entered output current with a second slider. Sometopology models do not support such a wide load current range, thus the load current slider can bechanged only in the range of 50% and 100%. The Quasi-resonant Flyback model uses a fixed outputpower as base for all calculations. That is why the load current slider is not available for this specifictopology.

Figure 3. Graph Window for FET Q1 of a Flyback Converter Operating in CCM

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FET Losses Calculator www.ti.com




NOTE: All equations used for calculations are ideal, with the only exception that the forward voltageof rectifier and freewheeling diodes is considered. For a collection of the equations behindcertain topologies, see the Power Topologies Handbook.

2 FET Losses CalculatorThe FET Losses Calculator lets the user either compare two different FETs or calculate losses for themain FET and a synchronous rectifier in a hard-switching power stage. Figure 4 shows the FET LossesCalculator window.

NOTE: The Quasi-resonant Flyback, LLC-Half-Bridge, and Phase-Shifted Full-Bridge are resonanttopologies. Results might not be accurate.

Figure 4. FET Losses Calculator Window

To attain the most accurate results, it is important to determine the gate drive voltage (VGS) of the powermanagement controller as the values for Qg, which is relevant for driver losses, and RDS(on) are dependenton this voltage and must be obtained from graphs in the data sheet of the FET.

The different losses which can be seen in the FET of a power supply are conducted losses, switchinglosses, Coss losses, and body diode losses. Reverse recovery losses are neglected, but can becomesignificant at high switching frequencies.

Conductive losses:

(1)

Switching losses:

(2)

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http://www.ti.com/lit/pdf/SLYU036

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www.ti.com Capacitor Current Sharing Calculator




Coss losses:

(3)

Body Diode losses:

(4)

The total losses for the main FET can be calculated as indicated in Equation 5

(5)

For synchronous rectifiers, the switching losses equal zero due to soft switching, but during the dead timethe body diode is conducting. So the total losses result as indicated in Equation 6:

(6)

Additionally, driver losses occur in the power management controller, which can be calculated as shown inEquation 7:

(7)

Power management controllers typically have a limited amount of gate drive current they can source andsink. Therefore, it is important to adjust the total resistance in the gate drive path so the resulting gatedrive current is equal to or smaller than the limit in the data sheet.

3 Capacitor Current Sharing CalculatorWhen connecting different kinds of capacitors in parallel at the input or output of a power supply, the RMScurrent going through each capacitor is different as it depends on the impedance of the capacitors acrossthe entire frequency range. For exact results for the RMS current per capacitor, impedances and currentsmust be calculated for all harmonics of the switching frequency. The RMS current for each harmonic mustbe derived with a Fast Fourier Transformation (FFT) of the total current signal based on the ratio betweentotal impedance and single-capacitor impedance at that harmonic frequency. The total RMS current percapacitor can then be calculated with the quadratic mean of all harmonic RMS current values for thiscapacitor.

Figure 5 shows the Capacitor Current Sharing Calculator.

NOTE: In Power Stage Designer, the impedances and the RMS currents are only calculated at theswitching frequency. Thus, the resulting RMS currents are rough estimations.

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Figure 5. Capacitor Current Sharing Calculator

The impedance for one capacitor at the switching frequency (n can be 1, 2, or 3 and refers to thecapacitor index) can be calculated as indicated in Equation 8:

(8)

Typical ESL values for capacitors are from 1 nH to 7 nH. By assuming 6nH/cm as parasitic inductance fora conductor, the inductance for a ceramic capacitor can be estimated by multiplying this value with thecapacitor length. PCB traces and vias can increase this value slightly (see [1]).

The total impedance of three parallel capacitors at the switching frequency results as seen in Equation 9:

(9)

The RMS current of one capacitor, while neglecting all other harmonics besides the switching frequency,can be calculated as seen in Equation 10:

(10)

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www.ti.com AC/DC Bulk Capacitor Calculator




4 AC/DC Bulk Capacitor CalculatorAC/DC power supplies typically require a bulk capacitor behind the input rectifier that provides a quasi-constant input voltage for the converter stage (see Figure 6). Power Stage Designer can calculate theminimum capacitance based on the desired minimum bulk voltage Vbulk,min, the maximum acceptablevoltage ripple ∆V in percent, the input power Pin and the minimum line frequency fline,min (see Equation 11).

Figure 6. Bulk Capacitor Calculator for AC/DC Power Supplies Window

(11)

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RCD-Snubber Calculator for Flyback Converters www.ti.com




5 RCD-Snubber Calculator for Flyback ConvertersIn Flyback converters the output voltage is reflected from the secondary to the primary side. Additionally,parasitics caused by the layout and the Flyback transformer leakage inductance can cause a voltagespike followed by ringing when the MOSFET is turning off. The voltage spike and the ringing can belimited by implementing an RCD-snubber circuit in parallel to the primary winding. The energy of the high-frequency ringing is dissipated in the RCD-network. The RCD-Snubber Calculator for Flyback convertersin Power Stage Designer helps the designer choose the starting values for snubber resistor and capacitorbased on the user’s inputs, which follow:• Sum of output voltage and rectifier voltage• Flyback transformer turns ratio• Leakage inductance• Maximum primary current• Switching frequency• Permitted voltage overshoot as a factor• Snubber capacitor voltage ripple in percent

Figure 7 shows the RCD-Snubber Calculator for Flyback Converters window.

Figure 7. RCD-Snubber Calculator for Flyback Converters Window

Vsnub is the reflected output voltage plus the permitted overshoot caused by transformer leakageinductance and switching node parasitics. Thus Ksnub has a value greater than 1. TI recommends a valueof 1.5 for most applications, permitting 50% overshoot (see [1]). See Equation 12.

(12)

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Starting Snubber resistance:

(13)

Starting Snubber capacitance:

(14)

6 RC-Snubber CalculatorAn RC-Snubber circuit is one option to reduce ringing in a switch mode power supply. Alternatives are theuse of MOSFET gate resistors or a resistor in series with the bootstrap capacitor to slow down rise and/orfall times. With the RC-Snubber Calculator, Power Stage Designer helps the designer determine startingvalues for the snubber resistor and capacitor.

Figure 8 shows the RC-Snubber Calculator window.

Figure 8. RC-Snubber Calculator Window

• Measure the oscillation frequency f0 of the circuit without a snubber network.• Add a capacitor C1 in parallel with the rectifier or FET and measure the shifted oscillation frequency f1.

Select a C1 value that is several times larger than the stated typical capacitance of the rectifier at fullreverse voltage or the output capacitance of the FET.

• After entering these three values, the tool will propose starting values for the R-C Snubber network.

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Output Voltage Resistor Divider www.ti.com




Frequency shift ratio:

(15)

Parasitic capacitance:

(16)

Parasitic inductance:

(17)

Starting Snubber capacitance:

(18)

Starting Snubber resistance:

(19)

7 Output Voltage Resistor DividerThe Output Voltage Resistor Divider Tool calculates the closest resistor values of the chosen E-Series tomatch the specified output voltage based on the entered reference voltage, reference voltage tolerance,and desired resistance value. The resistance value can be entered for the high-side (HS) or the low-side(LS) resistor. It is also possible to parallel two resistors to get more precise results. The followingequations calculate the resulting output voltage while respecting resistor tolerances and reference voltagetolerances. However, because effects caused by the bias current are not considered for the calculations,these values are estimates.

Figure 9 shows the Output Voltage Resistor Divider Calculator window.

Figure 9. Output Voltage Resistor Divider Calculator Window

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www.ti.com Dynamic Analog Output Voltage Scaling




Effective output voltage with chosen resistance values (see Equation 20):

(20)

Bias current:

(21)

Worst-case minimum output voltage:

(22)

Worst-case maximum output voltage:

(23)

8 Dynamic Analog Output Voltage ScalingIf the output voltage of a power supply must be adjustable, add a third resistor to the feedback resistordivider and apply an analog voltage to this resistor (for example, with the DAC of a microcontroller). Theanalog signal can also be provided by smoothing a PWM signal with a low-pass filter. After entering theminimum output voltage, maximum output voltage, reference voltage, maximum adjusting voltage signal,and the desired value for the top feedback resistor, Power Stage Designer calculates the required bottomfeedback resistance and the adjusting voltage signal series resistance, as well as the minimum biascurrent going through the top feedback resistor.

Figure 10 shows the Dynamic Analog Output Voltage Scaling Calculator window.

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Dynamic Digital Output Voltage Scaling www.ti.com




Figure 10. Dynamic Analog Output Voltage Scaling Calculator Window

(24)

9 Dynamic Digital Output Voltage ScalingDynamic output voltage adjustment can also be achieved by applying GPIO signals to an array of resistorsand signal FET combinations in parallel with the low-side resistor of the feedback divider. For most cases,a microcontroller output in open-drain configuration can be used instead of an external signal FETbecause it is already part of the system. Power Stage Designer calculates the low-side feedback resistor,the voltage per step, the bias current, and the series resistance for each bit based on the output voltagerange, the reference voltage, the number of bits, and the value of the high-side feedback resistor.

Figure 11 shows the Dynamic Digital Output Voltage Scaling Calculator window.

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www.ti.com Dynamic Digital Output Voltage Scaling




Figure 11. Dynamic Digital Output Voltage Scaling Calculator Window

(25)

The LM10011 is a device that has this feature integrated for 4/6-Bit VID.

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http://www.ti.com/product/LM10011

Unit Converter www.ti.com




10 Unit ConverterThe Unit Converter can help power supply designers convert typical parameters related to power supplies.These parameters are magnetic flux, gain, length, weight, airstream, PCB copper thickness, andtemperature. Figure 12 shows the Unit Converter window.

Figure 12. Unit Converter Window

11 Loop CalculatorThe Loop Calculator can help power supply designers with the compensation network for voltage modecontrolled (VMC) buck converters or current mode controlled (CMC) buck, boost, inverting buck-boost,forward, and flyback converters operating in continuous conduction mode (CCM). The transfer functionshave been simplified, thus the results give a first-order approximation of how the Bode plot of the powersupply will appear. Figure 13 shows the Loop Calculator window.

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www.ti.com Loop Calculator




Figure 13. Loop Calculator Window

The following steps apply when using the Loop Calculator.1. Select the topology/control scheme and the type of compensation for the design with the radio buttons

in the bottom-left corner. Typically, only the VMC buck needs a Type III Compensation. For all CMCtopologies, a Type II Compensation is usually sufficient.

2. Fill in all input fields with white background. If the Loop Calculator is started from one of the supportedtopologies, applicable values from the topologies window will directly transfer to the Loop Calculatorwindow.

3. Under General Information (from the schematic) sum the capacitance of the same output capacitortypes and calculate their effective ESR. The DC-biasing effect for ceramic capacitors must beconsidered because it can have a major impact on the accuracy of the gain and phase plot of thepower stage.

4. Enter the Gain Information (from the schematic and the data sheet for the controller).5. Fill in the values for RFBT and RFBB. With this information the Loop Calculator can suggest values for

the compensation network of the entered power supply design.

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Loop Calculator www.ti.com




The compensation network suggestions are calculated as follows:

CAUTIONIf unusual input conditions are applied, the suggestions of the tool do notnecessarily lead to a stable system.

• Compensation zeroes are placed on the pole of the transfer function of the power stage (L and Coutdouble pole for VMC, Rout and Cout single pole for CMC).

• Compensation poles are placed on the lower of either half of the switching frequency or the ESR zerofor Buck derived topologies.

• Compensation poles are placed on the lower of either the right half plane zero (RHPZ) frequency orthe ESR zero frequency for Boost/Buck-Boost derived topologies.

• The maximum achievable crossover frequency is approximately two decades below the GBWP (gainbandwidth product) of the error amplifier. The gain of the compensation network should never goabove the open loop gain of the error amplifier. Otherwise, the error amplifier will be clipping.

• For Boost/Buck-Boost derived topologies the desired crossover frequency is automatically set to 1/5 ofthe RHPZ frequency.

11.1 InputsTable 1 lists general Information:

Table 1. General Information

Vin Input voltageVout Output voltageIout Load currentL Inductance / Flyback primary inductance

DCRL Inductor DC resistance

Cout,1Capacitance output capacitor 1For ceramic capacitors use the capacitance at the DC bias voltage.

ESRout,1 Equivalent series resistance output capacitor 1

Cout,2Capacitance output capacitor 2For ceramic capacitors use the capacitance at the DC bias voltage.

ESRout,2 Equivalent series resistance output capacitor 2fswitch Switching frequency

Np ⁄ Ns Transformer turns ratioOpto BW Optocoupler bandwidth

Table 2 lists gain information:

Table 2. Gain Information

Vramp PWM ramp voltageGm Error amplifier transconductanceAs Current-sense amplifier gainRs Current-sense resistanceAOL Error amplifier open-loop gain

GBWP Error amplifier gain bandwidth productRp ⁄ RD Optocoupler transfer ratioVslope Slope compensation voltageSLM Slope compensation multiplier

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m,psS S

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Current-sense gain As and current-sense resistance Rs:

For converters with integrated current-sensing circuits, sometimes there are no specific values for As andRs in the data sheet. Instead, a value for Gm,ps (can also appear as “COMP to switch currenttransconductance”) is typically displayed. Equation 26 shows the relationship between these values.

(26)

In this case, values for As and Rs must be chosen to have the stated Gm,ps as a result. (For example, usethe RDS(on) of the internal FET for Rs and calculate As from Equation 26.)

The input field for Vslope offers the user the option to use either Vslope or a slope compensation multiplier(SLM), in case the value for Vslope cannot be calculated by the designer (for example, because of internalslope compensation). Switching between these two variables can be done by right-clicking on theVslope/SLM input field.

Vslope:• Calculate the value for Vslope with the equations from the data sheet. If the device has internal slope

compensation, a value for Vslope is typically given in the Electrical Characteristics section.

SLM:• SLM is a variable to simulate the slope compensation under certain circumstances. How it affects

calculations can be found in the subsections for each topology.• Ideal slope compensation will be calculated with a value of 1.• Values greater than 1 show how the converter will drift to VMC with increasing values of SLM, as the

information of the original current signal will be lost at a certain point. A Type III compensation networkwould then be necessary to compensate the converter.

• Values in the range from 0 to 1 simulate conditions when not enough slope compensation is present,and a resonance will become visible at half the switching frequency caused by the quality factor of thedouble pole of the inductance.

Table 3 lists component values:

Table 3. Component Values

RFBT Top feedback resistanceRFBB Bottom feedback resistanceRFF Compensation feed-forward resistance

RCOMP Compensation resistanceCFF Compensation feed-forward capacitance

CCOMP Compensation capacitanceCHF Compensation high-frequency capacitance

For Type II and Type II transconductance compensation networks, the Loop Calculator offers an option touse an additional Feed-Forward Capacitor in parallel with RFBT. This option can be enabled by right-clicking on the CFF input field and choosing Use.

At start-up the Loop Calculator displays only the resulting Bode plot for the Total Gain and Total Phase.The graphs for the Gain of the Power Stage, Phase of the Power Stage, Gain of the Error Amplifier,Phase of the Error Amplifier and the Error Amplifier Open Loop Gain can be switched on by selecting therespective checkbox.

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11.2 Transfer Functions

11.2.1 Output Capacitor Transfer Function

For two parallel capacitors the transfer function can be written as shown in Equation 27:

(27)

There are two ESR zeros:

(28)

And there are two ESR poles:

(29)

11.2.2 Transfer Function VMC Buck Power Stage

(30)

DC-Gain:

(31)

LC double pole:

(32)

Calculate Q0 with the larger of the ESR values:

(33)

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(34)

Duty cycle:

(35)

DC-Gain:

(36)

Load pole:

(37)

With Vslope:

(38)

With SLM:

(39)

11.2.4 Transfer Function CMC Boost Power Stage

(40)

Duty cycle:

(41)

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DC-Gain:

(42)

Load pole:

(43)

RHPZ:

(44)

With Vslope:

(45)

With SLM:

(46)

11.2.5 Transfer Function CMC Inverting Buck-Boost Power Stage

(47)

Duty cycle:

(48)

Load pole:

(49)

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(50)

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(51)

With SLM:

(52)

11.2.6 Transfer Function CMC Forward Power StageFor interleaved topologies like Push-Pull, Half-Bridge, or Full-Bridge, twice as much FET switchingfrequency must be used for calculations because the output inductor "sees" twice the FET switchingfrequency.

(53)

Duty cycle:

(54)

DC-Gain:

(55)

Load pole:

(56)

With Vslope:

(57)

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� �22

out pR

out s

V 1 D N

I L D N

§ ·u �Z u ¨ ¸¨ ¸u u © ¹

L switchfZ Su

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1 DC R

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u

� �out pVC

out s s s

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u � u

u � u u

pout

s

pin out

s

NV

ND

NV V

N

u

� u

R

VC 2

2P L L L

s1 E(s)

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§ ·� u¨ ¸¨ ¸Z© ¹ u

§ · § ·� u � �¨ ¸ ¨ ¸¨ ¸ ¨ ¸Z uZ Z© ¹ © ¹

pout s s

se 2

p

s

NSLM V A R

Ns

NL

N

u u u u

§ ·

u ¨ ¸¨ ¸© ¹

sin out s s

p

n

NV V A R

Ns

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§ ·u � u u¨ ¸¨ ¸

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e

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With SLM:

(58)

11.2.7 Transfer Function CMC Flyback Power Stage

(59)

Duty cycle:

(60)

DC-Gain:

(61)

Load pole:

(62)

RHPZ:

(63)

With Vslope:

(64)

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CCOMP RCOMP

RFBT

RFBB

VREF

VFB

VC

CHF

VOUT

+

-

Copyright © 2017, Texas Instruments Incorporated

out

c

Öv H(s) O(s)Öv H(s) O(s) 1

u

u �

out

c

ÖvH(s) O(s)

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opto

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se

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With SLM:

(65)

11.2.8 Transfer Function When Using an OptocouplerIsolated power supplies incorporate an additional pole in the transfer function due to the limited bandwidthof the optocoupler:

(66)

When the forward and flyback power stages are operating with Zener diode clamped isolatedcompensation, the transfer function for the power stage is as shown in Equation 67:

(67)

When the forward and flyback power stages are used without Zener diode clamped isolatedcompensation, the transfer function for the power stage is different:

(68)

11.2.9 Transfer Function Type II Compensation NetworkFigure 14 is a schematic of a Type II compensation network.

Figure 14. Schematic of a Type II Compensation Network

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VM ZEA ZEAc

out

HF

s1

AÖvsÖv s 1

�u Z Z

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�Z

RFBT

RFBB

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VOUT

VC


ZFFFBT CFF

1R C

Z u

PFF

FF

RFBB RFBT

11

C1 1

R R

Z

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�¨ ¸¨ ¸© ¹

HFCOMP HF

1R C

Z u

ZEACOMP COMP

1R C

Z u

COMPVM

FBT

RA

R

VM ZEA ZEAc

out

HF

s1

AÖvsÖv s 1

�u Z Z

� u

�Z





(69)

DC-Gain:

(70)

Compensation zero:

(71)

Compensation pole:

(72)

With additional feed-forward capacitor in parallel with RFBT:

(73)

11.2.10 Transfer Function Type II Transconductance Compensation NetworkFigure 15 is a schematic of a Type II transconductance compensation network.

Figure 15. Schematic of a Type II Transconductance Compensation Network

(74)

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VM ZEA ZEAc

out

HF

s1

AÖvsÖv s 1

�uZ Z

� u

�Z

RP RD

CHF

RFBB

CCOMP RCOMP

RBIAS RFBT

VFB

VCC

VC

VOUT


ZFFFBT CFF

1R C

Z u

PFF

FF

RFBB RFBT

11

C1 1

R R

Z

u§ ·

�¨ ¸¨ ¸© ¹

HFCOMP HF

1R C

Z u

ZEACOMP COMP

1R C

Z u

FBBVM m COMP

FBB FBT

RA G R

R R u u

�





DC-Gain:

(75)

Compensation zero:

(76)

Compensation Pole:

(77)

With additional feed-forward capacitor in parallel with RFBT:

(78)

11.2.11 Transfer Function Isolated Type II Compensation Network With a Zener ClampFigure 16 is a schematic of an isolated Type II compensation network with a Zener clamp.

Figure 16. Schematic of an Isolated Type II Compensation Network With a Zener Clamp

(79)

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ZEACOMP COMP

1R C

Z u

PVM

D

RA CTR

R u

VM ZEA ZEAc

out

HF

s1

AÖvsÖv s 1

�uZ Z

� u

�Z

RP RD

CHF

RFBB

CCOMP RCOMP

RBIAS RFBT

VFB

VCC

VC

VOUT


HFCOMP HF

1R C

Z u

ZEACOMP COMP

1R C

Z u

PVM

D

RA CTR

R u





DC-Gain:

(80)

Power Stage Designer uses a constant value of 1 for CTR.

Compensation zero:

(81)

Compensation pole:

(82)

11.2.12 Transfer Function Isolated Type II Compensation Network Without a Zener ClampFigure 17 is a schematic of an isolated Type II compensation network without a Zener clamp.

Figure 17. Schematic of an Isolated Type II Compensation Network Without a Zener Clamp

(83)

DC-Gain:

(84)

Power Stage Designer uses a constant value of 1 for CTR.

Compensation Zero:

(85)

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HFCOMP HF

1R C

Z u

PFFFF FF

1R C

Z u

ZFFFBT FF

1R C

Z u

ZEACOMP COMP

1R C

Z u

COMPVM

FBT

RA

R

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PFF HF

s s1 1

AÖvÖv s s s

1 1

§ · § ·� u �¨ ¸ ¨ ¸¨ ¸ ¨ ¸Z ZuZ © ¹ © ¹ � u

§ · § ·� u �¨ ¸ ¨ ¸¨ ¸ ¨ ¸Z Z© ¹ © ¹

VREF

VOUT

+

-

RFBT

RFBB

CCOMP RCOMP

CHF

VC

RFF

CFF

VFB


HFCOMP HF

1R C

Z u





Compensation pole:

(86)

11.2.13 Transfer Function Type III Compensation NetworkFigure 18 is a schematic of a Type III compensation network.

Figure 18. Schematic of a Type III Compensation Network

(87)

DC-Gain:

(88)

Compensation zero 1:

(89)

Compensation zero 2:

(90)

Compensation pole 1:

(91)

Compensation pole 2:

(92)

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Additional Information www.ti.com



Revision History

NOTE: Loop Calculator Tips

A Type I compensation network can be simulated by choosing a Type II compensation (TypeII, Type II isolated with a Zener clamp, Type II isolated with inner loop) and setting RCOMP

equal to RFBT. The crossover frequency depends on the value of CCOMP. Set CHF equal toCCOMP.

12 Additional InformationThe following list contains references to additional information for various topics in this user's guide.1. Mammano, Robert A.; Kollmann, Robert; Fundamentals of Power Supply Design, Chapter 13: Power-

Supply Construction, Texas Instruments, ISBN: 978-0-9985994-0-3 (see Section 3)2. Dinwoodie, L.; Exposing the Inner Behavior of a Quasi-Resonant Flyback Converter, Texas

Instruments Power Supply Design Seminar SEM2000, 2012/2013 (see Section 4)3. Keogh, Bernard; Cohen, Isaac; Flyback transformer design considerations for efficiency and EMI,

Texas Instruments Power Supply Design Seminar SEM2200, 2016/2017 (see Section 5)4. Dinwoodie, Lisa; Design Review: Isolated 50-Watt Flyback Converter Using the UCC3809 Primary

Side Controller and the UC3965 Precision Reference and Error Amplifier (see Section 5)5. Dinwoodie, Lisa; Application Report: UCC38C44 12-V Isolated Bias Supply (see Section 5)6. Betten, John; Power Tips: Calculate an R-C snubber in seven steps (see Section 6)7. Sheehan, R.; Diana, L.; Switch-mode power converter compensation made easy, Texas Instruments

Power Supply Design Seminar SEM2200, 2016/2017 (see Section 11.2)8. Ridley, R.; A More Accurate Current-Mode Control Model, Texas Instruments Power Supply Design

Seminar SEM1400, 2000 (see Section 11.2)9. Compensating the (often missed) Inner and Outer Control Loops using the TL431 by Robert Kollman

and John Betten. Power Electronic Technology Conference, Power Systems World 2002, Chicago (seeSection 11.2)

Revision HistoryNOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Original (November 2017) to A Revision ................................................................................................ Page

• Changed fourth line of Equation 11. .................................................................................................... 7

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https://e2e.ti.com/blogs_/b/powerhouse/archive/2016/05/05/calculate-an-r-c-snubber-in-seven-steps

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