sm_rw3400

RW3400 DIGITAL HOME

ENTERTAINMENT SYSTEM

SERVICE MANUAL

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A GENERAL DESCRIPTION A.1 DMN8652 The DMN8652 accepts video from broadcast TV and other analog video sources, and compresses and formats the video for storage on DVD in industry-standard recordable formats (DVD-RAM, DVD-RW/R, DVD+RW/R).The DMN8652 highly integrated DVD Recorder Processor can control ATAPI disc loaders and read bitstreams using the various media. The device can decode bitstreams and process navigation data of the various formats. For DVD video recording applications, the DMN8652 supports video compression and decompression in compliance with the MPEG-1, MPEG-2, and DV-25 specifications. It also transcodes between DV-25 and MPEG-2. The product supports corresponding audio compression and decompression in compliance with the Dolby Digital CE and MPEG-1 layer 2 specifications. For DVD playback applications, the DMN8652 supports the playback of DVD-Video disks with Dolby Digital 5.1 and DTS audio encoding, DVDAudio disks (MLP), VCD, and SVCD disks. DMN8652 also supports the play back of audio encoded in MP3 and WMA formats, and the display of pictures encoded in JPEG format. General Features:

A/V Encode/Decode Multiformat audio and video encode/decode

Resolutions Horizontal: 720, 704, 640, 544, 480, 352 Vertical: NTSC (480i, 480p) and PAL (576i) 240 and 288 (only at 352 horizontal resolution)

Formats NTSC, PAL, ITUR BT.656/601, SMPTE 250M

Input 8 or 10bit digital video from ITUR BT.656 (parallel D1) sources at 27MHz.

Digital Video

Output

Simultaneous 8-bit SMTPE 293M (ITU-R BT.1358) progressive video output and ITU-R BT.656 interlaced video output (for HDTV and VCR) of the same content. 16-bit YC b C r data (SMPTE 260M).

Baseband composite (M) NTSC or (B,D,G,H,I) PAL analog video.

Separate analog Y/C outputs to support S-video. Analog Video Output

Separate analog component video RGB or SMPTE YPbPr outputs.

Inputs Single stream input, supporting common audio formats, including I2S, with four input channels

Outputs

Dual stream outputs, supporting common audio formats, including I2S: Eight output channels on stream 1 Two output channels on stream 2

Resolutions 16 to 32 bits/sample

Analog Audio Sampling Frequency 32, 44.1, 48, and 96 kHz output

Audio

Digital Audio Sampling Frequency 8 to 192 kHz over IEC958

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Serial IEEE1394 Link, IDC, SPI, two IR blaster, dual UARTs

Parallel ATAPI/DVD&HDD I/O

USB1.1 Host low speed and full speed interface. A single port is available for down stream hub or device connection.

Host 16/32 bit internal host

Graphics 2D, 4 to 32bit RGB, OSD, flicker filter, and video scaler, supporting the following color modes: CLUT4, CLUT8, ARGB4444, ARGB 1555, ARGB 0565, ARGB 8888

System

Encryption/decryption CPRM, CPPM, CSS, 5C (via 1394), Watermark detection

Memory 16-256 Mbytes of SDRAM, SDR or DDR

Controller Onchip, 32 bit wide SDRAM interface, 148.5 Mhz. Memory

Peak Bandwidth 1.2 Gbytes/s

Input Voltages 3.3 V I/O; 1.8 V Core; 2.5 / 3.3 V SDRAM; 3.3 V Isolated Analog

System Clock 13.5 or 27 MHz

Operating Power 3.4 W @ nominal Vdd , six VDACs enabled in Full Power Mode

Package 388 Pin Ball Grid Array (BGA)

Physical

JTAG IEEE 1149.1 compliance for boundary scan testing and board assembly testing

A.2 DIGITAL VIDEO DECODER The TVP5146 or L2146 is a high quality, single-chip digital video decoder that digitizes and decodes all popular base-band analog video formats into digital component video. It supports the A/D conversion of component RGB and YPbPr signals, as well as the A/D conversion and decoding of NTSC, PAL and SECAM composite and S-Video into component YCbCr. Input terminals are properly configured to combination of RGB, YPbPr, CVBS, S-Video video inputs. The main blocks of the device include:

• Robust sync detection for weak and noisy signals as well as VCR • Y/C separation by 2D 5-line (5H) adaptive comb or chroma trap filter • Fast-switch input for instantaneous switching between CVBS and YCbCr/RGB component

video inputs SCART support) • Fast-switch input for synchronous switching between digital RGB overlay an any video inputs • Four 10-bit, 30-MSPS A/D converters with analog pre-processors (Clamp/AGC) • Luminance processor • Chrominance processor • Component processor • Clock/Timing processor and power-down control • Software controlled power saving stand-by modes • Output formatter • I2C host port interface • VBI data processor • Macrovision™ copy protection detection circuit (Type 1, 2 and 3) • 3.3V tolerant digital I/O ports

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A.3 MEMORY Flash Memory: The system host interface controls access to external 16Mbit flash ROM which is used for RISC code. SDRAM Memory: The DMN8652 processor uses a 32-bit memory interface to access to up to 256 Mbytes of SDRAM. Two 16-bit wide 128Mbits(8Mx16) DDR-SDRAMs are used in this product. The interface can run up to 148.5 MHz, at signal levels of 2.5V and 3.3 V. A.4 DRIVE INTERFACES The DMN8652 supports the AT Attachment Packet Interface (ATAPI), Integrated Drive Electronics (IDE), and other parallel and serial port interfaces used by many types of DVD loaders and harddiscs. These interfaces meet the specifications of many DVD loader and harddisc manufacturers. A.5 FRONT PANEL The front panel is based around three interface chips. First of them is VFD and a front panel controller chip. The DMN8652 controls the front panel chip using several control signals, (clock, data, chip select). The infrared remote control signal is received by IR receiver IC an passed directly to the DMN8652 for decoding. Second is USB interface chip and third is MC interface chip. Outputs and Inputs at the RW3400 front panel:

• Left, Right audio outputs. • CVBS-Video. • Memory Card Reader. • USB1.1

A.6 REAR PANEL Outputs and Inputs at the RW3400 rear panel:

• Front Left, Front Right, Rear Left, Rear Right, Center and Subwoofer (active) audio outputs. • Composite, S-Video, and SCART outputs. • Input SCART • Digital Audio Outputs (Optical and Coaxial) • 220-240 V 50Hz AC Power input

The video signals used to provide CVBS and S-Video are generated by the DMN8652’s internal video DAC. Six channel or two channel audio output by the DMN8652 in the form of IDS data streams. The S/PDIF serial stream is also generated by the DMN8652 output by the rear panel. A six channel audio DAC (CS4360) are used for six channel audio output with DMN8652. A two channel audio DAC (CS4340) are used for two channel audio output with DMN8652. B DESCRIPTIONS OF SYSTEM BLOCKS & DMN8652 PIN DESCRIPTION B.1 DMN8652 PIN DESCRIPTION

Ball No. Pin Name Type Module Description

A1 CLKI Clk. In Misc. Clock -- Used with CLKX for crystal input: Used to input LVTTL clock signal if crystal not used.

A2 CLKX Out Misc. Clock -- Used with CLKI for crystal input; Leave open if external clockapplied to CLKI

A3 DAC1_OUT Out Video DAC Analog video DAC output



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A9 TDI In JTAG Test Data In

A10 VO_D[0] lvGPIOExt[0] 1 3state I/O Video I/O Video Output Data






A16 VO_CLK Clk. I/O Video I/O Video Output Clock

A17 VI_CLK[0] Clk. In Video I/O Video input Clock

A18 VI_CLK[1] Clk. In Video I/O Video input Clock

A19 VO2_D[8] 3state I/O Video I/O Video I/O Data

A20 VI_E[1] lvGPIOExt[29] 1 3state I/O Video I/O Video Input Enable

A21 VI_VSYNC[0] PEC In Video I/O Video Input Vertical Sync

A22 VI_D[4] In Video I/O Video Input Data

A23 AO_IEC958 Out Audio I/O IEC958 Interface Output

A24 AI_MCLKO Clk Out Audio I/O Audio Master Input Clock output

A25 AO_MCLKO Clk Out Audio I/O Audio Master Output Clock output

A26 VI_D[9] In Video I/O Video Input Data

B1 XtalVdd Power Pwr/Gnd Quiet Xtal Vdd

B2 XtalVss Power Pwr/Gnd Quiet Xtal Vss

B3 Agnd_1 N/A Pwr/Gnd Analog Ground

B4 DAC2_OUTB Out Video DAC Current return path of the video DAC output

B5 DAC4_OUTB Out Video DAC Current return path of the video DAC output

B6 DAC_DVSS_1 Power Pwr/Gnd DAC ground

B7 TDO Out JTAG Test Data Out

B8 TCK Clk. In JTAG Test Clock

B9 VO_HSYNC 3state I/O Video I/O Video Output Horizontal Sync

B10 VO_D[1] lvGPIOExt[1] 1 3state I/O Video I/O Video Output Data





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B15 VO_E lvGPIOExt[30] 1 3state I/O Video I/O Video Output Enable

B16 VO2_D[0] 3state I/O In Video I/O Video I/O Data



B19 VI_D[1] In Video I/O Video Input Data

B20 VI_E[0] In Video I/O Video Input Enable




B24 AI_MCLKI GPIOExt[32] CS[8]

Clk In Audio I/O Audio Master Input Clock input

B25 AO_MCLKI GPIOExt[33] CS[9]

Clk. In Audio I/O Audio Master Output Clock input


C1 Vref In Pwr/Gnd Reference Resistor

C2 RefVss Analog ground Pwr/Gnd Reference ground

C3 Agnd_2 N/A Pwr/Gnd Analog Ground



C6 DAC_VDD_0 Power Pwr/Gnd DAC power

C7 TRST In JTAG Test Reset

C8 VO_VSYNC 3state I/O Video I/O Video Output Vertical Sync

C9 RSTO Out Misc. Reset Out

C10 VO_ACTIVE 3state I/O Video I/O Video Output Active

C11 VO_D[4] lvGPIOExt[4] 1 3state I/O Video I/O Video Output Data





C16 VO2_D[1] 3state I/O Video I/O Video I/O Data



C19 VI_D[0] In Video I/O Video Input Data

C20 VI_VSYNC[1] lvGPIOExt[45] 1 3state I/O Video I/O Video Input Vertical Sync

C21 GROUND N/A Pwr/Gnd Circuit ground

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C22 Vdd25_01 N/A Pwr/Gnd Digital 2.5 V Power

C23 GROUND N/A Pwr/Gnd Circuit ground



C26 AI_FSYNC I/O Audio I/O Start or end of the next stream 1 input sample or frame

D1 RefVdd Analog Power Pwr/Gnd Reference Vdd

D2 Avdd_2 N/A Pwr/Gnd Analog Vdd




D6 DAC_VDD_3 Power Pwr/Gnd DAC power

D7 DAC_DVDD Power Pwr/Gnd DAC Digital Vdd

D8 TMS In JTAG Test Mode Select

D9 EPD Out Misc. External Power Down

D10 Reserved, tie to Vdd

D11 Vdd_00 N/A Pwr/Gnd Digital 3.3 V Power



D14 Vddp_01 N/A Pwr/Gnd Digital 3.3 V Power


D16 VO2_D[2] 3state I/O Video I/O Video I/O Data





D21 Bias_5V00 Pwr/Gnd

D22 SDRAM_VREF In SDRAM Reference voltage for SSTL

D23 Vdd25_00 N/A Pwr/Gnd Digital 2.5 V Power

D24 AI__SCLK Clk. I/O Audio I/O Serial audio bit clock for audio input stream 1

D25 A2_FSYNC GPIOExt[34] 3state I/O Audio I/O Start or end of the next stream 2 input and output

sample or frame

D26 AI_D[0] In Audio I/O Audio Stream 1 Input Data

E1 Dminus_0 3state I/O Analog USB transceiver D port 0

E2 Dplus_0 3state I/O Analog USB transceiver D+ port 0

E3 USB_Agnd_0 N/A Analog USB Analog Ground

E4 USB_Avdd_0 N/A Analog USB Analog Power

E23 A2_SCLK GPIOExt[31]

Clk. I/O 3state I/O Audio I/O Serial audio bit clock for audio input and output

stream 2

E24 AI_D[1] GPIO[6] 3state I/O Audio I/O Audio Stream 1 Input Data

E25 AO_FSYNC Out Audio I/O Start or end of the next stream 1 output sample or frame

E26 AI2_D GPIO[7] 3state I/O Audio I/O Audio Stream 2 Input Data

F1 Dminus_1 3state I/O Analog USB transceiver D port 1

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F2 Dplus_1 3state I/O Analog USB transceiver D+ port 1

F3 USB_Agnd_1 N/A Analog USB Analog Ground

F4 USB_Avdd_1 N/A Analog USB Analog Power

F23 Vdd_03 N/A Pwr/Gnd Digital 3.3 V Power

F24 AO_SCLK Clk. Out Audio I/O Serial audio bit clock for audio output stream 1

F25 AO2_D[0] Out Audio I/O Audio Stream 2 Output Data

F26 AO_D[2] Out Audio I/O Audio Stream 1 Output Data

G1 Host PO_0 Out Analog Power enable for the external USB power management chips

G2 Host OC_0 In Analog Over current status pins from the external USB power management chips

G3 Host PO_1 GPIOExt[43] 3state I/O Analog Power enable for the external USB power

management chips

G4 Host OC_1 GPIOExt[44] 3state I/O Analog Over current status pins from the external USB power

management chips

G23 AO_D[1] Out Audio I/O Audio Stream 1 Output Data



G26 SDRAM_DQ[25] I/O SDRAM SDRAM Read / Write Data

H1 CLK0_DAC GPIOExt[35] 3state I/O Misc. Output of the internal 13.5 MHz crystal oscillator

H2 USB_48MHZ GPIOExt[36] 3state I/O Misc. External USB 48 MHz Clock

H3 1394_LINK_ON In 1394 Occurrence of a linkon event

H4 BYPASS_PLL In Misc. Bypasses the PLL used to generate the internal processing clock

H23 SDRAM_DQ[24] I/O SDRAM SDRAM Read / Write Data



H26 SDRAM_DQS[3] I/O SDRAM SDRAM Data Strobe

J1 1394_PHY_DATA[5] 3state I/O 1394 Phylink data bus



J4 1394_PHY_CTL[0] I/O 1394 Phylink control bus

J23 SDRAM_DQ[30] I/O SDRAM SDRAM Read / Write Data




K1 1394_PHY_CLK Clk. In 1394 49.152 MHz clock supplied by the PHY device

K2 1394_PHY_DATA[7] 3state I/O 1394 Phylink data bus

K3 1394_PHY_DATA[6] 3state I/O 1394 Phylink data bus

K4 Vdd_08 N/A Pwr/Gnd Digital 3.3 V Power

K23 SDRAM_DQM[3] Out SDRAM SDRAM Data Mask (Byte Enables)

K24 SDRAM_DQ[23] I/O SDRAM SDRAM Read / Write Data



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L1 1394_LPS Out 1394 Link Power Status

L2 1394_LREQ Out 1394 Link Request

L3 1394_PHY_CTL[1] I/O 1394 Phylink control bus

L4 1394_PHY_DATA[1] 3state I/O 1394 Phylink data bus

L11 GROUND N/A Pwr/Gnd Circuit ground






L23 SDRAM_DQ[20] I/O SDRAM SDRAM Read / Write Data

L24 SDRAM_DQS[2] I/O SDRAM SDRAM Data Strobe



M1 ATAPI_DATA[8] 3state I/O ATAPI Bidirectional ATAPI data bus

M2 ATAPI_DATA[7] I/O ATAPI Bidirectional ATAPI data bus

M3 1394_PHY_DATA[3] 3state I/O 1394 Phylink data bus

M4 1394_PHY_DATA[2] 3state I/O 1394 Phylink data bus

M11 GROUND N/A Pwr/Gnd Circuit ground






M23 Vdd25_02 N/A Pwr/Gnd Digital 2.5 V Power

M24 SDRAM_DQ[17] I/O SDRAM SDRAM Read / Write Data

M25 SDRAM_DQ[16] I/O SDRAM SDRAM Read / Write Data

M26 SDRAM_DQM[2] Out SDRAM SDRAM Data Mask (Byte Enables)

N1 ATAPI_DATA[9] 3state I/O ATAPI Bidirectional ATAPI data bus

N2 ATAPI_DATA[6] I/O ATAPI Bidirectional ATAPI data bus

N3 ATAPI_DATA[5] I/O ATAPI Bidirectional ATAPI data bus

N4 Vdd_09 N/A Pwr/Gnd Digital 3.3 V Power

N11 GROUND N/A Pwr/Gnd Circuit ground






N23 SDRAM_CLK[0] DInff. Out SDRAM SDRAM CLock -- buffered versions of the internal DMN8652 clock

N24 Vdd25_03 N/A Pwr/Gnd Digital 2.5 V Power

N25 SDRAM_DQ[15] I/O SDRAM SDRAM Read / Write Data

N26 SDRAM_DQM[1] Out SDRAM SDRAM Data Mask (Byte Enables)

P1 ATAPI_ADDR[4] Out ATAPI ATAPI device register address

P2 ATAPI_DATA[10] 3state I/O ATAPI Bidirectional ATAPI data bus

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P3 ATAPI_DATA[4] 2 I/O ATAPI Bidirectional ATAPI data bus

P4 Vddp_08A N/A Pwr/Gnd Digital 3.3 V Power

P11 GROUND N/A Pwr/Gnd Circuit ground






P23 SDRAM_CLK[0] DInff. Out SDRAM SDRAM CLock -- buffered versions of the internal DMN8652 clock

P24 Vdd25_04 N/A Pwr/Gnd Digital 2.5 V Power

P25 SDRAM_DQ[13] I/O SDRAM SDRAM Read / Write Data

P26 SDRAM_DQ[14] I/O SDRAM SDRAM Read / Write Data

R1 ATAPI_IORDY In ATAPI ATAPI device IO ready

R2 ATAPI_DATA[3] I/O ATAPI Bidirectional ATAPI data bus

R3 ATAPI_DATA[11] 3state I/O ATAPI Bidirectional ATAPI data bus

R4 Vddp_09 N/A Pwr/Gnd Digital 3.3 V Power

R11 GROUND N/A Pwr/Gnd Circuit ground






R23 SDRAM_CLK[1] Diff. Out SDRAM SDRAM CLock -- buffered versions of the internal DMN8652 clock

R24 Vdd25_05 N/A Pwr/Gnd Digital 2.5 V Power

R25 SDRAM_DQS[1] I/O SDRAM SDRAM Data Strobe

R26 SDRAM_DQ[12] I/O SDRAM SDRAM Read / Write Data

T1 ATAPI_DATA[2] I/O ATAPI Bidirectional ATAPI data bus

T2 ATAPI_DATA[12] 3state I/O ATAPI Bidirectional ATAPI data bus

T3 ATAPI_DIOW Out ATAPI ATAPI I/O write request

T4 Vddp_10 N/A Pwr/Gnd Digital 3.3 V Power

T11 GROUND N/A Pwr/Gnd Circuit ground






T23 SDRAM_CLK[1] Diff. Out SDRAM SDRAM CLock -- buffered versions of the internal DMN8652 clock

T24 Vdd25_06 N/A Pwr/Gnd Digital 2.5 V Power

T25 SDRAM_DQ[10] I/O SDRAM SDRAM Read / Write Data

T26 SDRAM_DQ[11] I/O SDRAM SDRAM Read / Write Data

U1 ATAPI_DATA[1] I/O ATAPI Bidirectional ATAPI data bus

U2 ATAPI_DATA[13] 3state I/O ATAPI Bidirectional ATAPI data bus

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U3 ATAPI_DATA[0] I/O ATAPI Bidirectional ATAPI data bus

U4 ATAPI_ADDR[3] Out ATAPI ATAPI device register address

U23 Vdd25_08 N/A Pwr/Gnd Digital 2.5 V Power

U24 SDRAM_DQM[0] Out SDRAM SDRAM Data Mask (Byte Enables)

U25 SDRAM_DQ[8] I/O SDRAM SDRAM Read / Write Data

U26 SDRAM_DQ[9] I/O SDRAM SDRAM Read / Write Data

V1 ATAPI_DMAACK Out ATAPI ATAPI DMA acknowledgement

V2 ATAPI_DATA[14] 3state I/O ATAPI Bidirectional ATAPI data bus

V3 ATAPI_ADDR[2] Out ATAPI ATAPI 2 device register address

V4 ATAPI_DMARQ In ATAPI ATAPI Device DMA request

V23 SDRAM_DQ[0] I/O SDRAM SDRAM Read / Write Data




W1 ATAPI_ADDR[1] Out ATAPI ATAPI device register address

W2 ATAPI_INTRQ In ATAPI ATAPI Device interrupt request

W3 ATAPI_DIOR Out ATAPI ATAPI I/O read request

W4 ATAPI_DATA[15] 3state I/O ATAPI Bidirectional ATAPI data bus

W23 SDRAM_CKE Out SDRAM SDRAM Clock Enable

W24 SDRAM_DQ[1] I/O SDRAM SDRAM Read / Write Data

W25 SDRAM_DQS[0] I/O SDRAM SDRAM Data Strobe

W26 SDRAM_DQ[5] I/O SDRAM SDRAM Read / Write Data

Y1 ATAPI_RESET Out ATAPI Reset out to connected ATAPI devices

Y2 ATAPI_ADDR[0] Out ATAPI ATAPI device register address

Y3 ATAPI2_DATA[0] I/O ATAPI Bidirectional ATAPI 2 data bus

Y4 ATAPI2_DATA[2] I/O ATAPI Bidirectional ATAPI 2 data bus

Y23 SDRAM_A[16] 3 Out SDRAM SDRAM Address, Bank Select, or Chip Select

Y24 SDRAM_RAS Out SDRAM SDRAM Row Address Strobe

Y25 SDRAM_DQ[2] I/O SDRAM SDRAM Read / Write Data

Y26 SDRAM_DQ[3] I/O SDRAM SDRAM Read / Write Data

AA1 ATAPI2_DATA[1] I/O ATAPI Bidirectional ATAPI 2 data bus



AA4 Vdd_14 N/A Pwr/Gnd Digital 3.3 V Power

AA23 Vdd_30 N/A Pwr/Gnd Digital 3.3 V Power

AA24 SDRAM_A[2] Out SDRAM SDRAM Address

AA25 SDRAM_CAS Out SDRAM SDRAM Column Address Strobe

AA26 SDRAM_WE Out SDRAM SDRAM Write Enable

AB1 ATAPI2_DATA[4] I/O ATAPI Bidirectional ATAPI 2 data bus

AB2 ATAPI2_DATA[6] I/O ATAPI Bidirectional ATAPI 2 data bus

AB3 ATAPI2_DATA[8] 3state I/O ATAPI Bidirectional ATAPI 2 data bus

AB4 ATAPI2_DATA[11] 3state I/O ATAPI Bidirectional ATAPI 2 data bus

AB23 SDRAM_A[1] Out SDRAM SDRAM Address

AB24 SDRAM_A[4] Out SDRAM SDRAM Address

AB25 SDRAM_A[15] 3 Out SDRAM SDRAM Address, Bank Select, or Chip Select

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AB26 SDRAM_A[17] 3 Out SDRAM SDRAM Address, Bank Select, or Chip Select

AC1 ATAPI2_DATA[7] I/O ATAPI Bidirectional ATAPI 2 data bus

AC2 ATAPI2_DATA[9] 3state I/O ATAPI Bidirectional ATAPI 2 data bus

AC3 ATAPI2_DATA[12] 3state I/O ATAPI Bidirectional ATAPI 2 data bus

AC4 ATAPI2_ADDR[2] Out ATAPI ATAPI 2 device register address

AC5 ATAPI2_DMARQ In ATAPI ATAPI 2 Device DMA request

AC6 Vdd_15 N/A Pwr/Gnd Digital 3.3 V Power

AC7 Bias_5V01 Pwr/Gnd

AC8 HMST_ADDRHI[3] MAddress[25] Out Host Infc Upper five Maddress bits [26:22]

AC9 HMST_ADDRLO[2] MAddress[3] Out Host Infc Lower five Maddress bits [5:1]

AC10 HMST_WAIT Out Host Infc Host Wait

AC11 HMST_AddrData[12] MAddress[18] MData[12]

3state I/O 3state I/O Host Infc Host MAddress [21:6] during address cycles;

Host MData [15:0]during data cycles

AC12 Vddp_19A N/A Pwr/Gnd Digital 3.3 V Power

AC13 Vddp_19 N/A Pwr/Gnd Digital 3.3 V Power



AC16 HMST_AddrData[4] MAddress[10] MData[4]

3state I/O 3state I/O

Host Infc Host MAddress [21:6] during address cycles; Host MData [15:0] during data cycles

AC17 HMST_UDS HMST_UWE Out Out Host Infc Host Upper Data Strobe

AC18 SIO_SPI_CS[2] CS[10] Out Serial I/O SPI chip select

AC19 SIO_SDA I/O Serial I/O IDC Data

AC20 SIO_UART1_RX In Serial I/O UART1 receive

AC21 Vdd_23 N/A Pwr/Gnd Digital 3.3 V Power

AC22 SIO_UART2_CTS In Serial I/O UART2 clear to send

AC23 SDRAM_A[8] Out SDRAM SDRAM Address




AD1 ATAPI2_DATA[10] 3state I/O ATAPI Bidirectional ATAPI 2 data bus

AD2 ATAPI2_DATA[13] 3state I/O ATAPI Bidirectional ATAPI 2 data bus

AD3 ATAPI2_ADDR[1] Out ATAPI ATAPI 2 device register address

AD4 ATAPI2_DIOW Out ATAPI ATAPI 2 I/O write request

AD5 ATAPI2_DIOR Out ATAPI ATAPI 2 I/O read request

AD6 ATAPI2_RESET Out ATAPI Reset out to connected ATAPI 2 devices

AD7 HMST_ADDRHI[1] MAddress[23] Out Host Infc Upper five Maddress bits [26:22]

AD8 HMST_GPIO[0] I/O Host Infc

AD9 HMST_ADDRLO[3] MAddress[4] Out Host Infc Lower five Maddress bits [5:1]

AD10 HSMT_DTACK Out Host Infc Data Transfer Acknowledge

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AD11 HMST_AddrData[15] MAddress[21] MData[15]

3state I/O Host Infc Host MAddress [21:6] during address cycles; Host MData [15:0] during data cycles

AD12 HMST_CS0_8BIT In Host Infc Slave Chip Select / Master 8bit transfer chip select





AD15 HMST_AddrData[2] MAddress[8] MData[2] 3state I/O Host Infc Host MAddress [21:6] during address cycles;

Host MData [15:0] during data cycles



AD17 HMST_AddrData[0] MAddress[6] MData[0] 3state I/O Host Infc Host MAddress [21:6] during address cycles;


AD18 SIO_SPI_CLK Out Serial I/O SPI clock

AD19 SIO_IRTX1 GPIOExt[40] CS7 3state I/O Serial I/O IR transmit 1

AD20 SPI_CS[3] CS[11] Out Serial I/O SPI chip select

AD21 SIO_SCL I/O Serial I/O IDC Clock

AD22 SIO_SPI_MISO In Serial I/O SPI master in slave out.

AD23 SDRAM_A[14] 3 Out SDRAM SDRAM Address, Bank Select, or Chip Select

AD24 SDRAM_A[10] Out SDRAM SDRAM Address



AE1 ATAPI2_DATA[14] 3state I/O ATAPI Bidirectional ATAPI 2 data bus

AE2 ATAPI2_ADDR[0] Out ATAPI ATAPI 2 device register address

AE3 ATAPI2_ADDR[4] Out ATAPI ATAPI 2 device register address

AE4 ATAPI2_IORDY In ATAPI ATAPI 2 device IO ready

AE5 HMST_CS[4] 3state I/O Host Infc Master Chip Select 4

AE6 HMST_ADDRHI[4] MAddress[26] Out Host Infc Upper five Maddress bits [26:22]

AE7 HMST_ADDRHI[0] MAddress[22] Out Host Infc Upper five Maddress bits [26:22]

AE8 HMST_ADDRLO[1] MAddress[2] Out Host Infc Lower five Maddress bits [5:1]

AE9 HMST_GPIO[3] 3state I/O Host Infc Slave address bus


AE11 HMST_AddrData[9] MAddress[15] MData[9]




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AE16 HMST_AddrData[1] MAddress[7] MData[1] 3state I/O Host Infc Host MAddress [21:6] during address cycles;


AE17 HMST_AddrData[3] MAddress[9] MData[3] 3state I/O Host Infc Host MAddress [21:6] during address cycles;


AE18 HMST_RST In Host Infc Host Reset

AE19 SIO_IRRX GPIOExt[39] CS6 3state I/O Serial I/O IR receive input

AE20 SIO_UART1_CTS GPIOExt[42] 3state I/O Serial I/O UART1 clear to send

AE21 SIO_SPI_CS[1] GPIOExt[25] 3state I/O Serial I/O SPI chip select

AE22 SIO_SPI_MOSI Out Serial I/O SPI master out slave in

AE23 SIO_UART2_TX GPIOExt[38] 3state I/O Serial I/O UART2 transmit

AE24 SIO_UART2_RTS Out Serial I/O UART2 request to send.

AE25 SDRAM_A[7] Out SDRAM SDRAM Address

AE26 SDRAM_A[11] Out SDRAM SDRAM Address

AF1 ATAPI2_DATA[15] 3state I/O ATAPI Bidirectional ATAPI 2 data bus

AF2 ATAPI2_ADDR[3] Out ATAPI ATAPI 2 device register address

AF3 ATAPI2_DMAACK Out ATAPI ATAPI 2 DMA acknowledgement

AF4 ATAPI2_INTRQ In ATAPI ATAPI 2 Device interrupt request

AF5 HMST_CS[5] 3state I/O Host Infc Master Chip Select 5

AF6 HMST_ADDRHI[2] MAddress[24] Out Host Infc Upper five Maddress bits [26:22]

AF7 HMST_ADDRLO[4] MAddress[5] Out Host Infc Lower five Maddress bits [5:1]

AF8 HMST_ADDRLO[0] MAddress[1] Out Host Infc Lower five Maddress bits [5:1]

AF9 PCMCIA_IOW GPIO[4] 3state I/O Host Infc PCMCIA I/O Write

AF10 PCMCIA_IOR GPIO[5] 3state I/O Host Infc PCMCIA I/O Read

AF11 HMST_AddrData[13] MAddress[19] MData[13]


AF12 HMST_AddrData[11] MAddress[17] MData[11]

3state I/O 3state I/O Host Infc Host MAddress [21:6] during address cycles;

Host MData [15:0]during data cycles

AF13 HMST_LDS HMST_OE In Out Host Infc Lower data strobe

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AF14 HMST_WR LWE In Out Host Infc Write enable

AF15 HMST_ALE Out Host Infc Master address latch enable





AF20 SIO_IRTX2 3state I/O Serial I/O IR transmit 2

AF21 SIO_SPI_CS[0] GPIOExt[24] 3state I/O Serial I/O SPI chip select

AF22 SIO_UART2_RX GPIOExt[37] 3state I/O Serial I/O UART2 receive

AF23 SIO_UART1_RTS GPIOExt[41] 3state I/O Serial I/O UART1 request to send

AF24 SIO_UART1_TX Out Serial I/O UART1 transmit

AF25 SDRAM_A[9] Out SDRAM SDRAM Address

AF26 SDRAM_A[13] Out SDRAM SDRAM Address 1. lvGPIO are GPIO that are 3.3 volt tolerance only. 2. ATAPI_DATA[4]] can be used as a IEC958 bypass input (bypassed and sent out to AO_IEC958) 3. For a one slot SDRAM system, SDRAM_A[17] should be connected to the SDRAM chip select. For a two slot system, both SDRAM_A[17] and SDRAM_A[16] are used as chip selects. The SDRAM address pins should be mapped to SDRAM chip as follows: SDRAM_A[17] = CS0 SDRAM_A[16] = CS1 SDRAM_A[15] = B1 SDRAM_A[14] = B0

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B.2 SYSTEM BLOCK DIAGRAM The block diagram of digital board is shown in the following figure:

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The block diagram of analog board is shown in the following figure:

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B.3 AUDIO OUTPUT The DMN-8652 can receive and transmit two separate streams of 16- to 32-bit audio data via the serial audio interface. Common audio formats, including inter-device serial (IDS), are supported. Four channels of audio input and eight channels of audio output are supported on stream 1. Two channels of audio input and two channels of audio output are supported on stream 2. Each stream has separate input and output clocking. An IEC-958 encoded audio output, synchronized to output stream 1, is also provided. Internal input and output audio clocks can be generated from the internal system clock. Four channels of serial audio data are clocked in by the two AI_D pins, and up to eight channels of serial audio data are clocked out of the four AO_D pins by the clock on the AO_SCLK pin. With two samples/frame, channel 2n and 2n + 1 use AudioIn/Out[n]. With one sample/frame, channel n uses AudioIn/Out[n]. AI_FSYNC determines the start or end of the next stream input sample or frame as specified by the stream frame format. The interface carries either PCM audio samples (mono or stereo) or compressed audio bitstreams (AC3 or MPEG). The sample rate of audio samples carried by this interface can be 32, 44.1, 48 or 96 kHz. The width of audio samples can be up to 24 bits. The DMN8652 also provides digital output in S/PDIF format. The board supports both optical and coaxial S/PDIF outputs. B.4 AUDIO DACS The IDS data and clock lines can be connected directly to one or more audio DAC to generate analog audio output. The six-channel DAC is an CS4360. The two-channel DAC is CS4340. The outputs of the DAC are differential, not single ended so a buffering circuit is required. The buffer circuits use op-amps to perform the low-pass filtering and the buffering. B.5 AUDIO ADC The CS5340 ADC converts analog audio signals to digital and passes trough I²S interface to DMN8652. It performs sampling, analog to digital conversion, and anti-alias filtering, generating 24-bit values for both left and right inputs in serial form at sample rates up to 200 kHz per channel. The CS5340 uses a 5th-order, multi-bit Delta-Sigma modulator followed by digital filtering and decimation, which removes the need for an external anti-alias filter. B.6 VIDEO INTERFACE Video Output The video output channel supports a separate PIP video layer and a separate OSD/graphics overlay with 4-bit, 8-bit, 16-bit or 32-bit pixel formats and optional two-tap flicker filter. Two programmable OSD windows are output for each field, without software intervention. For DMN-8652 processor, the maximum output rate is 74.25 MHz (SMPTE 250M). The maximum OSD pixel rate with flicker filtering and 32-bit pixels is 37.125 MHz. The DMN-8652 processor output values are optionally passed through an interpolating 4-tap, 8-phase horizontal filter. Video Input The video input channel captures 8- or 10-bit digital video from ITU-R BT.656 (parallel D1) or video decoder chips such as the TVP5146.Two programmable rectangular windows are captured from each field without software intervention. This allows for VITC and closed-caption capture. Additional windows can be captured by loading a new capture window into the input channel at the completion of each window. In the DMN8652, 10-bit input values are dithered down to 8-bit values and are optionally passed through an 8-tap, 8-phase horizontal filter for resampling and noise reduction. Double buffered luma and chroma buffers hold the filtered values. The DMA transfer captures up to one entire field between video interrupts. Luma information and chroma information are stored separately in SDRAM. Video Interface Pins The functions of the various Video I/O signal pins depend on the specific configuration of the DMN8652 Video Channels. The frequency of VO_CLK and VI_CLK varies from 27MHz to 74.25 MHz.

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B.7 DDR SDRAM MEMORY The DMN8652 device utilizes Synchronous DRAM (SDRAM) for the external memory bank due to SDRAM’s flexibility and high sustainable bandwidth. The interface supports Double Data Rate (DDR) SDRAM for high performance applications. The SDRAM clock frequency for SDR and DDR devices ranges from 108 to 148.5 MHz. The address and control I/O signals can drive up to four loads, while the data (DQ, DQS, DQM, and the clock) signal can drive up to two loads. All I/Os are PVT compensated to minimize output delay variations. RAS and CAS latency and cycle time are programmable, so that designers can use SDRAMs from different vendors at different speeds. The SDRAM devices are DDR SDRAM 16M x 16b which are used in the system. Since DDRs use a Stub-Series Terminated Logic (SSTL) interface to easily allow stacking, they are quite power-hungry and should be used only for high-performance, non-power critical applications. For DDRs, all control signals change only at the rising edge of the clock, but data and data mask can change on both rising and falling edges of the clock. B.8 FLASH MEMORY 32MBits Flash size is required for DMN8652.

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B.9 ATA/IDE LOADER&HDD INTERFACE The primary and secondary AT Attachment Packet Interface (ATAPI) is a standard interface with a 16-bit data bus, which is used to connect devices such as hard disks, CD/DVD ROMs, and DVD RAMs. All operations are initiated by reading/writing a set of ATAPI device registers through programmed input/output (PIO) data transfer. ATAPI has DMA commands for transferring long data. The peripheral I/O supports these transfers with the DVDctl (ATAPI control register). The ATAP interface supports the following operations:

• Register read • Register write • DMA read • DMA write

The Register read and write operations are used to configure a set of ATAPI device registers. The DMA read and write operations are needed for transferring long sector data. The ATAPI register address is defined by the output pins CS0, CS1, DA2, DA1, and DA0, where CS0 is the most significant bit. The ATAPI read cycle starts when the ATAPI Interface receives the ATAPI_RD command from the host. The ATAPI Interface subsequently puts the register address on the address bus and asserts the ATAPI_DIOR signal t1 time later. The 16-bit data (AtapiIOCS16 signal is always low) from the ATAPI device is latched by the ATAPI Interface during the rising edge of the ATAPI_DIOR signal. The wait cycle can be generated by the ATAPI device driving the ATAPI_IORDY signal low during the read cycle. The ATAPI device must drive the ATAPI_IORDY signal low before time tA to initiate a wait cycle. During the wait cycle, the ATAPI Interface keeps the register address and the ATAPI_DIOR signal asserted until the ATAPI_IORDY signal becomes high. The ATAPI write cycle starts when the ATAPI Interface receives the ATAPI_WR command from the host. The ATAPI Interface follows by placing the register address on the address bus and asserting the ATAPI_DIOW signal time t1 later. The ATAPI device can also initiate the wait cycle by driving the ATAPI_IORDY signal low before time tA. During the wait cycle, the ATAPI Interface keeps the register address, write the data, and the ATAPI_DIOW signal asserted until the ATAPI_IORDY signal becomes high. Note: The decoder board supports the standard ATAPI electrical connections, but the software protocol within the drive is not always supported according to ATAPI specifications. Custom software may need to be developed and tested to support ATAPI drives from different manufacturers. B.11 FRONT PANEL The VFD controller is a PTC PT6315. This controller is not a processor, but does include a simple state machine which scans the VFD and reads the front panel button matrix. The 6315 also includes RAM so it can store the current state of all the VFD icons and segments. Therefore, the 6315 need only be accessed when the VFD status changes and when the button status is read. The DMN8652 can control this chip directly using PIO pins or can allow the front panel PIC to control the VFD. There are video& audio connectors, USB&MC sockets on the user interface board. AU9368 is the electrical interface chip for USB1.1. B.12 MISCELLANEOUS FUNCTIONS Reset Circuitry A reset ic is used to provide the power-on-reset. Vth should be smaller than 4.65. B.13 CONNECTORS ATAPI Drive Standard Connector The I/O connector is a 40-pin connector as shown in figure A.1, with pin assignments as shown in table A.1. The connector shall be keyed to prevent the possibility of installing it upside down. A key is provided by the removal of pin 20. The corresponding pin on the cable connector shall be plugged.

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The cable plug, not the receptacle, governs the pin locations. The way in which the receptacle is mounted on the printed circuit board affects the pin positions, and pin 1 shall remain in the same relative position. This means the pin numbers of the receptacle may not reflect the conductor number of the plug. The header receptacle is not polarized, and all the signals are relative to pin 20, which is keyed. By using the plug positions as primary, a straight cable can connect devices. As shown in figure A.1, conductor 1 on pin 1 of the plug shall be in the same relative position no matter what the receptacle numbering looks like. If receptacle numbering was followed, the cable would have to twist 180 degrees between a device with top-mounted receptacles, and a device with bottom mounted receptacles.

Recommended part numbers for the mating connector and cable are shown below, but equivalent parts may be used.

Connector (40 pin) 3M 3417-7000 or equivalent Strain relief 3M 3448-2040 or equivalent Flat cable (stranded 28 AWG) 3M 3365-40 or equivalent Flat cable (stranded 28 AWG) 3M 3517-40 (shielded) or equivalent

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SCART Connectors Pinout of the scart connectors: SCART1 SCART2

1 Audio Right Out 1 Audio Right Out 2 Audio Right In 2 Audio Right In 3 Audio Left / Mono Out 3 Audio Left / Mono Out 4 Audio Gnd 4 Audio Gnd 5 Blue Gnd 5 Blue Gnd 6 Audio Left / Mono In 6 Audio Left / Mono In 7 Blue Out 7 Blue In 8 Control Voltage 8 Control Voltage 9 Green Gnd 9 Green Gnd 10 Comms Data 2(TVLINK) 10 Comms Data 2(Not connected) 11 Green Out 11 Green In 12 Comms Data 1(Not connected) 12 Comms Data 1(Not connected) 13 Red Gnd 13 Red Gnd 14 Comms Data Gnd 14 Comms Data Gnd 15 Red Out 15 Red In 16 Fast Blanking 16 Fast Blanking 17 Video Gnd 17 Video Gnd 18 Fast Blanking Gnd 18 Fast Blanking Gnd 19 Composite Video Out 19 Composite Video Out 20 Composite Video In 20 Composite Video In 21 Shield 21 Shield

Some cheaper SCART cables use unshielded wires, which is just about acceptable for short cable lengths. For longer lengths, shielded coaxial cable become essential. Scart Signals: Audio signals 0.5V RMS, <1K output impedance, >10K input impedance. Red, Green, Blue 0.7Vpp ±2dB, 75R input and output impedance. Note that the Red connection (pin 20) can alternatively carry the S-VHS Chrominance signal, which is 0.3V. Composite Video / CSync 1Vpp including sync, ±2dB, 75R input and output impedance.Bandwidth = 25Hz to 4.8MHz for normal TV Video de-emphasis to CCIR 405.1 (625-line TV) Fast Blanking 75R input and output impedance. This control voltage allows devices to over-ride the composite video input with RGB inputs, for example when inserting closed caption text. It is called fast because this can be done at the same speeds as other video signals, which is why it requires the same 75R impedances. 0 to 0.4V: TV is driven by the composite video input signal (pin 19). Left unconnected, it is pulled to 0V by its 75R termination. 1V to 3V: the TV is driven by the signals Red, Green, Blue and composite sync. The latter is sent to the TV on pin 19. This signal is useful when using a TV to display the RGB output of devices such as home computers with TV-compatible frame rates. Tying the signal to 5V via 100R forms a potential divider with the 75R termination, holding the signal at around 2V. Alternatively, if a TTL level (0 to 5V) negative sync pulse is available, this will be high during the display periods, so this can drive the blanking signal via a suitable resistor. Control Voltage 0 to 2V = TV, Normal. 5 to 8V = TV wide screen 9.5 to 12V = AV mode C CIRCUIT DESCRIPTION C.1 POWER SUPPLY & ANALOG BOARD Socket PL100 is the 220VAC input.

• 3.15A fuse F100 is used to protect the device against short circuit and unexpected overloads.

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• Line filter and capacitors L100, L101, L102, C100 and C101 are used to block the parasitic coming from the mains. They also prevent the noise, produced in the circuit, from being injected to the line.

• Voltage is rectified by diodes D100, D101, D102 and D103. Using capacitor C105 (47µf) a DC voltage is produced. (310-320VDC).

• The current in the primary side of the transformer TR100 comes to the SMPS IC (IC304 ICE2A165). The SMPS IC has a eight-pin DIP-8 package and an external MOSFET with a cooler is mounted on it. It has a built-in oscillator, overcurrent and overvoltage protection circuitry and runs at 100kHz. It starts with the current from the primary side of the transformer and follows the current from the feedback winding.

• Feedback current is deteceted by optocoupler IC101. Depending on the control current coming from the secondary side, SMPS IC keeps the output voltage constant by controlling the duty cycle of the ~30kHz signal (PWM) at the primary side of the transformer.

• Voltages on the secondary side of the transformer are as follows: +33V, +5V, +8V, +15V and -22V.

• Using the output of the D323, a photo diode inside of the IC101 generates feedback signal by using optocoupler's phototransistor. This phototransistor adjusts the control voltage at the IC304 pin2. The voltage at this pin effects the PWM output frequency on the IC304 pin4 and pin5. And finally output voltages reach their correct values by this way.

• –22 Volts is used to feed the VFD (Vacuum Fluorescent Display) driver IC on the front panel. • Socket PL108 is connector of cooler fan which is under the HDD. The cooler fan is controlled

by IC211(MCU) on the analog board. • Analog board is the interface between the digital board and the input/output signals. On the

analog board, there is a IF-PLL demodulator (IC204 TDA9885), a multi-standard sound processor (IC110 MSP3417), a video switch (IC206 STV6412) and an audio DAC (IC104 CS4360 for 6ch, IC107 CS4340 for 2ch).

• There are three op-amp ICs IC101, IC102 and IC103 for Front Left, Front Right, Rear Left, Rear Right, Center and Subwoofer outputs after DAC IC.

C.2 FRONT PANEL

• All the functions on the front panel are controlled by DMN8652 on the mainboard. Key scanning and IR checking operations on the standby mode are controlled by IC211 MSP430F1101A on the analog board. It also controls audio switching.

• DMN8652 IC sends the commands to IC101 PT6315 via socket PL101 (pins 4, 5 and 6). • Pin 5 is the oscillator pin and is connected via R169 100K. • LED D1(blue colour) is on in stand-by mode and off when the device is on. • Vacuum fluorescent display MD1 is specially designed for RW3400. • IR remote control receiver module IC102 (TSOP1836) sends the commands from the remote

control directly to DMN8652 and MSP430F1101A analog board controller. • Socket PL102 is the power connector of board and it carries the operating power(5V), VFD

filament voltage and –22 Volts. • Also there are connectors for Left&Right audio inputs and CVBS and S-Video Video inputs. • U1(TPS2041) is USB electrical interface chip which DMN8652 communicates with USB

devices via U1. • U2(AU9368) is multistandard memory card reader chip. DMN8652 communicates with U2 by

USB port. C.3 I/OS & BACK PANEL

• JK605 RCA audio jack on the analog board gives out analog audio that come from audio opamps in the form of Front Left, Front Right, Rear Left, Rear Right, Center and Subwoofer.

• There are two SCART connectors SCART1 and SCART2 (Scart2 is for input on Scart mode and Scart1 is for TV output), 1 RCA connector for CVBS out, 1 Connector for SVHS output.

• There are RF input and TV output connections on the tuner. • There are two SPDIF outputs on the power board, optical (MD100) and coaxial (JK100).

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D SERVICE MENU IN THE SOFTWARE When you power on the RW3400 DVD-Recorder, you can access to a hidden menu with useful information about the system by the following procedure:

• Be sure that tray is closed • Press ‘SETUP’ key • Press ‘3’, ‘2’,’1’ and ‘CLEAR’ keys consecutively.

Hidden menu content:

• Software Version Number / Download Date • Loader FW Version Number • Macrovision FW Version Number • MPEG Chip ID • Audio DAC • Region Number • Development Team

Region information may be between 0-6. 0 means the unit is multi-region, ie, it can play all discs independent of discs own region information. If player is set for a specific region and you try to play a dvd disc with another region information, disc will not be played. E SW UPDATE PROCEDURE Burn the given files to the CD according to the rules below. 1) Update file name must be DMN8600.CUB 2) No multi session and finalize CD options must be selected before burning Update procedure: 1) Insert the disc. 2) Select yes in the CD update confirmation screen. 3) The unit first loads the software into the memory then ejects the disc automatically. 4) Take the disc out and press close. 5) Wait until the player resets itself. (The flash update may take several minutes.) 6) After reset the update process is done. !!! Don't power off the unit after the disc has been ejected. !!!

sm_rw3400

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