some ideas for a tracking and timestamp pixel detector suitable for clic
DESCRIPTION
Some ideas for a tracking and timestamp pixel detector suitable for CLIC. Rafa Ballabriga, Michael Campbell, Xavier Llopart, Sami Vähänen CERN ESE. Outline. Assumptions for CLIC The effect of segmentation on performance (noise and jitter) - PowerPoint PPT PresentationTRANSCRIPT
Some ideas for a tracking and Some ideas for a tracking and timestamp pixel detector timestamp pixel detector
suitable for CLICsuitable for CLIC
Rafa Ballabriga, Michael Campbell, Xavier Llopart,
Sami Vähänen
CERN ESE
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OutlineOutline
• Assumptions for CLIC• The effect of segmentation on performance
(noise and jitter)• The Timepix architecture and how it could be
improved• Low mass bump bonding
-3-
Assumptions for CLICAssumptions for CLIC
• ~312 bunches per train spaced by 0.5ns• 50Hz bunch rate• Pixel size <= 15 m• Detector diameter 3cm• Detector length ~20cm• Physics hit occupancy ~20 hits/train• Background ~2M hits/train• Pixel occupancy on inner layer ~ 10-2??• Total power budget ~ 100mW/cm2
• Power cycling allows at least x10 more during up time • Each pixel records bunch number (or a multiple thereof)
for a given train• Full readout between trains
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p+
n-well
p-substrate gm
Iin Vout
p+
n-well
gm
Iin Vout
n-
CDET x PixelSide2
Cpadlin x PixelSide
Cpad
Geometry for readout chip bump-bonded to Si Sensor
-5-
Assumption for noise and jitter Assumption for noise and jitter calculations calculations
• Constant power dissipation 1W/cm2
• 70% of the power dissipated in the input stage (differential)
• Collection time must be faster than shaping time
• Charge sharing not taken into account• The input transistor size is calculated for
optimal ENC (Equivalent Noise Charge) for a given pixel size and shaping time
• First order CR-RC shaper
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CFB
2sv
s
ID CDET
VOUT
2pdi CinMOS
21)(
s
sshaper
s
ssH
IPR
WLfC
K
gKTnvvv
ox
a
mfthermals 2
2/1
22 14
2222 2 resetolknetworkdpd iqIiii
2SidePixelII Oo
System schematic System schematic
-7-
pspffws
thermalinMOS aiaAa
vCCENC
2
22
det2 2
mthermal g
KTnv1
42 WLC
KA
ox
af 2
Noise Equation:
Calculated from EKV modelnmL 200
W=OptimumW(Pixel Side)
Noise equationNoise equation
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0
200
400
600
800
1000
1200
1400
1600
0 100 200 300 400 500 600 700 800 900 1000
Pixel Side (um)
Inp
ut
Cap
acit
ance
(fF
)
CDET =/xD Cpadlin=1pF/cm Cpad=50fF (25m diameter pad)
is the permittivity (1.054 10-12 F cm-1 for Si) and xD is the thickness of the depletion region (xD equals 100m in the results presented in this report)
Geometry for readout chip bump-bonded to Si Sensor (input
capacitance)
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ENC as a function of shaping timeENC as a function of shaping time
ENC as a function of the pixel side for different shaping times. (1W/cm2, Si sensor Ileak = 1A/cm2)
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in
s
Q
ENCnsJitter
)(
• Triangular signal, Qin=7000e-
2max 10
1
PixelSideFlux
s
TimingTiming
Giovanni Anelli, FEE 2006 Perugia
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in
s
Q
ENCnsJitter
)(JitterJitter
0.01
0.1
1
10
100
10 100 1000
Pixel Side (um)
Jitt
er
(ns) Jitter (ns) (10ns) (Si)
Jitter (ns) (100ns) (Si)
Jitter (ns) (1us) (Si)
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Timepix Pixel SchematicTimepix Pixel Schematic
Preamp
Disc
THR14 bitsShift
Register
Input
Ctest
Testbit
Test Input
Mask
4 bits thr Adj
Mux
Mux
Clk_Read
Previous Pixel
Next Pixel
Conf
8 bits configuration
Polarity
Analog Digital
Clk_Count
Timepix Synchronization
Logic
Clk_Countb
P0
P1
Shutter
Ovf Control
Clk_Read
Shutter_int
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Area use in Medipix3 pixel
21
67
4
3
5
Area pixel: 55x55m2
Preamplifier~1/8 pixel surface
Analog part~30x30m (if charge summing is not needed)
(130nm IBM CMOS process)
1. Preamplifier2. Shaper3. Two discriminators with 4-bit
threshold adjustment4. Configuration bits5. Arbitration logic for charge
allocation6. Control logic7. Configurable counter.
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CLICpix readout architectureCLICpix readout architecture
• Pixels 15 m x 15 m• 65nm technology or less• Matrix 1024 x 1024 pixels• 1W/cm2 analog on power (100mW/cm2 DC)• Each pixel records bunch number (or multiple
thereof) • Timing precision 10ns or better• ToT in each pixel• All data read out at end of train
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Assembly
• Hybrid pixel with thinned readout chip (50m thick) and thin sensor (100m thick)
• Carbon nanofibre bumps• Carbon nanofibre heat sink
Smoltek’s technology enablescontrol of the morphology and properties of carbon nanofibers
Unique Control Carbon Nanofiber*• Electromigration occurs at >106A/cm2
• 100 % Yield
• diameter of 20- 200 nm
• height from 50 nm- 3 μm
• Compatible with CMOS-processes