songs about computer science topics digital logic …

Topics Datapath

x stages performing computation [x=5]

y hardware components needed

Combinational and Sequential logic Logic Gates

Computer Organisation 300096, Jamie Yang: [email protected]

Lecture 09: Datapath and Control

SONGS ABOUT COMPUTER SCIENCE

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To get all our programs to runThere must be compilation doneInto ones and zer-os:Seems rather tame.

But how do ones and zeros makeOur hardware bump and shake?Trans-..is-..tor..gates!It won't be hard to see.We Use...

Digital logic: inputs, switches...and grounds.inputs, switches...and grounds.inputs, switches...and grounds.Just by abstracting voltage, into zer-o's and ones.We can hack all night and day.… …

Five components of a Computer

2Computer Organisation 300096, Jamie Yang: [email protected]

Processor

Control

Datapath

Memory

Devices

Output

Input

Processor (CPU):

Datapath:

Control:

Elements that process data and addresses in the CPU [e.g. registers, ALUs, …]Determines which computation is performed [e.g. Routes data thru datapath (which regs, which ALU op)

Connection and Communication via Bus


Processor

Control

Datapath

Memory

Devices

Output

Input

A Bus is a shared communication link Single set of wires used to connect multiple subsystems A Bus is also a fundamental tool for composing large,

complex systems … this topic is fully covered in Computer Architecture course…

Datapath concept

Possible approach: build a single block to “execute an instruction”, which designed to perform all necessary operations starting from fetching the instruction Possible, but too bulky, inefficient and inflexible


Modular approach: break up the process of “executing an instruction” into stages, then connect stages… datapath is born! Advantages:

smaller, easier to understand and easier design blocks easier to optimise: one block can be changed without

affecting the others Elements that process data and addressesin the CPU

Fetch Decode Exec

Datapath Stages


+4

ALU

stage 4 OR stage 5

1. 2. 3. 4. 5.

rdrsrt

imm

PC (Program Counter)… Memory… Various registers ... ALU …

1. Fetch 2. Decode 3. ALU 4. Mem 5. Reg

Datapath Stages: 1

There is a wide variety of MIPS instructions: what general steps do they have in common?


Stage 1: Instruction FetchPC=PC+4

Datapath Stages: 2


Stage 2: Instruction Decode [0x 02324020 --- refer to ‘instruction decoding.pdf’ in materials folder]

5-bit decoder:specifies registers 0 - 31

register operands

555

Datapath Stages: 3


Stage 3: ALU (Arithmetic-Logic Unit) … Perform arithmetic/logical operation …

Datapath Stages: 4 and 5


Stage 5: Register Write

Stage 4: Memory Access (load/store data)

Calculate memory address sw

lw0x 0040003c

Datapath Instruction Example


+4

ALU

rdrsrt

imm

3 1 2

reg[1]

reg[2]

reg[1]+

reg[2]

look at a sample instruction add: add $r3, $r1, $r2 # r3 = r1+r2

Role of Controller


Controller causes the right transfers to happen.

+4

ALU

rdrsrt

imm

Controller

opcode, funct

R-Format Instructions


Read two register operands Perform arithmetic/logical operation Write register result

Branch Instructions


Read register operands Compare operands

Use ALU, subtract and check Zero output Calculate target address

bne $s0, $s1, Exit

bi-directional

address words

Combinational and Sequential Circuits


A complex functional component is implemented using lower level components - there are two classes of logic circuits:

COMBINATIONAL circuits SEQUENTIAL/STATE circuitsNo memory Have internal memory (or: elements that

contain state)The output depends only on the input

the output depends both on the set of inputs supplied and the value stored in memory, which is called the state of the logic block

how to ensure memory element is updated neither too soon, nor too late?

Truth Tables, Boolean Algebra Finite state machine (Mealy, Moore) …more on sequential circuits later, first: combinational logic…

Truth Tables, Boolean Algebra


Combinational logic does not have memory, so it’s described by defining the values of the outputs for each possible set of input values, as in truth tables.

Another approach: one can express the logic function with logic equations with the use of Boolean algebra.

Main Boolean algebra laws: [“+” is operator OR, and “●” is operator AND]Identity law A+0=A and A ● 1=AZero and One laws A+1=1 and A ● 0=0Inverse laws A+Ā=1 and A ● Ā=0Commutative laws A+B=B+A and A ● B= B ● AAssociative laws A+(B+C)=(A+B)+C and A ● (B ● C)=(A ● B) ● CDistributive laws A ● (B+C)=(A ● B)+ (A ● C) and

A+(B ● C)=(A+B) ● (A+C)

Logic Gates, Inverter and Multiplexor (Mux)


1. AND gate (c = a ● b)

2. OR gate (c = a + b)

3. Inverter (c = a)

4. Multiplexor (Mux)(if d = = 0, c = a;

else c = b)

Selector (Decoder)


Only one output is asserted for each input combination For example:

if inputs In0, In1, In2 are: 1 0 0 (decimal 4):Out4 = 1, all other outputs are 0

Out0Out1Out2Out3Out4Out5Out6Out7

3-bit decoder:inputs In0, In1, In2

00001000

Convert one bit-pattern to another bit-pattern

Universal Gates [Exercise]


In fact ALL logic functions can be constructed with only a single gate type, if it is inverting.

Common inverting gates are NOR (inverted OR) and NAND (inverted AND).

NOR and NAND are called universal gates.

Exercise:prove the above by implementingAND, OR and NOT:

1. using only NOR gates,2. using only NAND gates.

Universal Gates [Exercise]


Exercise:prove the above by implementing AND, OR and NOT:

1. using only NOR gates,2. using only NAND gates.

AND

OR

NOT

A Ā

AĀ

XOR implementation [Exercise]


How to construct eXclusive OR (XOR)?

Ordinary Implementation Universal Implementation?

Multiplexor implementation [Exercise]


How to construct Multiplexor (Mux)?

Ordinary Implementation Universal Implementation?

(Select)

S c0 a1 b

Arrays of logic elements


Used when combinational operations need to be performed on entire word (32 bits) for example when the result of an instruction that is written

into a register can come from one of two sources

32-bit wide 2-to-1 multiplexor

32-b

it w

ide

mul

tiple

xor i

s an

ar

ray

of 3

2 1-

bit m

ultip

lexo

rs

Programmable Logic Array (PLA)


Two-levels sum of products representation the 1st stage: array of AND gates that forms a set of product

terms (also known as miniterms), the 2nd stage: array of OR gates each of which forms a

logical sum of any number of the product terms.

1st stage

2nd stage

Sample PLA 1/2


Implements logic from page C-13 in the textbook (three inputs, three outputs)

2nd stage

1st stage

See a simplified drawing in next slide

Ā ● B ● C

Sample PLA 2/2


As before, simplified drawing shows AND and OR planes. Note inputs A, B and C run the width of AND plane in both

true and complement form.

true

complement

Ā ● B ● C

Clock


Clock: free running signal with fixed cycle time (clock period)

Clock determines when to write memory element level-triggered – act (store) on clock high (or low) edge-triggered – act (store) only on clock edge

We will consider here only negative (falling) edge-triggeredclocking methodology

Clock in MIPS (5 steps of datapath)


Synchronous (or clocked) combinational circuits Single-cycle machine: does everything in one clock cycle

instruction execution = up to 5 steps must complete 5th step before cycle ends

clocksignal

rising clock edge

falling clock edge

instruction executionstep 1/step 2/step 3/step 4/step 5

datapathstable

when the active clock edge occurs

Sequential logic: memory elements


All memory element store states: The output from any memory element depends BOTH on the

inputs and on the value stored inside the memory element. The simplest memory elements are unclocked (see S-R latch

next).

SR (set-reset) Latch, unclocked


SR-latch implemented with NOR Gates Output depends on both inputs and values stored (previous state)

S = 1 and R = 1 not allowed R=S=0 (removal of the input combination of 0’s and 1’s), output will

not change (NC) -- depends on the values in previous state Otherwise output copying input (set or reset action)

S=1 asserted, set Q=1 asserted;R asserted, Q deasserted.

D Latch (clocked), or: Delay Flip-Flop


When the clock C is asserted, the latch is opened, and the output Q immediately assumes the value of the D input

Sometimes called a transparent latch (when the latch opened, Q changes as D changes)

a clock signal

value to be stored

C controls the behavior of Qattempting to learn from D

FYI - Electronics Demonstrations:“Clocked SR Flip-Flop” athttps://www.falstad.com/circuit/e-clockedsrff.html

D flip-flop with a falling-edge trigger


Flip-flop: state changes only on a clock edge Master: the first latch, when the clock C is asserted Q follows D Slave: the second latch, when the clock C falls gets its input

from the output of the master latch.

C controls the behavior of Qattempting to learn from D

FYI - Electronics Demonstrations:“Master-Slave Flip-Flop” at https://www.falstad.com/circuit/e-masterslaveff.html

Register File Implementation


A register file with two read ports and one write port. Can be implemented with a decoder for each read or write port and

an array of D flip-flops used as registers.

Appendix C, C-54

Register: multiple flip-flops forming a single entity with the same clock signal

Register File Implementation 1/2 (read)


Implementation of two register read ports for a 32-bit wide register file

‘read register’ signal used as the multiplexor selector signal.

Read registernumber 1

Read registernumber 2

Read data 1

Read data 2

Register File Implementation 2/2 (write)


Decoder used together with the write signal to determine which register to write.

All three inputs will have set-up and hold-time constraints.

Write

Register number

Register data

$30

Revision


The following block-diagram demonstrates the branch instruction processing. Explain what do ‘Sign-extend’ and ‘Shift left 2’ perform.

The two-stage Programmable Logic Array (PLA)models its output as “a sum of products”.What does it mean?

bne $s0, $s1, Exit

Recommended readings


Text readings are listed in Teaching Schedule and Learning Guide

PH4: eBook is available

PH5: no eBook on library site yet

PH5: companion materials (e.g. online sections for further readings) http://booksite.elsevier.com/9780124077263/?ISBN=9780124077263

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