split, 12 december 2005 university of zagreb slide 1 chip level emc measurements and simulations...
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![Page 1: Split, 12 December 2005 University of Zagreb Slide 1 Chip level EMC measurements and simulations “Impact of Communications Technology to EMC“, COST 286](https://reader035.vdocuments.net/reader035/viewer/2022062518/56649d595503460f94a38a11/html5/thumbnails/1.jpg)
Slide 1
Split, 12 December 2005 University of Zagreb
Chip level EMC measurements and simulations
“Impact of Communications Technology to EMC“,
COST 286 Workshop
Vladimir Čeperić
Hrvoje Marković
Adrijan Barić
Faculty of Electrical Engineering and Computing,
University of Zagreb
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Slide 2
Split, 12 December 2005 University of Zagreb
Chip level EMC measurements and simulations
• European research program ROBUSPIC (ROBUst mixed signal design
methodologies for Smart Power ICs).
• UZAG’s focus points:
– Development of parasitic extraction procedures suitable for EMC
(electro-magnetic compatibility) analysis
– Identification and modelling of EME (electro-magnetic emission)
sources and analysis of EMI (electro-magnetic immunity)
– Methodology for full-chip smart-power EMC simulation
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Slide 3
Split, 12 December 2005 University of Zagreb
Outline
• Integrating EMC simulations in design flow
• Extraction and influence of PWR/GND parasitics
• EMC measurements system (IEC 62132-4 and IEC 61967-4)
• EMC test chip
• EMC optimizations
• Conclusion
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Split, 12 December 2005 University of Zagreb
Design flow
System level architecture design & component spec.
Electrical circuit design
Physical pattern layout
RC/RLC parasitic extraction & EMC simulations
Measurement & verification
PWR/GND lines/core of the circuitseparation
RC extraction of the core (Assura, ...)
RC (RLC) extraction of PWR/GND lines
Spice netlist
EMC simulations
MOR
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Slide 5
Split, 12 December 2005 University of Zagreb
The influence of the PWR/GND parasitics on the the emission levels
Comparison of invertor module and invertor module with HFSS extracted PWR/GND structure
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Slide 6
Split, 12 December 2005 University of Zagreb
NEED TO CONSIDER PACKAGING PARASITICS!
Influence of the package
SOIC8 package
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Slide 7
Split, 12 December 2005 University of Zagreb
Cadence Interface in Skill language
For conducted EME (IEC 61967-4)
- automatic generation of the Spectre netlist(s) with implementation of the 1
Ohm method
- transient simulations in Spectre
- manipulation of the results to determine the spectrum
- display of the results and automatic determination of the emission levels
For EM immunity (IEC 62132-4)
- Spectre analyses for defined
input power range
- determination of the input power
which causes malfunction
- display of the results
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Split, 12 December 2005 University of Zagreb
RC load of the BUS, R=1 kOhm (to VBAT) and C=1 nF to GNDOperating at 20.0 kbit/sec, VBAT = 13.7 V,Input frequency f=1 MHz
IEC 62132-4 for the measurement of EM immunity with direct
RF power injection method - HTVD LIN
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Slide 9
Split, 12 December 2005 University of Zagreb
EME and EMI HTVD LIN interface measurement system
EMC measurement system
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Slide 10
Split, 12 December 2005 University of Zagreb
HTVD – LIN interface EMC measurements
EME measurements-
Voltage over 1 Ohm
(IEC 61947-4)
Rx
D Tx
D BU
S
EMI measurements - DPI method (IEC 62132-4)
– Matlab measuring automatization:
– EME_EMI_measure_GPIB.m script
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Split, 12 December 2005 University of Zagreb
HTVD – LIN interface 1 Ohm method
measurement simulation
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Slide 12
Split, 12 December 2005 University of Zagreb
EMC test chip
Chip for EMC testing:
high voltage and low voltage parts - ams C35/H35
digital
conducted EME testing structure (to evaluate the influence of backannotation)
LIN interface (conducted EME and EMI)
analog
LC oscillator (conducted EME, package parasitics model evaluation)
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Slide 13
Split, 12 December 2005 University of Zagreb
EMC test chip
Chip for EMC testing:
two different packages used to
evaluate package influence on EME
and EMI
CLCC84
(Ceramic Leadless Chip Carrier)
JLCC84
(J-Leaded Ceramic Chip Carrier)
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Slide 14
Split, 12 December 2005 University of Zagreb
EMC test chip
Chip for EMC testing:conducted EME testing structure
LIN1, LIN2
LC oscillator1, LC oscillator2
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Slide 15
Split, 12 December 2005 University of Zagreb
Conducted EME testing structure
Conducted EME test structure enables:
Output buffers with different output currents can be enabled5.
Different number of PWR/GND refreshes4.
Different widths of PWR/GND rails3.
Input of each block can either be common input signal or
output of previous block
2.
Independent switching of 96 blocks1.
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Slide 16
Split, 12 December 2005 University of Zagreb
QUAD LC oscillator and VCO
• High voltage (AMS H35 CMOS technology)• Cross-coupling increases significantly the precision of the oscillation
frequency• Bond wires provide a resonant tank with high Q• conducted EME simulation and measurement• Bond wires used as inductance
– package parasitics model evaluation
VCO
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Slide 17
Split, 12 December 2005 University of Zagreb
LIN interface
• LIN interface is design in high voltage technology (50V)
• Design is tested for EM emission and EM immunity
LIN interface from LIN2.0 standard ( Figure 3.1 )
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Split, 12 December 2005 University of Zagreb
LIN interface EME optimization
After optimization: C-12-m
– Matlab script: EmissionLeveloptimization.m
Before optimization: C-10-o
Optimization parameters: voltage levels on BUS, emission level of LIN interface,
width, length and number of fingers of the high voltage transistor at TxD input
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Split, 12 December 2005 University of Zagreb
LIN interface EMS optimization
Optimization parameters: duty cycle and time delay (LIN 2.0 standard),
width, of the 10 transistors in Schmitt trigger
Matlab script: ImmunityOptimization.m
• Psin source connected to BUS pin via 4.7nF capacitor
f1=150kHz, f2=1MHz, dBm=20Without optimization:
max: td1=6.0755e-06, td2=5.691e-06
duty cycle min=0.4098
duty cycle max=0.4254
With optimization:
max: td1=5.2535e-06, td2=5.691e-06
duty cycle min=0.4278
duty cycle max= 0.42793
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Slide 20
Split, 12 December 2005 University of Zagreb
Conclusion
• EMC simulations can be incorporated into design flow• Package and PCB parasitics have to be considered• EMC measurement system according to IEC 62132-4
and IEC 61967-4 standards is being built• EMC test chip enables easy validation of EMC
simulations vs. measurements– package model validation– comparison of 3D EM simulations vs. RC extraction
simulations• Circuit optimizations wrt. EMC behavior are performed