spring 20067w. rhett davis with minor modifications by dean brock ece 406 at unaslide 1 ece 406...
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Spring 20067W. Rhett Davis with minor modifications by Dean Brock ECE 406 at UNA Slide 1
ECE 406 ECE 406 Design of Complex Digital Design of Complex Digital
SystemsSystems
Lecture Lecture 10:10: 9: 9: State Machines & Reset State Machines & Reset
BehaviorBehaviorSpring Spring 20062006 2007 2007
W. Rhett DavisW. Rhett DavisNC State UniversityNC State University
with significant material from Paul Franzon & Bill Allenwith significant material from Paul Franzon & Bill Allen
Spring 20067W. Rhett Davis with minor modifications by Dean Brock ECE 406 at UNA Slide 2
Summary of Lecture 8
How do you model a flip-flop?
What is the difference between blocking and non-blocking assignments?
How do you infer flip-flops for an always@(posedge clock) procedure with blocking or non-blocking assignments?
Is it better to use blocking or non-blocking assignments in an always@(posedge clock) procedure? Why?
Spring 20067W. Rhett Davis with minor modifications by Dean Brock ECE 406 at UNA Slide 3
Summary of Lecture 8
What are the key elements of the “simplified coding stlye”?
What Verilog constructs do you use to describe» MUXes» Control logic» Datapath logic» Registers
Spring 20067W. Rhett Davis with minor modifications by Dean Brock ECE 406 at UNA Slide 4
Today’s Lecture
State Machine Design (1.3.1, 2.6)
Using Reset Signals (1.3.2)
Data Converter Example
Spring 20067W. Rhett Davis with minor modifications by Dean Brock ECE 406 at UNA Slide 5
State Machine Design
This is a state-transition diagram
If you were asked to design a state-machine to implement this diagram, how would you do it?
in==0
in==1
in==0
in==1
Spring 20067W. Rhett Davis with minor modifications by Dean Brock ECE 406 at UNA Slide 6
Generalized State Machines
state register
input
current state
next state
outputstate-update and output logic
(combinational)
“Mealy Machine”» Most general» outputs labeled on
transitions
in==0 / out=2
in==1 / out=3
in==0 / out=1
in==1 / out=4
out=5
Spring 20067W. Rhett Davis with minor modifications by Dean Brock ECE 406 at UNA Slide 7
Moore Machine
Less General Output depends
on current state only
in==0
in==1
in==0
in==1 out=1
out=2
out=3
state register
input
current state
next state
output
state-update logic (combinational)
output logic (combinational)
Spring 20067W. Rhett Davis with minor modifications by Dean Brock ECE 406 at UNA Slide 8
State Machine Design
Step 1: Assign States Step 2: Create the state-
register Step 3: Write a
combinational procedure to implement the state-update logic and output logic
in==0
in==1
in==0
in==1 0 1 2
reg current_state, next_state;always@(posedge clock) current_state <= next_state;
always@(in or current_state) case (current_state) 0: if (in) next_state <= 0; else next_state <= 1;
1: if (in) next_state <= 2;
else next_state <= 0;
2: next_state <= 0;
default: next_state <= 0;
endcase
Spring 20067W. Rhett Davis with minor modifications by Dean Brock ECE 406 at UNA Slide 9
Sophisticated Style State Machine
Could you implement the output logic with this same always@ block?
in==0
in==1
in==0
in==1 0 1 2
reg state;always@(posedge clock) case (state) 0: if (in) state <= 0; else state <= 1;
1: if (in) state <= 2;
else state <= 0;
2: state <= 0;
default: state <= 0;
endcase
Spring 20067W. Rhett Davis with minor modifications by Dean Brock ECE 406 at UNA Slide 10
Today’s Lecture
State Machine Design (1.3.1, 2.6)
Using Reset Signals (1.3.2)
Data Converter Example
Spring 20067W. Rhett Davis with minor modifications by Dean Brock ECE 406 at UNA Slide 11
Reset Signals
At the start of the simulation, state has the value X
What will the next state be?
Will this be the case with synthesized hardware?
reg state;always@(posedge clock) case (state) 0: if (in) state <= 0; else state <= 1;
1: if (in) state <= 2;
else state <= 0;
2: state <= 0;
default: state <= 0;
endcase
Spring 20067W. Rhett Davis with minor modifications by Dean Brock ECE 406 at UNA Slide 12
Rules for Reset Signals
Only the edges for the clock and reset should be in sensitivity list
Reset condition should be specified first
No condition should be made on the clock
Spring 20067W. Rhett Davis with minor modifications by Dean Brock ECE 406 at UNA Slide 13
Types of Reset Signals
Asynchronous: Reset happens as soon as reset signal is asserted
Synchronous: Reset is synchronized to clock
always@(posedge clock or posedge reset) if (reset) value <= 0; else value <= next_value;
always@(posedge clock) if (reset) value <= 0; else value <= next_value;
Active-high reset
Spring 20067W. Rhett Davis with minor modifications by Dean Brock ECE 406 at UNA Slide 14
Active-Low Reset
How would you implement an active-low asynchronous reset?
WARNING: Popular Exam Question!
Spring 20067W. Rhett Davis with minor modifications by Dean Brock ECE 406 at UNA Slide 15
Resetting the State Machine
We generally prefer synchronous resets to asynchronous, so that we don’t have to worry about the relative timing of the two signals
reg state;always@(posedge clock) if (reset) state <= 0; else case (state) 0: if (in) state <= 0; else state <= 1;
1: if (in) state <= 2;
else state <= 0;
2: state <= 0;
default: state <= 0;
endcase
Spring 20067W. Rhett Davis with minor modifications by Dean Brock ECE 406 at UNA Slide 16
Today’s Lecture
State Machine Design (1.3.1, 2.6)
Using Reset Signals (1.3.2)
Data Converter Example
Spring 20067W. Rhett Davis with minor modifications by Dean Brock ECE 406 at UNA Slide 17
Data Converter Specification
When a new 32-bit data word arrives at the input, the module stores it and then outputs the word as 4 bytes, starting with the MSB and ending with the LSB.
The arrival of a 32-bit word to be converted is signaled by a pulse on ready that is 3 clock cycles long.
The output of a byte of data is signaled by a one clock cycle pulse on new. The output byte is available during the new pulse and for one clock cycle after.
Data Converter
IN
readyOUT
new
32
/ 8
/
Spring 20067W. Rhett Davis with minor modifications by Dean Brock ECE 406 at UNA Slide 18
Design Process
Step 1: Write Specification Step 2: Draw Schematic
» Ports» Registers» Datapath Logic» MUXes» Control Logic
Step 3: Write Verilog Code» Label Internal Signals» Map elements from schematic into code
Spring 20067W. Rhett Davis with minor modifications by Dean Brock ECE 406 at UNA Slide 19
Data Selector Schematic
ready
IN
clock
OUT
enable
D Q832
value
load 2
8
new
8
8
8
0
1
2
3
[31:24]
[23:16]
[15:8]
[7:0]
32
sel
State and output update logic
reset
DQ
reset
next_statestate
Spring 20067W. Rhett Davis with minor modifications by Dean Brock ECE 406 at UNA Slide 20
Controller State Diagramready==0
new=0load=0sel= 0
0
9
8
7
6
1
2
3
45
ready==1new=0load=1sel= 0
new=1load=0sel= 0
new=0load=0sel= 0
new=1load=0sel= 1
new=0load=0sel= 1new=1
load=0sel= 2
new=0load=0sel= 2
new=1load=0sel= 3
new=0load=0sel= 3
Spring 20067W. Rhett Davis with minor modifications by Dean Brock ECE 406 at UNA Slide 21
Data Converter (Simplified Style)
•module dataconv(IN, clock, ready, reset, OUT, new);• input clock,reset,ready;• input [31:0] IN; • output [7:0] OUT;• output new;•
Complete the module description
Spring 20067W. Rhett Davis with minor modifications by Dean Brock ECE 406 at UNA Slide 22
Data Converter (Simplified Style)
Spring 20067W. Rhett Davis with minor modifications by Dean Brock ECE 406 at UNA Slide 23
Data Converter (Simplified Style)
Spring 20067W. Rhett Davis with minor modifications by Dean Brock ECE 406 at UNA Slide 24
Data Converter (Sophisticated Style)
•module dataconv(IN, clock, ready, reset, OUT, new);•input clock,reset,ready;•input [31:0] IN; •output [7:0] OUT;•output new;
•reg [7:0] OUT;•reg new;•reg [31:0] value;•reg [3:0] state;
•always @(posedge clock)• begin• if (reset)• state <= 0;•
• else• case(state)• 0: begin• if (ready) state <= 1;• else state <= 0;• new <= 0;• end• 1: begin • state <= 2; • value <= IN;• end• 2: begin • state <= 3; • OUT <= value[31:24];• new <= 1; • end
Spring 20067W. Rhett Davis with minor modifications by Dean Brock ECE 406 at UNA Slide 25
Data Converter (Sophisticated Style)
• 3: begin • state <= 4; • new <= 0; • end• 4: begin • state <= 5; • OUT <= value[23:16];• new <= 1; • end• 5: begin • state <= 6; • new <= 0; • end• 6: begin • state <= 7; • OUT <= value[15:8];• new <= 1; • end
• 7: begin • state <= 8; • new <= 0; • end• 8: begin • state <= 9; • OUT <= value[7:0];• new <= 1; • end• 9: begin • state <= 0; • new <= 0; • end• default: begin state <= 0; end• endcase• end
•endmodule
Spring 20067W. Rhett Davis with minor modifications by Dean Brock ECE 406 at UNA Slide 26
Comparison of Styles
What will be the difference between the hardware synthesized from the simplified and sophisticated versions of the Data Converter code given in class?
Spring 20067W. Rhett Davis with minor modifications by Dean Brock ECE 406 at UNA Slide 27
Summary
How do you implement a state-machine when given a state-transition diagram?
Why in general do you need a reset-signal for a module?
What is the difference between synchronous and asynchronous reset signals?