sso simulation with ibis · kpd(t)*ipd(vout) ipc(vout) igc(vout) c_comp/2 c_comp/2 out vss vdd...

Manfred M

aurer Folie 1IBIS Summit Meeting Munich 2006

Overview

SSN 2000

kssn - table

EnhancedVCCS model

Summary

Industrial Solutions and ServicesYour Success is Our Goal

SSO Simulation with IBISManfred [email protected]

www.siemens.de/edh

Manfred M


Overview

SSN 2000

kssn - table

EnhancedVCCS model

Summary

Overview

Overview

MotivationMotivationSSN SSN withwith IBIS in 2000IBIS in 2000

Simulation Simulation setupsetup

BEHAVIOR BEHAVIOR –– modelmodel withwith VoltageVoltage--ControlledControlled CurrentCurrent SourcesSources

veryvery good good concordanceconcordance withwith transistortransistor basedbased modelsmodels

Table Table drivendriven kssnkssn--multipliermultiplier

Multiplier Multiplier extractionextraction

ResultsResults HSPICE vs. VCCSHSPICE vs. VCCS--BEHAVIORBEHAVIOR

LackingLacking concordanceconcordanceEnhancedEnhanced VCCSVCCS--BEHAVIOR BEHAVIOR

Additional RC Additional RC –– Timing Timing coeficientcoeficient

ImprovedImproved resultsresultsSummary Summary

Manfred M


Overview

SSN 2000

kssn - table

EnhancedVCCS model

Summary

Acknowledgements

Overview

TEXAS INSTRUMENTSTEXAS INSTRUMENTSCDCE706 CDCE706

PROGRAMMABLE 3PROGRAMMABLE 3--PLL CLOCK SYNTHESIZER /PLL CLOCK SYNTHESIZER /MULTIPLIER / DIVIDERMULTIPLIER / DIVIDER

INFINEON TECHNOLOGIES INFINEON TECHNOLOGIES HYB18T512160AF

DDR2 - Memory

Manfred M


Overview

SSN 2000

kssn - table

EnhancedVCCS model

Summary

SSO Simulation Setup ( m+1 switching outputs )

T1

T2

H / L

VCC

GND

IF1 =m x I VDD

IF2 =m x I GND

IVDD

IGND

C GND

C VDD

LVD D

LGND

RVD D

R GND

PackageRLC

PackageRLC

TRANSMITTER RECEIVER

R1

R2

tr-line

tr-line

Quiet Output

Switching Output

SSN 2000

Manfred M


Overview

SSN 2000

kssn - table

EnhancedVCCS model

Summary

VCCS-Model enhancement

kssnr(Vdd-Vss) *kpu(t) *Ipu(Vout)

kssnf(Vdd-Vss) *kpd(t) *Ipd(Vout)

Ipc(Vout)

Igc(Vout)

C_comp/2

C_comp/2

OUT

VSS

VDD

• A second multiplier for rising (kssnr) and falling (kssnf) edges• Both multipliers are controlled by the (Vdd-Vss) voltage drop• Feedback on the gate source voltage of the output transistors• Multiplier generation:

Pullup/down V/I-tables as a function of VddSSO-V/t-table (Golden Waveform)

SSN 2000

Manfred M


Overview

SSN 2000

kssn - table

EnhancedVCCS model

Summary

VCX16244 SSN analysis results (rising edge)Enhanced two waveform behavioral model Number of SSO = 6

Node OUT:Transistor basedBehavioral

Node END:Transistor basedBehavioral

Node OUT:Transistor basedBehavioral

Node END:Transistor basedBehavioral

SSN 2000

Manfred M


Overview

SSN 2000

kssn - table

EnhancedVCCS model

Summary

kssnr/f Multiplier Generation Method

SSN 2000

I(3.6V)

I(3.3V)

50 Ohm loading characteristic

CMOS Driver Output High Characteristic

kssnr(3.6V) = I(3.6V)/I(3.3V)

Manfred M


Overview

SSN 2000

kssn - table

EnhancedVCCS model

Summary

kssn rising coefficient extractionHYB18T512160AF (DDR2) INFINEON

kssn - table

Manfred M


Overview

SSN 2000

kssn - table

EnhancedVCCS model

Summary

kssn falling coefficient extractionHYB18T512160AF (DDR2) INFINEON

kssn - table

zoom

Manfred M


Overview

SSN 2000

kssn - table

EnhancedVCCS model

Summary

kssn falling coefficient extraction (zoom)HYB18T512160AF (DDR2) INFINEON

kssn - table

Manfred M


Overview

SSN 2000

kssn - table

EnhancedVCCS model

Summary

HYB18T512160AF / INFINEON kssn rising/falling @ Vdd = 0.5V to 3.6V (1.8V nom.)

0,0000

0,5000

1,0000

1,5000

2,0000

0,4 0,6 0,8 1 1,2 1,4 1,6 1,8 2 2,2 2,4 2,6 2,8 3 3,2 3,4 3,6

Vdd (V)

kssn kssnr

kssnf

Vdd_nom

kssn - table

Manfred M


Overview

SSN 2000

kssn - table

EnhancedVCCS model

Summary

TI CDCE706 TEXAS INSTRUMENTS kssn rising/falling @ Vdd = 0.5V to 5V (3.3V nom.)

0,000

0,200

0,400

0,600

0,800

1,000

1,200

1,400

1,600

0,3 0,6 0,9 1,2 1,5 1,8 2,1 2,4 2,7 3 3,3 3,6 3,9 4,2 4,5 4,8

Vdd(V)

kssn

kssnfkssnrkssnr_00kssnf_00

Vdd_nom

slew rate min

slew rate maxkssn - table

Manfred M


Overview

SSN 2000

kssn - table

EnhancedVCCS model

Summary

DDR2 buffer Infineon Supply voltage drop ( L=2x1nH) / Load Tline Zo=50 Ohm

IBISVCCS + kssn

Transistor based

kssn - table

w/o pkg

w/ pkg

Manfred M


Overview

SSN 2000

kssn - table

EnhancedVCCS model

Summary

TI CDCE706 / Voltage drop / Rising edgeVCCS-model with kssn table ( L=2x3nH)

IBIS /HSPICE@ NO PKG VCCS + kssn

transistor based model

VCCS + kssn

transistor based model

kssn - table

Manfred M


Overview

SSN 2000

kssn - table

EnhancedVCCS model

Summary

TI CDCE706 Rising edge vs. Vdd dropTransistor based model

kssn - table

Vdd dropL=1nH …9nH

Vdd=3.3V

Sig.@Vdd=3.3V

Sig.@Vdd drop

Manfred M


Overview

SSN 2000

kssn - table

EnhancedVCCS model

Summary

TI CDCE706 Falling edge vs. Vdd dropTransistor based model

kssn - table

Vdd dropL=1nH …9nH

Vdd=3.3V

Sig.@Vdd=3.3V

Sig.@Vdd drop

Manfred M


Overview

SSN 2000

kssn - table

EnhancedVCCS model

Summary

Differences VCCS 2000 vs. 2006

VCCS 2000 VCCS 2006VCCS 2000 VCCS 2006TransitionTransition Time Time ca. 5nsca. 5ns <500ps <500ps

Operation PointOperation Point saturationsaturation regionregion linear linear regionregion

VddVdd/GND drop/GND drop

amplitudeamplitude ca. 15%Vddca. 15%Vdd ca. 40% ca. 40% VddVdd

widthwidth ca. 7nsca. 7ns ca. 1nsca. 1ns

Design of Design of thethe OUTPUT OUTPUT stagestage

Time Time domainsdomains NONO YESYES

SlewSlew rate rate controlcontrol NO/YESNO/YES YESYES

VddVdd--dropdrop FeedFeed back NOback NO YESYES

PrestagePrestage @@Vdd_intVdd_int NO/YESNO/YES YESYES

OnOn--diedie capacitancecapacitance NO NO YESYES

kssn - table

Manfred M


Overview

SSN 2000

kssn - table

EnhancedVCCS model

Summary

Improvement with prestage capacitance Cpre

EnhancedVCCS model



Ipc(Vout)

Igc(Vout)

C_comp/2

C_comp/2

OUT

VSS

VDD

Cpre

Cpre:Vdd-Vss prestageCapacitance

Evaluation:SPICE simulation usinga capacitance bridge

Cpre:Vdd-Vss prestageCapacitance

Evaluation:SPICE simulation usinga capacitance bridge

Manfred M


Overview

SSN 2000

kssn - table

EnhancedVCCS model

Summary

Vdd drop improvement with Cpre=30pFCDCE706 with PKG L=2x3nH 10 SSO

EnhancedVCCS model

Manfred M


Overview

SSN 2000

kssn - table

EnhancedVCCS model

Summary

Enhanced VCCS-Behavior Modelwith kssn (static) and td_RC (dynamic) coefficients



Ipc(Vout)

Igc(Vout)

C_comp/2

C_comp/2

OUT

VSS

VDD

td_RCr(Vdd-Vss) *

td_RCf(Vdd-Vss) *

td_RC determination

-by optimisation throughthe Vdd_drop @ known L

- by adjustment fromI=I(t) table @ L

td_RC determination

-by optimisation throughthe Vdd_drop @ known L

- by adjustment fromI=I(t) table @ L

EnhancedVCCS model

Manfred M


Overview

SSN 2000

kssn - table

EnhancedVCCS model

Summary

Vdd drop improvementDDR2 with PKG L=2x3nH 5 SSO

EnhancedVCCS model

Manfred M


Overview

SSN 2000

kssn - table

EnhancedVCCS model

Summary

Vdd drop improvementCDCE706 with PKG L=2x3nH 10 SSO

EnhancedVCCS model

Manfred M


Overview

SSN 2000

kssn - table

EnhancedVCCS model

Summary

Summary

Summary

WithWith improvedimproved IBIS IBIS modelsmodels, SSO , SSO cancan bebe simulatedsimulated in a in a betterbetterconcordanceconcordance withwith transistortransistor basedbased modelsmodels, , IFIF

kssnkssn –– tabletable informationinformation (BIRD 97.x)(BIRD 97.x)

currentcurrent vs. time vs. time tablestables @ @ knownknown RLC RLC environmentenvironment (BIRD 95)(BIRD 95)

Advantages Advantages

Signal Signal integrityintegrity analysisanalysis

PDS PDS –– VoltageVoltage drop drop

Timing Timing simulationsimulation

More investigations have to be done, to evaluate for different More investigations have to be done, to evaluate for different technologies, the validity range and the accuracy of the proposetechnologies, the validity range and the accuracy of the proposed d improvementimprovement

Manfred M


Overview

SSN 2000

kssn - table

EnhancedVCCS model

Summary

Industrial Solutions and ServicesYour Success is Our Goal

Questions

SSO Simulation with IBISManfred [email protected]

sso simulation with ibis · kpd(t)*ipd(vout) ipc(vout) igc(vout) c_comp/2 c_comp/2 out vss vdd...

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