Stateflow Toolbox

Stateflow® is an environment for modeling and simulating combinatorial and sequential decision logic based on state machines and flow charts. Stateflow lets you combine graphical and tabular representations, including state transition diagrams, flow charts, state transition tables, and truth tables, to model how your system reacts to events, time-based conditions, and external input signals.

With Stateflow you can design logic for supervisory control, task scheduling, and fault management applications. Stateflow includes state machine animation and static and run-time checks for testing design consistency and completeness before implementation.

Sum of Product

332211 xaxaxaY ***

(Simulink/Stateflow method)

Verilog codeSimulink/Stateflow method

Limitations

Stateflow has a large number of features, some of which may never have reasonable hardware implementations. Other features,while feasible to implement in hardware, were not supported by HDL simulink Coder for the sake of keeping the code simple. The limitations of SF2VHD are on thenumber and types of objects in HDL library. The next two subsections outline all these limitations, including why they were left out and any suggestions forfuture implementation if the need arises.

Future work

SVPWM

DCPower

PMSM

PIIGBT-base

Inverter

PWM1

0* di

qi

di

Park-1modifyClark-1

PWM6

—

—++

—

PWM2PWM3PWM4PWM5PI

1refv

3refv2refvqv

dvvv

*qi

r

*r

+ a,b,c

,d,q

,

Current controller

PIController

Current controller and coodinate transformation

Modelsim

Park Clark

i

ibici,

d,q ,

a,b,c

sin /cos of Flux angle

e Flux angleTransform.

ai

Simulink

A B C

r

References

1. Davis, W. R. BWRC IC Design Flow Concept Slides. 2000.2. Davis, W. R. SSHAFT Manifesto.http://bwrc.eecs.berkeley.edu/Research/IC_Design_Flow/Flow. 2000.3. Harel, D. StateCharts: A Visual Formalism for Complex Systems. Sci. Comput.Programs, 8:231-274. 1987.4. The MathWorks, Inc. Using Stateflow. 1999.5. Husted, P. Design and Implementation of Digital Timing Recovery and CarrierSynchronization for High Speed Wireless Communications. Masters thesis, Departmentof Electrical Engineering and Computer Science, U. C. Berkeley. 2000.6. Ammer, J. and Sheets, M. Timing Recovery Unit For a 1.6Mbps DSSS Receiver.EE225C Final Project, Department of Electrical Engineering and Computer Science, U. C.Berkeley. 2000.

Thanks for attention!