static techniques for v&v

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Static Techniques for V&V

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Static Techniques for V&V. Hierarchy of V&V techniques. V&V. Dynamic Techniques. Static Techniques. Informal Analysis. Formal Analysis. Testing. Symbolic Execution. Simulation. Model Checking. Static Analysis. Walkthrough. Inspection. Proofs. Review. Analysis. - PowerPoint PPT Presentation

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Page 1: Static Techniques for V&V

Static Techniques for V&V

Page 2: Static Techniques for V&V

Hierarchy of V&V techniques

Static Analysis

V&V

Dynamic Techniques

Model Checking

Simulation

SymbolicExecution

Testing InformalAnalysis

FormalAnalysis

Static Techniques

Proofs Review

Inspection

Walkthrough

Page 3: Static Techniques for V&V

Analysis

• Different from experimenting (testing).

–  • Based on a model

– Source code or abstracted source code– Not the actual product (executable).

Page 4: Static Techniques for V&V

Analysis• Can be subject to failure itself (wrong

proof)– Similar to mathematical proofs– Start with conjecture– Try to show it is a theorem

• Find either

Page 5: Static Techniques for V&V

Informal Analysis

• Reviews• Inspections• Walkthroughs

Page 6: Static Techniques for V&V

Code Reviews:

• Read. If you can’t read it, neither can the people trying to maintain it

• Do this for any artifact

• This is a team effort

Page 7: Static Techniques for V&V

Walk-through:• Simulate by hand, pick test cases, generalize• Looking for any bugs• Keep size small (3-5)• Players get documentation ahead of time• Meeting is restricted to a few hours

Page 8: Static Techniques for V&V

Code Inspections:

• Looking for specific bugs• Common bugs:

– Un-initialized variables– Jumps into loops– Incompatible assignments (type errors)– Non-termination– Out-of-bounds– Memory leaks– Parameter mismatches

Page 9: Static Techniques for V&V

(Semi) Formal Analysis Techniques

• Proofs• Static checking

– Code analysis: syntax errors and simple error patterns (i.e. Pointer problems)

– Structure checking: CFGs with structural error detection (dead code, logic errors)

Page 10: Static Techniques for V&V

Formal correctness proofs

{true}Begin

read (a);read (b);x = a + b;write (x)

end;{output = input1 + input2}

Precondition

Post condition

Page 11: Static Techniques for V&V

Proof Step 1

{true}Begin

read (a);read (b);x = a + b;write (x)

end;{output = input1 + input2}

Due to the semantics of write(), the post condition holds iff {x=input1 + input2} holds

Page 12: Static Techniques for V&V

Proof Step 2

{true}Begin

read (a);read (b);x = a + b;write (x)

end;{output = input1 + input2}

{x=input1 + input2} holds iff {a+b = input1 + input2}

Page 13: Static Techniques for V&V

Proof Step 3

{true}Begin

read (a);read (b);x = a + b;write (x)

end;{output = input1 + input2}

Since the semantics of read(a) and read(b) assign input1 to a and input2 to b, {a+b = input1 + input2} holds

Page 14: Static Techniques for V&V

Basic Idea

• For any postcondition POST on program variables, and

• For any assignment statement x = expr,– expr is an expression containing variables

• POST holds after the assignment iff POST’ holds before the assignment

Page 15: Static Techniques for V&V

Basic Idea

• We want to show that whenever the preconditions hold, the postconditions must hold, that is – Pre -> Post

• We can take post conditions and derive necessary and sufficient conditions, then show the preconditions match these.

Page 16: Static Techniques for V&V

Notes

• We assume there are no side effects in expr.

Page 17: Static Techniques for V&V

Consider examples

• {x = 5} x = x + 1 {x = 6}

• {z-43 > y + 7} x = z – 43 {x > y + 7}

Page 18: Static Techniques for V&V

Sequences

• Suppose you have shown {F1} S1 {F2} and {F2} S2 {F3}

• You can deduce– {F1} S1;S2 {F3}

Page 19: Static Techniques for V&V

Consider conditional:

{true}if x >= y then

max = xelse

max = y;{ (max = x or max = y) AND (max >= x and max >= y) }

Page 20: Static Techniques for V&V

Proof informally by cases:

 assume x >= y.then { (x = x or x = y) AND (x >= x and x >= y) },

which is true.

Page 21: Static Techniques for V&V

Rules of inference, conditional:

• Given {pre and condition} s1 {post} and {pre and not condition} s2 {post}

• Infer{pre} if condition then s1 else s2 {post}

Page 22: Static Techniques for V&V

Loop invariants

• I is a loop invariant• cond is the loop condition (while loop)• S is the body of the loop

Page 23: Static Techniques for V&V

Loop example:

{x > y}while (x <> 0)

x = x –2y = y –2

end while{x > y and x = 0}

Invariant

Page 24: Static Techniques for V&V

Loop example:

{x > y}while (x <> 0)

x = x –2y = y –2

end while{x > y and x = 0}

Note: Loop is not guaranteed to terminate

Page 25: Static Techniques for V&V

Loops example:

• Can easily show that if x > y at exit, it must have been so at entry.

• Might need induction to do these in general.• Notice, this loop does not end if x is odd on

entry.

Page 26: Static Techniques for V&V

Example {input1>0 and input2>0}beginread(x); read(y); div=0;while x>=y loopdiv = div + 1;x = x – y;end loop;write (div); write (x);

end{input1 = output1*input2 + output2 and 0<=output2<input2}

Page 27: Static Techniques for V&V

Notes:

• Formal proofs may be more complex than the program

• Proofs are error prone if done by hand• Proofs require mathematical sophistication• Proofs may be overwhelming to do

Page 28: Static Techniques for V&V

Notes 2:• Proofs rely on a semantic model of the

environment (language, processor): They only provide assurance under this model

• Proofs may depend on continuous systems, not discrete systems

• Are they useful?– only for very small parts of the code.– they can be automated (PVS, for example)

• Many research issues here

Page 29: Static Techniques for V&V

Notes 3

• Automated Theorem Provers: ACL2, HOL, Isabelle, Clam/Oyster– Theorem proving frameworks for software

• Outline:

Page 30: Static Techniques for V&V

Symbolic execution

• Similar to testing, but instead of individual test cases, you have symbolic generalization

• each test is a test of an entire class of tests. (testing, one element of equiv class. symbolic, entire class).

• Plan: try to get path coverage. How? In general, abstract the source code with respect to some property. Then do symbolic execution of every path through abstracted code.

• Research problem. 

Page 31: Static Techniques for V&V

Model Checking

• Exhaustive search through state space of program (complete state space expansion)

• Form of symbolic execution• Problem: state space

Page 32: Static Techniques for V&V

Model Checker

• Model software as FSA (what’s that?)• Model properties in some logic, usually

temporal logic (LTL, CTL)• Represent FSA as a graph (what’s that?)• Traverse graph (how?)• Show properties hold in each node of graph

Page 33: Static Techniques for V&V

Model Checking

• What does it mean if an assertion does not hold in the model?

• What does it mean if the assertion does hold in the model?

Page 34: Static Techniques for V&V

Automated Programming

• Automatically generate programs from specifications

• Deductive Synthesis: extract a program from a proof

Page 35: Static Techniques for V&V

Cleanroom

• Build software in such a way as to prevent defects from being introduced. No testing.

• Specify system.• Refine specification systematically, proving

that the refinement meets the specification

Page 36: Static Techniques for V&V

Transformational Programming

• Take an input string and rewrite it:– aBc => axyc– Rules can have conditions – Rules can have procedural attachment or be higher

order• Formal, stepwise refinement of specification to

program• Can check each step individually• “correct” by construction