status of knowledge on non-binary ldpc decoders part ii
TRANSCRIPT
Status of Knowledge on Non-Binary LDPC DecodersPart II: Reduced Complexity Non-Binary Decoders
D. Declercq 1
1ETIS - UMR8051ENSEA/Cergy-University/CNRS
France
IEEE SSC SCV Tutorial, Santa Clara, October 21st, 2010
D. Declercq (ETIS - UMR8051) 1 / 56
Outline
1 Extended Min-Sum Decoding of NB-LDPC Codes
2 Further Refinements and ASIC Implementation
3 Analysis and Optimal Correction of the NB-LDPC decoders
4 Alternative Decoders: the Min-Max Decoder
5 Alternative Decoders: Symbol Flipping Decoder
6 Alternative Decoders: Non-Binary Stochastic Decoder
7 General Conclusion on Simplified Non-Binary Decoding
D. Declercq (ETIS - UMR8051) 2 / 56
Bibliography of Low Complexity Decoders (1)
The bottleneck of the decoder complexity is the check node update
Extended Min-Sum Decoding[Declercq,2007] D. DECLERCQ AND M. FOSSORIER, “DECODING ALGORITHMS FOR NONBINARY LDPC CODES OVER
GF(Q)”, IEEE Transactions on communication, VOL. 55(4), PP. 633-643, APRIL 2007
[Voicila,2008] A. VOICILA, D. DECLERCQ, F. VERDIER, M. FOSSORIER AND P. URARD, “ARCHITECTURE OF A
NON-BINARY LDPC DECODER FOR THE NEXT GENERATION CODING SYSTEMS”, Proceedings of IEEE International
Conference on Consumer Electronics (ICCE), LAS VEGAS, USA, JAN. 2008
[Voicila,2010] A. VOICILA, D. DECLERCQ, F. VERDIER, M. FOSSORIER AND P. URARD, “LOW COMPLEXITY DECODING
ALGORITHM FOR NON-BINARY LDPC CODES IN HIGH ORDER FIELDS”, IEEE Transactions on communication, VOL. 58(5),
MAY 2010.
[Boutillon,2010] E. BOUTILLON AND L. CONDE-CANENCIA, “BUBBLE CHECK: A SIMPLIFIED ALGORITHM FOR
ELEMENTARY CHECK NODE PROCESSING IN EXTENDED MIN-SUM NON-BINARY LDPC DECODERS”, IEE Electronics
Letters, VOL. 46(9) PP. 633-634, APRIL 2010.
D. Declercq (ETIS - UMR8051) 3 / 56
Bibliography of Low Complexity Decoders (2)
Min-Max Decoding[Savin,2008] V. SAVIN, “MIN-MAX DECODING FOR NON BINARY LDPC CODES”, Proceedings of ISIT’08, TORONTO,
CANADA, JULY 2008.
[Lin,2010] J. LIN, J. SHA, Z. WANG AND L. LI, “EFFICIENT DECODER DESIGN FOR NONBINARY QUASICYCLIC LDPC
CODES”, IEEE Transactions on Circuits and Systems, VOL.57(5), PP 1071–1082, MAY 2010.
Symbol Flipping Decoding[Kuo,2006] F.-C. KUO AND L. HANZO, “SYMBOL FLIPPING BASED DECODING OF GENERALIZED LOW DENSITY PARITY
CHECK CODES OVER GF(Q)”,Proceedings of IEEE WCNC’06, LAS-VEGAS, NV, APRIL, 2006.
[Liu,2010] B. LIU, J. GAO, G.DOU AND W. TAO, “WEIGHTED SYMBOL-FLIPPING DECODING FOR NONBINARY LDPC
CODES”, Int. Conf. on Network Security, Wireless Communications and Trusted Computing, WUHAN, HUBEI, CHINA,
APRIL 2010.
Stochastic Decoding[Sarkis,2009] G. SARKIS, S. MANNOR AND W.J. GROSS, “STOCHASTIC DECODING OF LDPC CODES OVER GF(Q)”,
Proceedings of IEEE ICC’09, DRESDEN, GERMANY, JUNE 2009.
D. Declercq (ETIS - UMR8051) 4 / 56
Outline
1 Extended Min-Sum Decoding of NB-LDPC Codes
2 Further Refinements and ASIC Implementation
3 Analysis and Optimal Correction of the NB-LDPC decoders
4 Alternative Decoders: the Min-Max Decoder
5 Alternative Decoders: Symbol Flipping Decoder
6 Alternative Decoders: Non-Binary Stochastic Decoder
7 General Conclusion on Simplified Non-Binary Decoding
D. Declercq (ETIS - UMR8051) 5 / 56
Complexity of BP-based decoders are too highIdea : Truncated messages
Objective: reduce the complexity of O(q2) while staying in the Log-Domain
Messages are composed of q Log-Density Ratios (LDR)
with GF (q) =˘
0, α0, α1, . . . , αq−2¯ =˘
0, α1, α2, . . . , αq−1¯
U(αk ) = logµc → p[αk ]
µc → p[0]∀k = 0, . . . , q − 1
We proposed a decoding algorithm, called extended min-sum (EMS), which stores only alimited number nm � q of reliabilities in the vector messages
n
q
values
values
m
dc−1 Input Edges Output Edge
nm
values
D. Declercq (ETIS - UMR8051) 6 / 56
Compensation of the Truncated Messages (1)
First, the values in a message are sorted in decreasing order so that the kept valuescorrespond to the maximum reliabilities.
Let A be a size q LDR vector. We compensate the q − nm truncated values of A with asingle scalar value γA, which is the simplest model one can use to build the truncatedvector B (size nm)
Note that in principle γA depends on the values in the message A.
The truncated version B of A is composed of the nm largest values of A sorted indecreasing order:
A = [A[0] . . .A[nm − 1] . . .A[q − 1]]T
−−−−−−−→Truncation B = [B[0] . . .B[nm − 1] γA . . . γA]T
D. Declercq (ETIS - UMR8051) 7 / 56
Compensation of the truncated messages (2)How to choose γA ?
Let PA/PB be the probability domain versions of A/B:
PA[k ] = PA[0]eA[k ] k ∈ {0, . . . , q − 1} PB [k ] = PA[0]eB[k ] k ∈ {0, . . . , nm − 1}
clearly:q−1Xk=0
PA[k ] = 1nm−1Xk=0
PB [k ] < 1
choose γA such thatnm−1Xk=0
PB [k ] + (q − nm)PγA = 1
γA = max ∗ (A[nm], . . . ,A[q − 1])− log(q − nm)
so, in a first order approximation, we can choose:
γA = A[nm − 1]− log(q − nm)− offset
D. Declercq (ETIS - UMR8051) 8 / 56
New Definition of a MessageLet’s take the exemple of GF(8) and nm = 4.
with GF (q) =˘
0, α0, α1, . . . , αq−2¯ =˘
0, α1, α2, . . . , αq−1¯
2666666666666666666666666666664
0 = log µ(0)µ(0)
U[α1] = log µ(α1)µ(0)
U[α2] = log µ(α2)µ(0)
U[α3] = log µ(α3)µ(0)
U[α4] = log µ(α4)µ(0)
U[α5] = log µ(α5)µ(0)
U[α6] = log µ(α6)µ(0)
U[α7] = log µ(α7)µ(0)
3777777777777777777777777777775
⇒
U2666666666664
U[α3]
U[α7]
U[α1]
U[α4]
3777777777775
β2666666666664
α3
α7
α1
α4
3777777777775h 1c1
c1 c2 c3
h 3c3h 2c2
vp v
v pu
p cu vc p
n =4m
Permutation
Nodes
+
D. Declercq (ETIS - UMR8051) 9 / 56
Description of the EMS algorithmVariable Node Update
dv−1 Input Edges
Output Edge
Option 1 Option 2
Truncate
ci
Udv [αk ] = Lch[αk ] +
dv−1Xi=1
Vi [αk ]
k ∈ {0, . . . , q − 1}
Vi [αk ] =
Vi [αk ] if αk ∈ βViγVi
if αk /∈ βVi
Complexity O(nm dv + nm log(q) dv ): still too large !
Complexity can be reduced without significant loss to O(nm log(nm) dv ) with intermediatetruncations and recursive implementation.
D. Declercq (ETIS - UMR8051) 10 / 56
Description of the EMS algorithmVariable Node Update: special case of dv = 2
Output Edge
Single Input Edge
Option 1 Option 2
ci
U2[β2(k)] = Lch[β2(k)] + V1[β2(k)]
if β2(k) ∈ β1
U2[β2(k)] = Lch[β2(k)] + γV1
if β2(k) /∈ β1
k ∈ {0, . . . , nm − 1}
worst case complexity O(nm log(nm)), or average complexity O(nm + δ).
D. Declercq (ETIS - UMR8051) 11 / 56
Description of the EMS algorithmThe permutation step
c i
c ih ij
Uout [βout (k)] = U in[β in(k)]
βout [k ] = hij βin[k ]
k ∈ {0, . . . , nm − 1}
Since the message is now composed with the indices β, the permutation step is just acomputation of the new indices hij β
D. Declercq (ETIS - UMR8051) 12 / 56
Parity Check Node UpdateNotion of Elementary Step
The bottleneck of the decoder complexity is the check node update
One Elementary Check Node Update corresponds to 2 input edges only.
c 1h1
c 2h2
c 3h3
V3[β3[k ]] = max(i,j)∈{0..nm−1}2
(U1[β1[i]] + U2[β2[j]])
such that β3[k ]⊕ β1[i]⊕ β2[j] = 0
k ∈ {0, . . . , nm}
Brute force complexity of this step is O(n2m + nm log(nm)).
D. Declercq (ETIS - UMR8051) 13 / 56
Parity Check Node Update with dc = 5Forward/Backward implementation from elementary steps
p c1
U
p c1
U
size nm
size nm
size nm
size nm size nm
size nm size nm
size nm
size nm
size nm
c V5
p size nm
size nm
size nm
size nm
size nm
size nm
size nm
size nm
size nm p cU2
size nm U size nm I
size nm V
Backward
Forward
c V2
1 c V
c V4
p
p
p
BI 1 2
FI 1 2FI 1 1
3 c V p
U p c5
U p c5
p cU4
p cU4
U p c3
U p c3
1BI 1
2 3 4 5h v h v h v h v
p cU2
1h v1 2 3 4 5
(a) (b)
D. Declercq (ETIS - UMR8051) 14 / 56
Reduced Complexity Algorithm for ElementaryCheck-Node
One elementary step assumes only two input messages U, I of size nm and one outputmessage V of size nm.
We assume here a serial architecture, i.e. which aims at filling the nm outputs of theElementary CheckNode in nm steps.
What is the minimum number of operations needed ?
[Voicila,2010] A. VOICILA, D. DECLERCQ, F. VERDIER, M. FOSSORIER AND P. URARD, “LOW COMPLEXITY DECODING
ALGORITHM FOR NON-BINARY LDPC CODES IN HIGH ORDER FIELDS”, IEEE Transactions on communication, VOL. 58(5), MAY
2010.
D. Declercq (ETIS - UMR8051) 15 / 56
Reduced Complexity Algorithm for ElementaryCheck-NodeInitialization
V
U
I
GF adder
D. Declercq (ETIS - UMR8051) 16 / 56
Reduced Complexity Algorithm for ElementaryCheck-NodeFirst output value
GF adder
U
I
V
D. Declercq (ETIS - UMR8051) 17 / 56
Reduced Complexity Algorithm for ElementaryCheck-NodeSecond output value
GF adder
U
I
V
D. Declercq (ETIS - UMR8051) 18 / 56
Reduced Complexity Algorithm for ElementaryCheck-Nodek − th output value
GF adder
U
I
V
The 6th output corresponds
to an entry already filled
D. Declercq (ETIS - UMR8051) 19 / 56
Reduced Complexity Algorithm for ElementaryCheck-Nodek − th output value
GF adder
U
I
V
D. Declercq (ETIS - UMR8051) 20 / 56
Minimum Complexity Algorithm for ElementaryCheck-NodeHow many candidates need to be consirered at each step ?
Let us denote the possible candidates at step k of the elementary check-node algorithm asbubbles,
We allow the moves of the bubbles to be both horizontal or vertical,
Let us remove the un-necessary candidates from the previous algorithm.
[Boutillon,2010] E. BOUTILLON AND L. CONDE-CANENCIA, “BUBBLE CHECK: A SIMPLIFIED ALGORITHM FOR ELEMENTARY
CHECK NODE PROCESSING IN EXTENDED MIN-SUM NON-BINARY LDPC DECODERS”, IEE Electronics Letters, VOL. 46(9) PP.
633-634, APRIL 2010.
D. Declercq (ETIS - UMR8051) 21 / 56
Minimum Complexity Algorithm for ElementaryCheck-NodeWorst case scenario
Maximum number of bubbles: triangular shape,
Extraction of the k th value: comparison with a maximum of Ψ(k) candidates,
with a memory buffer of size Ψ(k), the elementary update needs nm + δ steps.
Ψ(k) =
&1 +
p1 + 8(k − 1)
2
’
[Boutillon,2010] E. BOUTILLON AND L. CONDE-CANENCIA, “BUBBLE CHECK: A SIMPLIFIED ALGORITHM FOR ELEMENTARY
CHECK NODE PROCESSING IN EXTENDED MIN-SUM NON-BINARY LDPC DECODERS”, IEE Electronics Letters, VOL. 46(9) PP.
633-634, APRIL 2010.
D. Declercq (ETIS - UMR8051) 22 / 56
Complexity and Memory Evaluation of EMSWorst Case scenario
The bubble algorithm can be used as well for the variable node update.
The Worst Case complexity of EMS algorithm is dominated by O(nm log(nm)) for bothparity and variable nodes computation
No. max No. real add. No. GF(q) add.
Check Node 3(dc − 2)nm log(nm) 3(dc − 2)(2 nm) 3(dc − 2)(2 nm)
Variable Node (dv + 2(dv − 2))nm log(nm) (dv + 2(dv − 2))(2 nm) 0
Permutation Node 0 0 nm(dv + dc )
The Average complexity of EMS algorithm is O(nm + δ)
The edge memory scales as N ∗ dv ∗ nm ∗ (Nbits + log2 q) bits
D. Declercq (ETIS - UMR8051) 23 / 56
Performance of the EMS vs. Non-Binary BP
The EMS GF(64) nm = 32 algorithm has 0.05dB performance loss in the waterfall regionand performs even better than the BP decoder in the error floor region.
1 1.2 1.4 1.6 1.8 2 2.2 2.4 2.6 2.8 310
−8
10−7
10−6
10−5
10−4
10−3
10−2
10−1
100
Eb/N0 (in db)
FE
R
EMS GF(64) nm=16
BP GF(64)
BP GF(256)
EMS GF(256) nm=32
EMS GF(64) nm=32
R=1/2,dv = 2, dc = 4Nb ≈ 848 bits
D. Declercq (ETIS - UMR8051) 24 / 56
Performance vs. Binary LDPC codes
EMS vs binary MS algorithm,
LDPC code (R=0.5, Nb=504 bits),
BI-AWGN channel
1 1.5 2 2.5 3 3.5 410
−8
10−7
10−6
10−5
10−4
10−3
10−2
10−1
100
Eb/N0 (in dB)
FER
EMS GF(64) nm=6MS binary correctedEMS GF(64) nm=12EMS GF(64) nm=18
EMS vs binary MS algorithm,
LDPC code (R=0.5, Nb=1008 bits),
256-QAM-AWGN channel
8 8.5 9 9.5 10 10.5 11 11.5 12 12.510
−7
10−6
10−5
10−4
10−3
10−2
10−1
100
Eb/N0 (in dB)FE
R
EMS GF(256) nm=6
EMS GF(256) nm=12
EMS GF(256) nm=18
EMS GF(256) nm=36
MS binary corrected
D. Declercq (ETIS - UMR8051) 25 / 56
Conclusions
∆! Like the Binary Min-Sum, the EMS needs to be compensated by an offset ∆!
The EMS is the best known low complexity decoding algorithm for non binary LDPC codes.
The main originality of the proposed algorithm is to truncate the vector messages to a fixednumber of values nm � q.
The complexity of the proposed algorithm is dominated by O(nm log2(nm))
The EMS decoding algorithm can approach the performance of the BP decoder and evenin some cases beat the BP decoder.
The proposed low complexity, low memory EMS decoding algorithm becomes a goodcandidate for the hardware implementation of non binary LDPC decoders.
D. Declercq (ETIS - UMR8051) 26 / 56
Outline
1 Extended Min-Sum Decoding of NB-LDPC Codes
2 Further Refinements and ASIC Implementation
3 Analysis and Optimal Correction of the NB-LDPC decoders
4 Alternative Decoders: the Min-Max Decoder
5 Alternative Decoders: Symbol Flipping Decoder
6 Alternative Decoders: Non-Binary Stochastic Decoder
7 General Conclusion on Simplified Non-Binary Decoding
D. Declercq (ETIS - UMR8051) 27 / 56
The DAVINCI project
The DAVINCI Project
European projet funded by the 7th-Framework-Program of the European Commission(http://www.ict-davinci-codes.eu/),
Consortia Partners: Samsung-UK, ENSEA, ST-Microelectronics, IMEC, univ.Bretagne-sud, CTTC, WISER, ITTI,
David Declercq scientific coordinator of the project.
Outcomes of the Project
QC-LDPC Code Design adapted for parallel implementation of the decoder and linearencoding,
Refinements of the EMS decoder (bubble-check algorithm, new definition of messages),
Hardware model with increased degree of parallelism.
D. Declercq (ETIS - UMR8051) 28 / 56
Slightly Modified Definition of the Messages
Messages are composed of q Log-Density Ratios (LDR)
U(αk ) = logµc → p[α∗]
µc → p[αk ]∀k = 0, . . . , q − 1
such that U(α∗) ≥ U(αk ), ∀k .the definition of the LDR depends on the message !not a problem for the EMS since the indices are stored in the message,With this new definition, we need only Nbit = 5 bits of quantization for each LDR value.
D. Declercq (ETIS - UMR8051) 29 / 56
ST-Microelectronics ASIC implementationPower Estimation
Power estimation done at gate netlist level
Based on real simulation patterns, in different modes and SNR conditions
Passive/active phases of the LDPC decoding taken into account
Mode Mode 1N=96
Mode 2N=192
Mode 3N=288
Mode 4N=384
FER3.3E-4 1.3E-4 < 1E-5 < 1E-5
Mean n.o. iterations3.72 4.03 4.23 4.38
Mean frame power (W)0.0986 0.101 0.103 0.104
Consumption (µJ)0.284 0.583 0.89 1.2
~ 100 mW in continuous reception
D. Declercq (ETIS - UMR8051) 30 / 56
ST-Microelectronics ASIC implementationChip Area
Post-synthesis area: 1.28 mm2 on a 45nm technology
100 Mbits/s worst case throughput (user throughput) @ 300 MHz clock
C. Liu [7] T. Brack [8] G. Gentile [9]DaVinci decoder
ASIC version
Code length (bits) 576-2304 576-2304 576-2304 288-2880
F clock (MHz) 150 333 400 300
Iterations 20 10-15 15 18
throughput 105 133-928 128-746 100-200
Technology 90 nm 130 nm 65 nm 45 nm
area 6.25 3.83 0.59 1.28
Area equiv. 45nm 1.56 0.48 0.3 1.28
x4 area
D. Declercq (ETIS - UMR8051) 31 / 56
Outline
1 Extended Min-Sum Decoding of NB-LDPC Codes
2 Further Refinements and ASIC Implementation
3 Analysis and Optimal Correction of the NB-LDPC decoders
4 Alternative Decoders: the Min-Max Decoder
5 Alternative Decoders: Symbol Flipping Decoder
6 Alternative Decoders: Non-Binary Stochastic Decoder
7 General Conclusion on Simplified Non-Binary Decoding
D. Declercq (ETIS - UMR8051) 32 / 56
The Role Model Framework
For small values of nm, very precice compensation of the EMS decoder is an issue
A single offset correction might not be powerfull enough:
1 compensation for the truncation of messages,2 compensation for the max operator instead of max∗,3 compensation for the truncation of intermediate messages during the
Forward/Backward recursion,4 compensation for the presence of cycles in the Tanner graph.
Motivation: make use of a theoretical framework for the optimal design ofreduced-complexity receiver components operating on finite precision messages
General Idea: Let’s assume that one can have access to the Bayesian optimumreceiver/decoder outputs, which will serve as Role Model.
[Sayir,2010] J. SAYIR, “DESIGN OF NON-BINARY DECODERS USING THE ROLE MODEL FRAMEWORK”, proceedings of the
ISTC’10, BREST, FRANCE, SEPTEMBER 2010.
D. Declercq (ETIS - UMR8051) 33 / 56
Classical Design of Receiver Components
ChannelSource Bayesian EstimatorX
Y1
Y2
Y3
PX|Y1Y2Y3
X !1
X !2
Bayesian Estimation
Advantages:Guarantees optimalityCan be repeated at will in a classical serial or iterative message-passing setup
Drawbacks:Calculates probabilities, i.e., real numbersOperations can be overly complex (e.g. MIMO MAP detector, Non-Binary LDPCdecoder)
D. Declercq (ETIS - UMR8051) 34 / 56
Practical Implementation of Receiver Algorithms
Impact of Hardware Implementation with Finite Precision, Reduced Complexity
Bayesian operations are replaced by simpler alternatives
⇒ Approximate Bayesian estimation
Loss of optimality (even under constraints)
Often, we turn to an heuristic decoder design by simulation.
D. Declercq (ETIS - UMR8051) 35 / 56
Approach by Constrained Optimization
ChannelSourceLow Complexity
Component (non-Bayesian)
X
Y1
Y2
Y3
X !1
X !2
BayesianPost-Processing
PX|ZZ
Bayesian Post-Processing
Optimal under constraints, given the low complexity component
Can be derived analytically for simple components (e.g. Min-Sum decoder for binary LDPCcodes)
Allow to consider elaborate parametrized correction functions (vector, non-linear, adaptive,etc) and to optimize the parameters offline.
D. Declercq (ETIS - UMR8051) 36 / 56
Role Model Estimation
Source Estimatorin TrainingChannel
Low ComplexityComponent
XY Z = f(Y )
BayesianRole ModelEstimator
QX|Z
PX|Y
X !1
X !2
arg minQX|ZEPYZ
ˆDKL(PX |Y ||QX |Z )
˜= PX |Z
This is convex optimization problem: optimum values of the parameters exist.
The issue is to choose an efficient model for EMS correction/compensation.
With the simple model γA = A[nm − 1]− log(q − nm)− offset , the Role Model frameworkgives the same offset value as the ones we got by Monte Carlo simulation.
D. Declercq (ETIS - UMR8051) 37 / 56
Outline
1 Extended Min-Sum Decoding of NB-LDPC Codes
2 Further Refinements and ASIC Implementation
3 Analysis and Optimal Correction of the NB-LDPC decoders
4 Alternative Decoders: the Min-Max Decoder
5 Alternative Decoders: Symbol Flipping Decoder
6 Alternative Decoders: Non-Binary Stochastic Decoder
7 General Conclusion on Simplified Non-Binary Decoding
D. Declercq (ETIS - UMR8051) 38 / 56
Alternative to the EMS: the Min-Max decoder
Messages are composed of q Log-Density Ratios (LDR)
U(αk ) = logµc → p[α∗]
µc → p[αk ]∀k = 0, . . . , q − 1
such that U(α∗) ≥ U(αk ), ∀k .
The EMS step:V3[β3[k ]] = min
(i,j)∈{0..nm−1}2(U1[β1[i]] + U2[β2[j]])
such that β3[k ]⊕ β1[i]⊕ β2[j] = 0
k ∈ {0, . . . , nm}is replaced by:
V3[β3[k ]] = min(i,j)∈{0..q−1}2
(max (U1[β1[i]],U2[β2[j]]))
such that β3[k ]⊕ β1[i]⊕ β2[j] = 0
k ∈ {0, . . . , q − 1}
D. Declercq (ETIS - UMR8051) 39 / 56
Alternative to the EMS: the Min-Max decoderAdvantages
possible to perform a block implementation of the check-node (no Forward/Backward),Throughput is improved compared to the full-complexity Non-Binary Min-Sum decoder,
Drawbacks ?
Throughput is only slightly better than the EMS decoder with nm small enough,Looses more performance in the waterfall than the EMS (0.2dB reported in [Lin,2010] forGF(32) and Nb = 600 bits),Worse robusteness to quantization: [Lin,2010] reports good performance with 7 bits ofquantization.
Advantage ?
Could bring an extra complexity reduction in case of hybrid version Min-Max/EMS ?
[Savin,2008] V. SAVIN, “MIN-MAX DECODING FOR NON BINARY LDPC CODES”, Proceedings of ISIT’08, TORONTO, CANADA,
JULY 2008.
[Lin,2010] J. LIN, J. SHA, Z. WANG AND L. LI, “EFFICIENT DECODER DESIGN FOR NONBINARY QUASICYCLIC LDPC CODES”,
IEEE Transactions on Circuits and Systems, VOL.57(5), PP 1071–1082, MAY 2010.
D. Declercq (ETIS - UMR8051) 40 / 56
Outline
1 Extended Min-Sum Decoding of NB-LDPC Codes
2 Further Refinements and ASIC Implementation
3 Analysis and Optimal Correction of the NB-LDPC decoders
4 Alternative Decoders: the Min-Max Decoder
5 Alternative Decoders: Symbol Flipping Decoder
6 Alternative Decoders: Non-Binary Stochastic Decoder
7 General Conclusion on Simplified Non-Binary Decoding
D. Declercq (ETIS - UMR8051) 41 / 56
Alternative to the EMS: the Symbol Flipping decoder
Messages are now symbols of GF (q) =˘
0, α1, α2, . . . , αq−1¯
: U = αi V = αj
Let us consider the simplest Check-Node update
dc−1 incomming edges
VU
c 1h1
c 2h2
h dc−1
cdc−1
Vdc−1 = U1 ⊕ . . .⊕ Udc−2
Issue is now how to define the variable node update ?
dv−1 Input Edges
Output Edge
Option 1 Option 2
U
L
V
ci
Udv−1 = Vi if all {Vi}i=0..dv−2 are equal
Udv−1 = χ if not
D. Declercq (ETIS - UMR8051) 42 / 56
Alternative to the EMS: the Symbol Flipping decoderDifferent Solutions for the Variable Node update
1 [Gallager,1963]: Random choice of χ ∈ GF(q)\L2 Weighted Symbol Flipping: choose χ according to the channel soft-values,3 Put memory on the edges and choose χ from a previous computed value.
Advantages
Increadibly low complexity hard decoding,Requires minimal storage for the messages values.Complexity added for Weighted Symbol Flipping is low,Could be an alterative to Hard Decoding of Reed-Solomon codes.
Drawbacks
Too simple: performance loss in the waterfall is large: [Liu,2010] report 1.5dB to 2.5dB loss,for very small block-lengths (a hundred symbols).so far, it’s only an alternative to Hard Decoding of Reed-Solomon codes.need more research to decide if weighted symbol flipping is promising.
[Liu,2010] B. LIU, J. GAO, G.DOU AND W. TAO, “WEIGHTED SYMBOL-FLIPPING DECODING FOR NONBINARY LDPC CODES”,
Int. Conf. on Network Security, Wireless Communications and Trusted Computing, WUHAN, HUBEI, CHINA, APRIL 2010.
D. Declercq (ETIS - UMR8051) 43 / 56
Outline
1 Extended Min-Sum Decoding of NB-LDPC Codes
2 Further Refinements and ASIC Implementation
3 Analysis and Optimal Correction of the NB-LDPC decoders
4 Alternative Decoders: the Min-Max Decoder
5 Alternative Decoders: Symbol Flipping Decoder
6 Alternative Decoders: Non-Binary Stochastic Decoder
7 General Conclusion on Simplified Non-Binary Decoding
D. Declercq (ETIS - UMR8051) 44 / 56
Stochastic DecoderList/Vector version of Hard-Decoders
Messages are now lists of symbols of GF (q) =˘
0, α1, α2, . . . , αq−1¯
:
U =˘
U(t)¯t=1...T V =
˘V (t)¯
t=1...T
The occurences of the symbols in the list represent the probabilities of the symbols.
exemple for GF(4) = {0, α1, α2, α3}
µ(0) =9
25µ(1) =
325
µ(2) =1025
µ(3) =3
25
. . . 0 α1 α2 α2 α2 0 0 α3 α1 α1 0 0 0 α2 α3 0 α2 α2 0 α2 0 α3 α2 α2 α2 α2 . . .
Check-Nodes update is restricted to Parity-Check computation (same as symbol-flipping).
D. Declercq (ETIS - UMR8051) 45 / 56
Stochastic Decoder: Variable Nodes (1)Agree or Freeze
Memory
One Step
ci
U(t)dv−1 = V (t)
i if all {Vi} are equal
U(t)dv−1 = U(t−1)
dv−1 if not
D. Declercq (ETIS - UMR8051) 46 / 56
Stochastic Decoder: Variable Nodes (1)Agree or Freeze
Freeze
Memory
One Step
ci
U(t)dv−1 = V (t)
i if all {Vi} are equal
U(t)dv−1 = U(t−1)
dv−1 if not
D. Declercq (ETIS - UMR8051) 47 / 56
Stochastic Decoder: Variable Nodes (2)Agree or Memory
Memory
Edge
ci
U(t)dv−1 = V (t)
i if all {Vi} are equal
U(t)dv−1 = U(t−τ(ω))
dv−1 if not
D. Declercq (ETIS - UMR8051) 48 / 56
Stochastic Decoder: Variable Nodes (2)Agree or Memory
Freeze
Memory
Edge
accessRandom Memory
ci
U(t)dv−1 = V (t)
i if all {Vi} are equal
U(t)dv−1 = U(t−τ(ω))
dv−1 if not
D. Declercq (ETIS - UMR8051) 49 / 56
Error-correcting Performance
(256,128) LDPC code over GF(16)
10-6
10-5
10-4
10-3
10-2
10-1
100
1 1.5 2 2.5 3 3.5 4
Fra
me E
rror
Rate
Eb/N0 (dB)
rmax = 10
rmax = 1000
SPA maxitrs=103
Stoc. maxitrs=106
Stoc. maxitrs=104
Simple decoder, but latency is catastrophic.
D. Declercq (ETIS - UMR8051) 50 / 56
Relaxed Half-Stochastic Decoding
For high dv and q, the variable node is the bottleneck in stochastic decoders
Relaxed Stochastic Decoder: replace edge memory by a q-vector message ofprobabilities µv → p estimated in a relaxed way. Then sample the Check-Node input fromµv → p .
Relaxed Half-Stochastic Decoder: replace variable node inputs by (dv − 1) q-vectormessages of probabilities
˘µip → v
¯estimated in a relaxed way. Perform BP-based
variable node update to get µv → p , then sample the Check-Node input from µv → p .
[Sarkis,2010] G. SARKIS, S. HEMATI, S. MANNOR AND W.J. GROSS, “RELAXED HALF-STOCHASTIC DECODING OF LDPC
CODES OVER GF(q)”, Proceedings of the Allerton conf., MONTICELLO, ILLINOIS, USA, SEPTEMBER 2010.
D. Declercq (ETIS - UMR8051) 51 / 56
Performance of Relaxed Half-Stochastic Decoder
10-8
10-7
10-6
10-5
10-4
10-3
10-2
10-1
100
1 1.5 2 2.5 3 3.5 4 4.5 5
Eb/N0 (dB)
GF(32) (4,28)n = 868, k = 747rmax = 10
GF(16) (2,4)n = 256, k = 128rmax = 10
GF(64) (2,4)n = 192, k = 96rmax = 1
GF(256) (2,4)n = 192, k = 96rmax = 1
SPARHS
D. Declercq (ETIS - UMR8051) 52 / 56
Average Iteration is still Too Large !!
(256,128) LDPC code over GF(16).
SNR (dB) 2.0 3.0 4.0
Stochastic 2834 475 253
RHS, β = 164 373 167 103
RHS, SNR-adapted β 373 50 17
No hardware implementation proposed yet, too soon to conclude about interest (or not) ofRHS decoder.
D. Declercq (ETIS - UMR8051) 53 / 56
Outline
1 Extended Min-Sum Decoding of NB-LDPC Codes
2 Further Refinements and ASIC Implementation
3 Analysis and Optimal Correction of the NB-LDPC decoders
4 Alternative Decoders: the Min-Max Decoder
5 Alternative Decoders: Symbol Flipping Decoder
6 Alternative Decoders: Non-Binary Stochastic Decoder
7 General Conclusion on Simplified Non-Binary Decoding
D. Declercq (ETIS - UMR8051) 54 / 56
ConclusionsPros/Cons of existing Solutions
EMS with nm sufficiently large: good performance but too complex (3 to 6 times more thanbinary),
Memory/Routing requirements are reduced ... but not greatly,
Min-Max: same class of algorithm than EMS: roughly same advantages and drawbacks.
Stochastic Decoding: Simple, but good performance achieved only at the price of a veryhigh latency,
Symbol Flipping: Very Simple, but too weak for the moment,
The most interesting issue in my opinion comes from a proper compensation of thesub-optimal decoders.How, where and when correct the messages is the key question.
D. Declercq (ETIS - UMR8051) 55 / 56
ConclusionsThe Holy-Grail of Non-Binary Decoding
Algorithms do not scale well with q for fixed complexity (even EMS),
GF(8) GF(16) GF(32) GF(64) GF(128) GF(256) GF(512)0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
2
2.2
2.4
Galois Field Order
Thre
shold
Valu
e δ
=(E
b/N
0) d
B
factor correctionoffset correction
BP
EMS(n
m,n
c)=(7,2)
EMS(n
m,n
c)=(13,3)
In principle we would like that the algorithms for GF(q) LDPC decoders have complexitygrowing in p = log2(q) and not with q.
How to achieve that with still good performance is the Holy-Grail of Non-Binary Decoding.
D. Declercq (ETIS - UMR8051) 56 / 56