Stavelet Update

10.12.2010Peter W Phillips

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Contents

1. Stavelet Numerology and Dead Chip2. Shield Configurations3. Bias Voltage4. Noise on SP+ line5. Future Programme

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The Stavelet

Hybrid 0 1 2 3 4 5 6 7

BCC 62 61 60 59 58 57 56 55

MUX 7 6 5 4 3 2 1 0

DEMUX 14/15 12/13 10/11 8/9 6/7 4/5 2/3 0/1

Coupling DC AC AC DC AC DC AC DC

Strips Stereo Straight Straight Stereo Straight Stereo Stereo Straight

Module 0 1 2 4

s/n 1 9 3 4

Silicon FZ2 FZ1 FZ2 FZ2

1. Stavelet Numerology

Dead Chip

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Dead Chip: A Victim of Violent Crime

Certainly not infant mortality!

2. Shield Optimisation: intention

For DC coupled hybrids, make the DC shield connection represented by the black line.Initially retain AC shield connections at the other side of all hybrids, then start taking them off.

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Shield Optimisation: reality

LIN

DC

AC

AC

DC

AC

DC

AC

DC

LIN

A

DC

AC

AC

DC

AC

DC

AC

DC B

DC

AC

AC

DC

AC

DC

AC

DC

LIN

C

DC

AC

AC

DC

AC

DC

AC

DC

LIN

D

DC

AC

AC

DC

AC

DC

AC

DC

LIN

E

DC

AC

AC

DC

AC

DC

AC

DC

LIN

F

Conditions for A-F:•New IF board•EoS linear 3V3•HSIO switch mode 48V PSU•XIlinx cable plugged in•ADCs not being read•Screened SP cable•TTi TSX3510 @5A CI

LIN

Note: configuration “B” was a mistake. I meant to remove the AC coupled shield link from hybrid 7, not hybrid 6…

DC PB

AC

AC

DC

AC

DC

AC

DC

LIN(PB – previous best)

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ENC for various shield configurations

00 01 10 11 20 21 30 31 40 41 50 51 60 61 70 71 Hybrid / Column

It’s obvious that removing the AC coupled shield bonds from hybrid 6 at step Bwas a bad idea. Otherwise we got better in some places, worse in others…

(PB – previous best)

ENC

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Stavelet ENC @2fC, TSX3510P@5A1330-3, 150V bias, linear EoS 3V3

DEAD CHIP

SWAP

PED

DC

AC

AC

DC

AC

DC

AC

DC

LIN

F

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Stavelet ENC @2fC, TSX3510P@5APREVIOUS BEST(1284-6) shield pads separated, EoS linear

DC PB

AC

AC

DC

AC

DC

AC

DC

LINDEAD CHIP

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3.Bias Voltage

• Using TTi Supply @5.0A• Strobe Delay set at 150V• Measure ENC for 100 to 260V in 20V steps

Conditions for HV study:•New IF board•EoS linear 3V3•HSIO switch mode 48V PSU•XIlinx cable plugged in•ADCs not being read•UNSCREENED SP cable•TTi TSX3510 @5A CI

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0 2 4 6 8 10 12 14 16580

600

620

640

660

680

700

720

740

760

100V120V140V160V180V200V220V240V260VL'POOL

ENC as f(Vdet)

Column

ENC

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ENC as f(Vdet)

100 120 140 160 180 200 220 240 260 280 300600

620

640

660

680

700

720

740

760

0 Stereo DC1 Stereo DC2 Straight AC3 Straight AC

100 120 140 160 180 200 220 240 260 280600

620

640

660

680

700

720

740

760

4 Straight AC5 Straight AC6 Stereo DC7 Stereo DC

100 120 140 160 180 200 220 240 260 280560

580

600

620

640

660

680

700

720

740

760

8 Straight AC9 Straight AC10 Stereo DC11 Stereo DC

100 120 140 160 180 200 220 240 260 280550

600

650

700

750

12 Stereo AC13 Stereo AC14 Straight DC15 Straight DC

ENC

V

ENC

VENC

V

ENC

V

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Stavelet ENC @2fC, Tti @ 5A1341-6, 150V bias, linear EoS 3V3, one choke on SP- only

DEAD CHIP

SWAP

PED

DC

AC

AC

DC

AC

DC

AC

DC

LIN

F150V

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Stavelet ENC @2fC, Tti @ 5A1341-3, 200V bias, linear EoS 3V3, one choke on SP- only

DEAD CHIP

SWAP

PED

DC

AC

AC

DC

AC

DC

AC

DC

LIN

F200V

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• At upgrade week I reported ~1.5V spikes (left)– Correlated with ADC readout

activity. These are I2C devices (single ended) so not such a big surprise.

– Matt changed the firmware to read ADCs on demand

– I changed the software to remove said demand.

– Sadly this did not reduce the stavelet noise

• Now look to see what’s left…

4. Noise on power lines

Single Ended Probe on SP+

1.81V Pk-Pk!!!Correlated with EoS ADC (I2C) traffic

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Noise on SP+

TTi TSX 3510 at 5.0A CI, one choke Jan Stastny CS at 5A, one choke

With TTi unit, trace is similar at all times.

With repaired JS current source, there is more voltage noise during readout (above). Between bursts, the noise band is ~1/3 of that shown.

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• Addition of a second CM choke (with 2 turns) gives a considerable reduction in both the baseline noise and spike amplitude.

• Noise levels during and between bursts is now similar.

• ENC plot overleaf

Noise on SP+

Jan Stastny CS at 5A, two chokes

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Stavelet ENC @2fC, repaired CS@5A1333-27, 200V bias, linear EoS 3V3, two chokes

DEAD CHIP

SWAP

PED

DC

AC

AC

DC

AC

DC

AC

DC

LIN

F200V

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Noise on SP+

Jan Stastny CS at 5A + SCTLV filter

Adding a more complex filter (PP3 prototype) introduces a phase lag to the current measurements, which disturbs the control loop. Oscillation is the result .

IN OUT

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5. Future Programme• Further shield configurations

– Replace fused bias bonds– Float LVDS screen– Revert to previous best or common shield and try higher Vdet

• Extra noise at“GND” end of stavelet (H0)– Add C between SP+ and SP1 at EoS– Longer cables and/or chokes CM between IF and EoS– Split ground planes at EoS (again)

• Current Source– Try screened SP cable with JS unit– Try remote sensing– Revised unit due soon

• Updated HSIO firmware & software (presently being debugged)– Fibre optic ethernet– Ability to pulse noise injection lines– Double trigger noise tests

• SP Plugin boards