submicron inp bipolar transistors: scaling laws, technology roadmaps, advanced fabrication processes...
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Submicron InP Bipolar Transistors:Scaling Laws, Technology Roadmaps, Advanced Fabrication Processes
Mark Rodwell
University of California, Santa Barbara
[email protected] 805-893-3244, 805-893-3262 fax
2002 SSDM Conference, September, Nagoya
Applications of InP HBTs
Optical Fiber Transceivers
40 Gb:InP and SiGe HBT both feasible ICs now available; market has vanished
80 & 160 Gb may come in timewithin feasibility for scaled InP HBTworld may not need capacity for some timeWDM might be better use of fiber bandwidth
mmWave Transmission
60-80 GHz, 120-160 GHz, 220-300 GHzLow atmospheric attenuation (weather permitting).High antenna gains (short wavelengths).10 Gb/s transmission over 500 meters with 20 cm antennas needs 4 mW transmitter power
Mixed-Signal ICs for Military Radar/Comms
direct digital frequency synthesis, ADCs, DACshigh resolution at very high bandwidths sought
How Do We Improve the Bandwidth of Bipolar Transistors ?
collex
Ebc
Ejecollectorbase RR
qI
kTC
qI
kTC
f
2
1
Thinner base, thinner collector higher f , but higher RbbCcb , RexCcb …
what parameters are really important in HBTs ?how do we improve HBT performance ?
How do we improve gate delay ?
clock clock clock clock
inin
out
out
cexLOGIC
LOGIC
Ccb
becb
becbC
LOGIC
IRq
kTV
V
IR
CCR
CCI
V
6
leastat bemust swing logic The
resistance base the through
charge stored
collector base Supplying
resistance base the through
charging ecapacitancDepletion
swing logic the through
charging ecapacitancDepletion
:by DeterminedDelay Gate
bb
depletion,bb
depletion,
max
logic
emitter
collector
min,
depl,
& not speed,clock for design toneed
:SiGen faster thabarely logic InP
high at lowfor low very bemust
22
objective.design HBTkey a is /High
total.of 80%-60% is
. with correlated not wellDelay
ff
JVR
v
T
A
A
V
V
I
VC
CI
CCIV
f
eex
effective
C
CE
LOGIC
C
LOGICcb
cbC
becbCLOGIC
Scaling Laws for fast HBTs
22 as scale alsomust )cm-( y resistivitcontact base the
HBTs, mesa-undercutor substrate-ferrednot transbut HBTs, mesaFor v
circuitarbitrary an in bandwidth in increase 1: a
obtain order toin parameters HBTin change alproportion Required
Challenges with Scaling:
Collector-base scaling Mesa HBT: collector under base Ohmics. Base Ohmics must be one transfer length → sets minimum size for collector Solution: reduce base contact resistivity → narrower base contacts allowedSolution: decouple base & collector dimensions
transferred-substrate, undercut-mesa, or buried SiO2 in junction (SiGe)
Emitter Ohmic Resistivity: must improve in proportion to square of speed improvements
Current Density: self-heating, current-induced dopant migration, dark-line defect formation
Loss of breakdownavalanche Vbr never less than collector bandgap (1.12 V for Si, 1.4 V for InP) ….sufficient for logic, insufficient for power
Yield !submicron HBT processes have progressively decreasing yield
Technology Roadmaps for 40 / 80 / 160 Gb/s
Low Ccb InP HBT structures
emitterbase contact
collectorcontact
SI substrate
InGaAs subcollector
InP collector
InGaAscollector
InP subcollector
InGaAs base
undercutcollector junction
undercut-collector
transferred-substrate Allows deep submicron collector scaling
Problems with heating at high J
Low yield at deep submicron scaling
Popular approach
Uncertain yield at submicron geometries
Conservative approach
Still not viable for > 3000 transistors per IC
Need improved device structures for high yield at 0.1 m scaling
Narrow-mesa with ~1E20 carbon-doped base
0
10
20
30
40
10 100 1000
Tra
nsi
sto
r G
ain
s, d
B
Frequency, GHz
U
U
MSG/MAG
H21
unbounded U
Ic = 5 mA, Vce = 1.1 V
Unbounded Power Gain in Submicron InAlAs/InGaAs HBTs
Unbounded 45-170 GHz Unilateral power gain
Power gain is high, but fmax can’t be determined
Miguel Urteaga
Int. Symp. Compound Semiconductors, Tokyo, Oct. 2001 Int. Journal High Speed Electronics and Systems, to be published
0.3 x 18 m2
Emitter
0.7 x 18.6 m2
Collector
-1 10-3
0 100
1 10-3
2 10-3
3 10-3
4 10-3
5 10-3
0 50 100 150 200
Ic = 1 mAIc = 2 mAIc = 3 mAIc = 4 mAIc = 5 mA
Gc
(S)
Frequency (GHz)
Vce
=1.2 V
60 S=1/17k negative conductance at 110 GHz
termsG negative 2212 bbcbiRCG
reduced
0 100
2 10-15
4 10-15
6 10-15
8 10-15
1 10-14
0 50 100 150 200
Ic = 1 mAIc = 2 mAIc = 3 mAIc = 4 mAIc = 5 mA
Cc
(Fa
rads
)
Frequency (GHz)
Vce
=1.1 V
termsoncancellati /12 cbCB
Capacitance modulation & negative resistance observed: Gunn-like or IMPATT effects ?
E
B C
R ex
R bb
C cbx
C cb i
C be,depl
re=1/gm
Y cb
gm
b
Collector velocity modulation: Ccb cancellation and negative resistance
c
cjx
ceI )sin(xI
ps 5.0)cm/s 1032/(μm 3.02/ 5 electroncollc vT
c
cjDCC
cbcb
ceIdV
dY
)sin(
,
Miguel Urteaga
-3 10-3
-2 10-3
-1 10-3
0 100
1 10-3
2 10-3
3 10-3
0 100 200 300 400 500 600 700
Real Part: Collector-Base Conductance
colle
cto
r-b
ase
co
nd
uct
an
ce,
Sie
me
ns
-Ic
*d(t
au_
c)/d
Vcb
= -
Ccb
,ca
nce
llatio
n=
-1 f
F
Frequency, GHz
negative Ycb: 0-700 GHz(340 S=1/3000 at 120 GHz) -1 10-15
-5 10-16
0
5 10-16
1 10-15
0 100 200 300 400 500 600 700
Equivalent Negative Capacitance, Bcb
/
eq
uiv
ale
nt
cap
aci
tan
ce,
Bcb
/ o
meg
a,
Fa
rad
s
-Ic
*d(t
au_
c)/d
Vcb
= -
Ccb
,ca
nce
llatio
n=-1
fF
Frequency, GHz
equivalent negative Ccb: starts decreasing at ~150 GHzreaches zero at 370 GHz
c
c
ccb
cDCCeq d
d
dV
dIC
)(sin1 2
,
c
cc
ccb
cDCCcb d
d
dV
dIG
)sin()cos(
,
If Ccb cancellation is observed, there must also be an associated negative resistance
2nd Hypothesis: weak IMPATT effects in the collector
H
Hj
c
cjx
Hc MeeI
)sin(
1)sin(
xI
H
Hj
cbDCCcb
hedV
dMIY
)sin(
,
ps 3)cm/s 1052/(μm 3.02/ 4 holecollH vT
Miguel Urteaga
E
B C
R ex
R bb
C cbx
C cb i
C be,depl
re=1/gm
Y cb
gm
b
-1 10-4
0 100
1 10-4
2 10-4
3 10-4
4 10-4
0 50 100 150 200 250
Real Part: Collector-Base Conductance
IMP
AT
T
con
duc
tan
ce,
Sie
me
ns
-Ic*
d(t
au
_c)
/dV
cb=
-C
cb,c
an
cella
tion
=-1
fF
Frequency, GHz
negative conductance: 83-166 GHz(70 S=1/14,000 at 120 GHz)
-1 10-15
-8 10-16
-6 10-16
-4 10-16
-2 10-16
0
2 10-16
4 10-16
0 50 100 150 200 250
Equivalent Negative Capacitance, B12
/
MP
AT
T c
ap
aci
tanc
e,
Bcb
/ o
meg
a,
Fa
rad
s
-Ic*
d(t
au
_c)
/dV
cb=
-C
cb,c
an
cella
tion
=-1
fF
Frequency, GHz
equivalent negative Ccb: starts decreasing at ~50 GHzreaches zero at 166 GHz
IMPATT effect also produces both capacitance cancellation and negative resistance
sfrequencie lowat :Again cbtotalcccb VITAC
Deep Submicron Bipolar Transistors for 140-220 GHz Amplification Miguel Urteaga
0
10
20
30
40
10 100 1000
Tra
nsi
sto
r G
ain
s, d
B
Frequency, GHz
U
U
MSG/MAG
H21
unbounded U
-4
-2
0
2
4
6
8
140 150 160 170 180 190 200 210 220
S2
1,
dB
Frequency, GHz
1-transistor amplifier: 6.3dB @ 175 GHz
-30
-20
-10
0
10
140 150 160 170 180 190 200 210 220
gain
, dB
Frequency (GHz)
3-transistor amplifier: 8 dB @ 195 GHz
raw 0.3 m transistor: 6-11 dB power gain @ 200 GHz
UCSB
Wideband Mesa InP/InGaAs/InP DHBTs
Mattias Dahlstrom (UCSB) Amy Liu (IQE)
2000 Å InP collector300 Å InGaAs base8E19 to 5E19 graded C base dopingInAlAs/InGaAs base-collector grade.
500 Ohm/square base sheet resistancePd/Ti/Pd/Au base Ohmic contacts< 10-7 Ohm-cm2 base contact resistance
7.5 V Breakdown282 GHz f, > 450 GHz fmax , operation to 500 kA/cm2 at 1.7 voltsRbb is low, Ccb needs further reduction
0
5
10
15
20
25
30
1010 1011 1012
Ga
in (
dB
) H
21,
U
Frequency (Hz)
UCSB / IQE
1 m base contacts, 0.5 m emitter junction 0.7 m emitter contact
Vce=1.7 V J=3.7E5 A/cm2
282 GHz f>450 GHz fmax,
480 GHz
87 GHz HBT master-slave latch
InAlAs /InGaAs/InP MESA DHBT
400 Å base, 2000 Å collector,
9 V BVCEO
200 GHz ft, 180 GHz fmax
2.5 x 105 A/cm2 operation
PK Sundararajan, Zach Griffith
-0.2
-0.18
-0.16
-0.14
-0.12
-0.1
-0.08
-0.06
22 22.02 22.04 22.06 22.08 22.1 22.12 22.14
87 GHz input, 43.5 GHz output
Vo
ut (
Vol
ts)
time (nsec)
UCSB
8 GHz ADCTechnology0.7 um InP MESA DHBT 400 Å base, 2000 Å collector, 9 V BVCEO, 200 GHz ft, 180 GHz fmax2.5 x 105 A/cm2 operation
PK Sundararajan
975 kHz FFT bin size8 GHz clock rate65.5 MHz signal64:1 oversampling ratio
Designsimple 2nd-order gm-C topologycomparator is 87 GHz MSS latchintegration by capacitive loads 3-stage comparator, RTZ gated DAC
Results133 dB (1 Hz) SNR at 74 MHzequivalent to ~8.8 bits at 200 MS/s
High current density 10 mA/m2
T-shaped polysilicon emitter 0.25 m junction wide contact low resistance, high yield
Thin intrinsic base: low b
Thick extrinsic base: low Rbb
Low Ccb collector junction collector pedestal CVD/CMP SiO2 planarization regrown poly extrinsic base
High-yield, planar processing high levels of integration LSI and VLSI capabilities
SiGe clock rates up to 65 GHzMuch more complex ICs than feasible in InP HBTInP HBT must reach higher integration scales or will cease to compete
Very strong features of SiGe-bipolar transistors
InP vs Si/SiGe HBTs: materials vs scaling advantages
Advantages of InP~20:1 lower base sheet resistance, ~5:1 higher base electron diffusivity~3:1 higher collector electron velocity, ~4:1 higher breakdown-at same f.
Disadvantage of InP: archaic mesa fabrication processPresently only scaled to ~ 1 um (production)large emitters, poor emitter contact:low current density: 2 mA/um2
high collector capacitance nonplanar device - low yieldlow integration scales
InP HBT limits to yield: non-planar processEmitter contact
Etch to base
Liftoff base metal
Failure modes
Yield degrades as emitters arescaled to submicron dimensions
base contact
emittercontact
base contact
S.I. substrate
base
sub collector
S.I. substrate
base
sub collector
S.I. substrate
base
sub collector
emitter
S.I. substrate
base
sub collector
Emitter planarization, interconnects
base contact
liftoff failure:emitter-baseshort-circuit
S.I. substrate
base
sub collector
base contact
excessiveemitter undercut
S.I. substrate
base
sub collector
S.I. substrate
base
sub collector
planarization failure: interconnect breaks
MBE growth of Polycrystalline n+ InAs
Polycrystalline InAs grown on SiN:
• Doping = 1.3 1019 cm-3, Mobility = 620 cm2/V•s
• doping-mobility product 81021 (V •s •cm)-1
InGaAs lattice matched to InP:
• Doping = 1.0 1019 cm-3, Mobility = 2200 cm2/V•s
• doping-mobility product 221021 (V •s •cm)-1
Polycrystalline InAs has potential as an extrinsic emitter contact
Dennis Scott
6 1018
8 1018
1 1019
1.2 1019
1.4 1019
1.6 1019
1.8 1019
2 1019
2.2 1019
945 950 955 960 965 970 975 980 985
Poly InAs:Si Doping vs. Temp
Dop
ing
Temp
SiGe HBT process: extensive use of non-selective-area poly-Si regrowth
Can a similar technology be developed for InP ?
Process Flow:Single-poly-regrowthInP HBT
collectorcontact
top view
subcollectorisolationimplantmask
emitterjunction
extrinsicemitterandcontact
basecontact
N- collector
N+ subcollector
S.I. substrate
1) Epitaxial Growth,Fe implant isolation
2) Deposit Pd/W base Ohmics.Encapsulate with Si3N4Etch base-collector junction
base
N- collector
N+ subcollector
S.I. substrate
base
basecontactSi
3N
4
3) Passivate with Si3N4Etch emitter window through baseForm emitter SiN sidewalls
N- collector
N+ subcollector
S.I. substrate
basecontact
Si3
N4
4) Regrow polycrystalline emitter.Deposit emitter metal.Etch through emitter
N- collector
N+ subcollector
S.I. substrate
base contact
Si3
N4
regrownInAlAs/InAsemitter*
*monocrystalline wheregrown on semiconductor,polycrystalline wheregrown on silicon nitride
emitter contact
5) Recess etch and depositcollector contacts
N- collector
N+ subcollector
S.I. substrate
base contact
Si3N
4
regrownInAlAs/InAs emitter*
emitter contact
collector contact
Dennis Scott
Regrown-Poly-InAs-Emitter HBT
0.0 100
2.0 100
4.0 100
6.0 100
8.0 100
1.0 101
0 1 2 3 4
AE = 0.8 x 15 um 2 I
b = 100uA/step
I c (m
A)
Vce
(V)
Dennis Scott
Emitter Regrowth with Buried Base Contact MetalDennis Scott
Buried W/Au base metal under emitter→ further reduced Rbb
Similar to buried WSi base contact process (SiGe, Washio)
Submicron Scaling of InP HBTs
InP HBTs are a mixed-signal, not a MIMIC technology for MIMICs, sub-0.1-m InP HEMTs are hard to beat mixed-signal is fiber ICs, ADCs, DACs, digital frequency synthesis these are 1000 -- 40,000 transistor ICs
InP HBTs are struggling to compete with SiGe HBT application demands transistor counts near/beyond yield limits large emitter junctions→ high current → power near acceptable limits no decisive speed advantage in relevant circuits: digital logic materials advantages being squandered by inadequate scaling
Critically needed for InP HBTs highly scaled process: 0.2 m emitters, 0.4 m collectors highly planar and high-yield fabrication processes small emitter junctions (0.2 m x 0.5 m) for acceptable power