Supporting Information for

Negative transconductance and negative differential resistance in

asymmetric narrow bandgap 2D-3D heterostructure

Tiaoyang Li, Xuefei Li, Mengchuan Tian, Qianlan Hu, Xin Wang, Sichao Li and Yanqing

Wu*

Wuhan National High Magnetic Field Center and School of Optical and Electronic

Information, Huazhong University of Science and Technology, Wuhan 430074, China

E-mail: yqwu@mail.hust.edu.cn

Electronic Supplementary Material (ESI) for Nanoscale.This journal is © The Royal Society of Chemistry 2019

mailto:yqwu@mail.hust.edu.cn

Supplementary section 1:

Figure S1 | Fabrication process of BP/InAs device. For fabricating the BP/InAs

heterostructure, we start with InAs wafer and deposit 20 nm Ti/60 nm Au as the Ohmic

contact to InAs. Then, 20 nm insulating dielectric HfO2 was deposited at 250 °C by

atomic layer deposition (ALD), followed by rapid thermal annealing (RTA) at 500 °C

for 30 s in a nitrogen ambient to improve the dielectric film quality. Next, the HfO2/InAs

wafer was patterned using photolithography and the dielectric HfO2 was selectively

etched using inductively coupled plasma (ICP). (a) The engineered substrate comprises

the InAs contacts and the insulating region. Scale bar, 200 m. (b) The BP flake was

exfoliated and transferred onto the substrate, part of the BP flake overlaps with the InAs

while the other part stacks on the HfO2. Scale bar, 20 m. (c) A stack of 20 nm Ni/60

nm Au was deposited as BP contact. Scale bar, 20 m. (d) The gate dielectric stack

contains 5 nm Al2O3 by natural oxidation of Al and 10 nm HfO2 by ALD. Scale bar, 20

m. (e) A stack of 20 nm Ni/60 nm Au gate electrode was deposited to complete the

device. Scale bar, 20 m. There is no overlapping region between the BP contact and

the gate electrode. (f) The two terminal IV characteristics of the InAs devices at 300

K with various channel length, showing an excellent Ohmic contact.

InAs

contact

BP Flake

HfO2

Gate

HfO2

InAs

BP Contact

Al2O3+HfO2

-0.2 0.0 0.2-100

0

100

I d (

mA

)

Vd (V)

4 m

8m

16m

32 m

64 m

100 m

a b c

d e f

Supplementary section 2:

Figure S2 Raman spectra measured with a 532 nm excitation laser on different BP/InAs

heterostructures on the same wafer.

InAs

BP/InAs_4

BP/InAs_3

BP/InAs_2

A1

g

Inte

ns

ity

(a.u

.)A

2

gB

2gLO

BP/InAs_1

200 250 350 400 450 500

Raman shift (cm-1)

a

Supplementary section 3:

Figure S3 | Simulation details. To determine the band alignment at the BP/InAs

heterointerface, we calculate the 2D band diagram in the parallel and vertical directions

of the BP/InAs heterostructure using nextnano software. These simulations do not

consider BTBT or other transport mechanisms, and also do not consider the interaction

between electronic orbital positions of the different layers but the carrier density,

bandgaps, and band alignment. (a) Energy-band diagrams for isolated BP and InAs with

different bandgap and electron affinity. The energy band alignment is type-III broken-

gap, which meets the band alignment requirement for interband tunneling. (b)

Schematic view of the BP/InAs heterostructure that is used for simulation of the band

diagrams. The thickness of BP flake and InAs are 10 nm and 100 nm, respectively. The

length of the access region and BP/InAs overlapping region all are 100 nm. (c) The

band alignment of the heterostructure along the blue dashed line in Figure S3b. A

horizontal hole potential barrier is naturally formed at the boundary due to the

InAs

BP

z (nm)

x (nm)

0 100 200-100

10

100

a b

0.3 eV

BP InAs

4.4 eV

4.9 eV

0.35 eV

c dMaterial BP InAs

Thickness (nm) 10 100

Bandgap (eV) 0.3 0.35

mn*/m0 (x, y, z)=(0.2, 0.7, 0.2) 0.024

mh*/m0 (x, y, z)=(0.2, 1, 0.4) 0.41

Electron affinity

(eV)4.4 4.9

Carrier density

(/cm3)110

17 31016-100 0

-0.6

-0.3

0.0

0.3

0.6

electron barrier

EV

InAs

E (

eV

)

x (nm)

EF

BP

EC

EC

EV

hole barrier

0 10 20

z (nm)100 200

x (nm)

inhomogeneous carrier distribution in the access BP region and the BP/InAs

overlapping region. The barrier at the InAs side is very small and can be ignored. (d)

The detailed materials parameters used in the simulations for BP/InAs heterostructures.

Supplementary section 4:

Figure S4 (a) The double-sweep output characteristics of the BP/InAs device, showing

an NDR behavior for both forward and reverse sweeps. And the gate leakage current is

small enough compared with drain current.

-0.4 -0.2 0.0 0.2 0.410

-12

10-11

10-10

10-9

10-8

10-7

I ds (

A)

Vds

(V)

Forward

Reverse

Igs

a

Supplementary section 5:

Figure S5 (a) The IdsVds curves of the BP FET at 4.3 K, with Vgs changing from 1.8 V

to 3 V with a step of 0.4 V. (b) The two terminal IV characteristics of the InAs

devices at 4.3 K with various channel length. The metal contacts on BP and InAs show

a good ohmic at 4.3 K.

-1.0 -0.5 0.0 0.5 1.0-40

-20

0

20

40

Vgs

= 1.8 to 3 V

step= 0.4 V

BP FET_4.3 K

I ds (

A)

Vds

(V)-0.2 -0.1 0.0 0.1 0.2

-100

-50

0

50

100

I d (

mA

)

Vd (V)

InAs_4.3 K

4 m

8 m

16 m

32 m

64 m

100 m

a b