synthesis of a traffic light sequence circuit

7/26/2019 Synthesis of a Traffic Light Sequence Circuit

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Abstract - In order to fully understand the topics covered in the

course logcist, a project showing the application of said topics

was necessary to make. In creating a traffic light sequence in an

intersection using integrated circuit chips, 7 segment LED

display and other passive elements in the circuit, truth tales,state tales, state diagrams and !arnaugh maps "topics that were

covered during the term# were then used to analy$e the results.

Index Terms%cominational circuits& digital circuits& flip'

flops& logic circuits& logic gates& sequential circuits

I. INTRODUCTION

The first few chapters of the paper discusses the theorybehind logic circuits including the functions of commerciallyavailable integrated circuits used for logic circuits. It isfollowed by the discussion of the synthesis of a traffic lightseuential circuit by means of all the tools of !oolean algebraand by analysis of state transition tables and diagrams. Thecircuits obtained then are put into test by means of asimulation software using "ultisim. #inally$ the simulationresults obtained are to be discussed for analysis.

II. T%&OR&TIC'(#R'"&)OR*

A. Boolean algebra

!oolean algebra is mathematics specifically used tomanipulate logic e+pressions in a more concise form. (ogice+pressions can be manipulated with the use of theorems thatcreate or comprehend optimi,ed switching$ digital andcomputer circuits.

Figure 2 - 1Examples of Boolean algebra Theorems

There are many established methods in order to simplify!oolean e+pressions such as *-mapping$ maing use of atruth table which are used to minimi,e the cost in creatinglogic circuits.

B. 555 IC timerThe N&/// timer IC is an eight pin dip pacage IC which

performs varying tass that involves timing in electroniccircuits. The /// timer has three operating modes0"onostable$ 'stable$ and !istable.

Figure 2 - 2 The 555 timer and its pin assignments

)hen operating in monostable the /// timer acts as a one-shotmonostable multivibrator used as a pulse generator circuit.The multivibrator circuit has only one stable state and

produces a single output pulse when triggered e+ternally.During !istable mode$ the /// operates as a flip-flop when its

DI1 pin is not connected and no capacitor is used. (astly'stable mode$ which was used in this pro2ect where the ///timer operates as an oscillator. The output from the /// timeris a continuous pulse waveform of a freuency that isdependent on the values of two resistors and capacitors used inits circuit.

Figure 2 - The 555 timer !ir!uit in Astable mode

During astable mode the /// timer generates pulsewaveforms$ the freuency of the pulse depends on the valuesof R3$ R4 and C. given by the euation0

f= 1

ln (2) C (R1+2R2)

C. "ultiplexer #$%&15

' multiple+er is a device that selects one of several analoginputs and outputs the input into a single line. %aving an inputof 4n and having select lines n. ' multiple+er IC 56(13/7 wasused in this pro2ect.

1ynthesis of a Traffic (ight 1euence Circuit'drian !. 'biera$ Dino #. (igutan$ Carl !. "atulac$ Daniel 8. Navarrete$ and "arc C. 1er,o


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Figure 2 - $ a #$%&15 "'( IC !onne!tion diagram

This IC 9ermits multiple+ing from N lines to 3 line$ performsat parallel-to-serial conversion$ %igh fan-out$ low impedance$totem pole outputs. It averages a propagation delay of 36nanoseconds from data$ 3: nanoseconds from strobe and 44nanoseconds from select.

). )e!oder' 3-of-n binary decoder has n output bits$ and the integerinputs bits serve as the ;address; or bit number of the output

bit that is to be activated. )hen a binary decoderreceives n inputs it activates one and only one of its 4noutputs

based on that input with all other outputs deactivated. ' 4-to-6 binary decoders were used in this pro2ect.

Figure 2 - 5 a blo!* diagram of a 2-to-$ )e!oder

This pro2ect made use of a Decoder IC %C#6//


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F. $-bit binar !ounter #$%&3

Figure 2 - 3 #$%&3 IC binar Counter

Figure 2 - 14 #$%&32 IC ex!itation table

. BC) up-do6n de!ade !ounter #$%&132

Figure 2 - BC) up7do6n !ounter pin !onfig. 0 %ogi! smbol0 and

IEC logi! smbol

Figure 2-12 BC) up7do6n !ounter internal !ir!uit

Figure 2-1 BC) up7do6n !ounter Fun!tion table


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,. #-segment %E) de!oder7dri8er #$%&$#

Figure 2 9 1 #$%&$# !ir!uit diagram

Figure 2 9 1 #$%&$# Transition table

III. 1&AU&NTI'(CIRCUIT1NT%&1I1

The design begins by considering the structure of the trafficlight seuence and the duration >in seconds? of each trafficlight state. The structure of the seuence is as follows0 in afour-way road intersection$ the straight traffic flow of a pair ofopposite roads is considered first$ followed by the leftwardtraffic flow for the same pair. The straight flow must bestopped before the leftward flow commences. 'fter theleftward traffic flow of the first pair of opposite roads$ thestraight traffic flow of another pair of opposite roads follows$then also followed by the leftward traffic flow for the same

pair. 'fter the leftward traffic flow for second pair of oppositeroads$ the straight traffic flow follows for the first pair ofopposite roads and the seuence repeats.

#irst flow 1econd flow

Third flow #ourth flow#ig. 7-3. The order of traffic flow seuence. 'fter the fourth flow$ the firstflow follows and the seuence repeats.

#or each flow$ there are three traffic light states0 green$yellow and red states. #or convenience$ the duration of theyellow state is considered as the unit length of time in thedesign of traffic light seuential circuit since it has the shortestduration. The duration of green state was decided to be thricethe duration of yellow state for convenience in circuit design.The duration of red state follows from the duration of yellowand green states and will be determined later on. #urthermore$it was decided that the duration of the yellow state shall be 6seconds from which follows that the duration of the greenstate be 34 seconds E again$ these values were chosen forsimplicity of circuit design. ' pair of 5-segment display forcountdown for each traffic light panel will indicate the numberof seconds left for the current state before the transition to thene+t state will occur. It too has its own seuential circuit toconsider that must be synchroni,ed with the seuential circuitof the traffic light. To mae things clear$ we will divide thediscussion of synthesis of seuential circuits into two0 one forthe traffic light seuence and the other for the 5-segmentdisplay countdown timer. These circuits will be combined lateron.

A. Traffi! %ight &euential Cir!uit

#or each flow$ there are three traffic light states0 green$yellow and red states. The seuence goes as follows0 greenstate$ followed by yellow state then by the red state. The redstate is followed by the green state and the seuence repeats.%owever$ since the traffic flow seuence also repeats$ we mustconsider the seuences of all traffic light panels for all roadsso that we can determine which panels are in green$ yellow orred state at a given moment. (et us first denote the two pairsof opposite roads as 3 and 4$ the straight and leftward flow by1 and ( and the green$ yellow and red states as 8$ and Rrespectively. ' seuence of symbols such as 813 refers to thegreen state for straight flow for the first pair of opposite roads.

1imilarly$ (4 refers to the yellow state for leftward flow forthe second pair of opposite roads. Now with the notation setand following the discussion earlier in this chapter$ thesuccession of traffic light states goes as follows0


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#ig. 7-4. The state diagram for the seuence of traffic light states for allpanels.

Note that the red state was not included in #ig.7-4. )hat weare showing in the state diagram is the succession of states bylooing at all panels. If one will loo at a panel$ the statediagram goes as follows0

#ig. 7-7. The state diagram for the seuence of traffic light states for onepanel.

The red state for each panel occurs after the yellow state ofthat panel until it goes into green state again. Obviously$ thered state has the longest duration of all the states in a panel.

Now$ if we denote 813 as 1B$ 13 as 13 and so on$ we willcome up with a state table lie so0

T'!(& 7-3

1T'T&T'!(OR&'C%9'N&(1tat

e1B 13 14 17 16 1/ 1< 15

813 3 B B B B B B B13 B 3 B B B B B BR13 B B 3 3 3 3 3 38(3 B B 3 B B B B B(3 B B B 3 B B B BR(3 3 3 B B 3 3 3 3814 B B B B 3 B B B14 B B B B B 3 B BR14 3 3 3 3 B B 3 38(4 B B B B B B 3 B(4 B B B B B B B 3R(4 3 3 3 3 3 3 B B

%ere$ the rows in the first column indicate the state for eachpanel. The F3G indicates that the row is the active state for agiven column state and a FBG indicates that the row is not theactive state for a given column state for a panel.

%owever$ employing the state diagram in #ig. 7-4 entailsthat the duration of the green state is the same as yellow state.In order to mae the green state longer$ there are two options0>3? design the circuit such that the different states have

different duration$ depending on the current state and >4?maintain eual duration of each state but add same statescorresponding to green state. 'dding same states will maethe duration of those state longer$ since they are oneH onlycombinational circuits will ensure that they are for the greenstate. Despite the redundancy of states$ the synthesis will befar simpler than the first option.

In this regard$ we shall add two more states for all the green

states in #ig. 7-4. This implies that the duration of the greenstate would be thrice as long as the duration of the yellow state

E this is one of the reasons why it was decided that the lengthof green state be as thrice as long as the yellow state. 'notherreason is that the addition of these states will mae 3< states intotal E a power of 4 where 6 flip-flops would suit best thedesign. #ig. 7-6 shows the modified state diagram.

Now$ the new states will be designated by symbols 1Bthrough 13/ with 1B being the first 813 state. )e will employthe T flip-flop for the design. To begin with$ the states are to

be converted to binary designation for us to be able to create astate transition table shown in Table 7-4. The flip-flops aredesignated by '$ !$ C and D with ' being the most significant

bit. The flip-flop inputs are obtained from the present state$ thene+t state and the T flip-flop e+citation table. !ased from theflip-flop inputs columns$ we will determine the combinationalcircuit necessary for each inputs by using *arnaugh map.

!ased from #ig. 7-/$ the input euation for flip-flop D isTD=1 H for flip-flop C is TC=D H for flip-flop ! isTB=CD H and for flip-flop ' is TA=BCD . The

synthesi,ed circuit based from these euations is shown on#ig. 7-


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1B B B B B B B B 3 B B B 313 B B B 3 B B 3 B B B 3 314 B B 3 B B B 3 3 B B B 317 B B 3 3 B 3 B B B 3 3 316 B 3 B B B 3 B 3 B B B 31/ B 3 B 3 B 3 3 B B B 3 31< B 3 3 B B 3 3 3 B B B 315 B 3 3 3 3 B B B 3 3 3 3

1 3 B B B 3 B B 3 B B B 31: 3 B B 3 3 B 3 B B B 3 313B 3 B 3 B 3 B 3 3 B B B 3133 3 B 3 3 3 3 B B B 3 3 3134 3 3 B B 3 3 B 3 B B B 3137 3 3 B 3 3 3 3 B B B 3 3136 3 3 3 B 3 3 3 3 B B B 313/ 3 3 3 3 B B B B 3 3 3 3

TD BB B3 33 3B TC BB B3 33 3BBB 3 3 3 3 BB B 3 3 BB3 3 3 3 3 B3 B 3 3 B33 3 3 3 3 33 B 3 3 B3B 3 3 3 3 3B B 3 3 B

T! BB B3 33 3B T' BB B3 33 3BBB B B 3 B BB B B B BB3 B B 3 B B3 B B 3 B33 B B 3 B 33 B B 3 B3B B B 3 B 3B B B B B#ig. 7-/. *arnaugh maps for T flip-flop inputs.

#ig. 7-


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T'!(& 7-6TRUT%T'!(ORTR'##IC(I8%T1T'TORO99O1IT&RO'D14

1tate

No.

9resent 1tate 14 (4

' ! C D 8 R 8 R

1B B B B B B B 3 B B 313 B B B 3 B B 3 B B 314 B B 3 B B B 3 B B 317 B B 3 3 B B 3 B B 3

16 B 3 B B B B 3 B B 31/ B 3 B 3 B B 3 B B 31< B 3 3 B B B 3 B B 315 B 3 3 3 B B 3 B B 31 3 B B B 3 B B B B 31: 3 B B 3 3 B B B B 313B 3 B 3 B 3 B B B B 3133 3 B 3 3 B 3 B B B 3134 3 3 B B B B 3 3 B B137 3 3 B 3 B B 3 3 B B136 3 3 3 B B B 3 3 B B13/ 3 3 3 3 B B 3 B 3 B

' loo at the *-map for 814 from #ig. 7- reveals that itseuation is given by GS2=A B 'C'+AB' D ' .1imilarly$ YS2=AB' CD and RS2=A '+B . #or

the leftward flow0 GL2=ABC'+ABD ' $YL2=ABCD $ and RL2=A '+B ' .Now that we have completed the set of traffic light state

euations$ one may go ahead and implement them directly.%owever$ these euations can be simplified further byobserving several patterns$ thus maing the implementationeven simpler.

To begin with$ let us factor out the common terms in 813$

giving us GS1=A

'

B

'

(C '+D ') . 1imilarly$

GL1=A'B (C'+D') . Continuing in the same fashionfor the rest of the green814 BB B3 33 3B 14 BB B3 33 3BBB B B B B BB B B B BB3 B B B B B3 B B B B33 B B B B 33 B B B B3B 3 3 B 3 3B B B 3 B

R14 BB B3 33 3B8(4

BB B3 33 3B

BB 3 3 3 3 BB B B B BB3 3 3 3 3 B3 B B B B33 3 3 3 3 33 3 3 B 33B B B B B 3B B B B B

(4

BB B3 33 3B R(4 BB B3 33 3B

BB B B B B BB 3 3 3 3B3 B B B B B3 3 3 3 333 B B 3 B 33 B B B B3B B B B B 3B 3 3 3 3

#ig. 7-. *arnaugh maps for traffic light states for opposite roads 4.

states$ we notice that the euation has the form

G xx=xx (C'+D ') . The same pattern can be observedfor the yellow states E Y xx=xxCD . Only the two mostsignificant bits are changed as we move from panel to panel.'lso note that the euations of the green and yellow states arecomplementary in the same panel so that G+Y=1 . Infact$ if we use De "organGs theorem on the euation of the

green states$ we could write Gxx=xx (CD ) ' $ fromwhich it is obvious that the least two significant bits are 2ustthe complement of the yellow stateGs least two significant bits

E namely CD. Now$ instead of using two 7-input 'ND gatesand a 4-input OR gate for each green state$ we could haveused a single 4-input N'ND gate for all the green states.1imilarly$ we could have used a single 4-input 'ND gates forall yellow states. )e will deal with the red states later on.

One may argue that the proposed simplification wouldresult in all green states simultaneously active at all panelsH thesame case for the yellow states. )hat we will do now is to

analy,e the two most significant bits$ which will nowdetermine the panel whose green or yellow state is active. Thetable below shows which panel is active as a function of thetwo most significant bits ' and !.

T'!(& 7-/TRUT%T'!(OR'CTIJ&9'N&(1'1' #UNCTIONO#' 'ND!

' ! 13 (3 14 (4B B 3 B B BB 3 B 3 B B3 B B B 3 B3 3 B B B 3

's discussed in Chapter 4$ the truth table is reminiscent of a

4-to-6 decoder circuit. &ssentially$ the decoder acts as aselector that determines which panel will have an active greenor yellow state. The red state will then be 2ust the complementof the selector bit for each panel.

%owever$ we must mae ad2ustments so that we may beable to implement it by using commercially available ICs. Onesuch IC is the dual 4-to-6 decoder CD6//< whose output isactive (O). This means that all the outputs of the decodermust be complemented to obtain the truth table shown in Table7-/. In this regard$ we decided to create a logic circuit out oftransistors to tae advantage of this characteristics and tominimi,e the costs. The transistori,ed logic circuit behindeach panel is shown below0


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#ig. 7-:. Transistori,ed logic circuit behind each traffic light panel.

The transistori,ed logic circuit provides several advantagesthan using ICs0 first is the reduced cost for implementing thelogic circuit for each traffic light panel$ second is that thecircuit will provide larger current handling capability than ifICs were used and third is that it reuires less wiring thanusing ICs. The transistori,ed circuit also allows us to use theconcept of multiple+ing. The circuitGs truth table is shown onTable 7-


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#ig. 7-33. The physical panel setup for the traffic light (&Ds and 5-segmentdisplay

Note that the set of red$ yellow and green states on the rightside is for the straight flow while on the left side is for theleftward flow. !ased from the considerations stated earlier$Table 7-5 shows the seuence of countdown that is loaded to5-segment display whenever a light state transition occurs.

T'!(& 7-5(O'D&DCOUNTDO)N1&AU&NCOR' 5-1&8"&NTDI19('INO99O1IT&

RO'D13

1tate 1tarting Countdown Display813 3413 68(3 34(3 6R+3 74

The time displayed for the duration of the red state iscalculated by adding the duration of green and yellow statesfor each side of the physical panel$ so that12+4+12+4=32 . The same loaded countdown

seuence applies to the physical panel corresponding to the

opposite road. #or the second pair of opposite roads$ the tablebelow shows the seuence of countdown that is loaded to 5-segment display whenever a light state transition occurs.

T'!(& 7-(O'D&DCOUNTDO)N1&AU&NCOR' 5-1&8"&NTDI19('INO99O1IT&

RO'D14

1tate 1tarting Countdown DisplayR+4 74814 3414 68(4 34(4 6

Note that the loaded seuence for opposite roads 4 is 2ust

the complement of the opposite roads 3H that is whenever thetraffic light state on opposite roads 3 is not in red state$ thestarting countdown display for opposite roads 4 is 74 and viceversa.

%aving stated that the duration of the yellow state is 6seconds$ we must now modify the seuential circuit from the

previous section. The modification is as follows0 the clocinput for 56(1:7 >from #ig. 7-3B? is to be connected to aseuential circuit so that the transition occurs for every 6seconds that the cloc triggers. The synthesis of the circuit isessentially the same as discussed in the previous section.

%owever$ since the number of states is 2ust 6$ the reuirednumber of flip-flops is 2ust 4. #ollowing the procedure asdiscussed in the previous section$ the synthesi,ed circuit isshown below0

#ig. 7-34. The 6-state seuential circuit to replace the cloc in 56(1:7.

In effect$ the total number of states once the circuit in #ig.7-34 is to be connected becomes 2

6=64 states. Thefigure below shows how the synthesi,ed circuit from #ig. 7-34is connected to the cloc input of 56(1:7 by means of a

N'ND gate.

#ig. 7-37. The modified seuential circuit based from #ig. 7-3B.'ll


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4 B L L L L L L L L7 B L L L L L L L L6 B L L L L L L L L/ B L L L L L L L L< B L L L L L L L L5 B L L L L L L L L B L L L L L L L L: B L L L L L L L L

3B B L L L L L L L L33 B L L L L L L L L34 3 B B B B B 3 B B37 B L L L L L L L L36 B L L L L L L L L3/ B L L L L L L L L3< 3 B B B 3 B B 3 B35 B L L L L L L L L3 B L L L L L L L L3: B L L L L L L L L4B B L L L L L L L L43 B L L L L L L L L44 B L L L L L L L L

47 B L L L L L L L L46 B L L L L L L L L4/ B L L L L L L L L4< B L L L L L L L L45 B L L L L L L L L4 3 B B B B B 3 B B4: B L L L L L L L L7B B L L L L L L L L73 B L L L L L L L L74 3 B B 3 3 B B 3 B77 B L L L L L L L L76 B L L L L L L L L7/ B L L L L L L L L7< B L L L L L L L L75 B L L L L L L L L7 B L L L L L L L L7: B L L L L L L L L6B B L L L L L L L L63 B L L L L L L L L64 B L L L L L L L L67 B L L L L L L L L66 B L L L L L L L L6/ B L L L L L L L L6< B L L L L L L L L65 B L L L L L L L L

6 B L L L L L L L L6: B L L L L L L L L/B B L L L L L L L L/3 B L L L L L L L L/4 B L L L L L L L L/7 B L L L L L L L L/6 B L L L L L L L L// B L L L L L L L L/< B L L L L L L L L/5 B L L L L L L L L/ B L L L L L L L L

/: B L L L L L L L L


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7 B L L L L L L L L7: B L L L L L L L L6B B L L L L L L L L63 B L L L L L L L L64 B L L L L L L L L67 B L L L L L L L L66 3 B B B B B 3 B B6/ B L L L L L L L L

6< B L L L L L L L L65 B L L L L L L L L6 3 B B B 3 B B 3 B6: B L L L L L L L L/B B L L L L L L L L/3 B L L L L L L L L/4 B L L L L L L L L/7 B L L L L L L L L/6 B L L L L L L L L// B L L L L L L L L/< B L L L L L L L L/5 B L L L L L L L L/ B L L L L L L L L

/: B L L L L L L L L


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hardware implementation. The circuit for the traffic light stateseuential circuit together with the modification made for the5-segment display is shown on #ig. 6-3. Notice that the flip-flops that were used where * flip-flop instead of T flip-flops

because it is commercially available and can reproduce thesame function as the T flip-flop. The timer circuit generatorthat was used uses the ("/// timer IC whose resistance andcapacitance values where ad2usted to generate a 3 %, suare

waveform output.The logic analy,er was connected to the output of the 4 *

flip-flops and the 56(1:7 binary counter so that the firstwaveform shows the least significant bit and the si+thwaveform shows the most significant bit. The output of thelogic analy,er is shown on #ig. 6-4. The bottom mostwaveform shown is the cloc waveform. Notice that it has thehighest freuency among all other waveforms. The length oftime that the seuential circuit state repeats is about


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J. CONC(U1ION'NDR&CO""&ND'TION1

!ased from the results obtained from the previous chapter$ thesimulation results shows that the desired seuential circuit thatwas synthesi,ed in the third chapter met the e+pected timingdiagrams. )e are also able to demonstrate the effectiveness of

#ig. 6-4. The output of the logic analy,er for the * flip-flops and 56(13:7binary counter.

the seuential circuit synthesis methods to perform the desiredtraffic light state transitions$ as well as synthesi,ingcombinational circuits to properly load the countdown timerthat the 5-segment (&D displays must display. %owever$several modifications for the circuit in simulation$ such as

placing an RC networ$ may not be necessary when the circuitis to be implemented in reality. The RC networs present in

the circuit is used to eliminate any spurious signals caused bythe delay in the propagation of the result of logic operationsand in fact is inherent to the computerGs processing power.

#ig. 6-7. The output of the logic analy,er for the traffic light state transitions.

)e found out that it may be possible to modify the circuitso that the timer countdown is fle+ible E that is for e+amplethat the duration of a green light state need not be always 34seconds. #or further improvements$ it would even be better ifthere is an input mechanism for which the circuit would basethe duration of each light state without referring to aninternally set value. It may be achieved by the use of DI9switches and the use of binary adder logic circuits.


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#ig. 6-6. The logic circuit simulation for the combinational circuit used forloading the proper countdown display at traffic light state transitions.

#ig. 6-/. The output of the logic analy,er for the load pin combinationalcircuits.


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#ig. 6-ptimi?ation$ CRC 9ress$4BB/$ pp. :B3-:B7.

M4 D. !. 9dPr$ ;(&CTUR&0 (O8IC >!OO(&'N?'(8&!R' 'ND '99(IC'TION1$; Qbuda University$"icroelectronics and Technology Institute$ 4B34-4B37.

M7 %. 8oyal$ ;Understanding of IC/// Timer and$;


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International ournal of In8enti8e Engineering and

&!ien!es @IIE&0 vol. 7$ no. 4$ pp. 4-7$ 4B3/.

M6 a. hassaei$ ;/// Timer0 'stable "ode Circuit$; 'utodes$Inc.$ 4BB/. MOnline. 'vailable0http0==www.instructables.com=id=///-Timer='((1T&91.M'ccessed 34 uly 4B3/.

M/ T. Dean$ inet6or* uide to et6or*s$ !oston$ "'$Cengage (earning$ 4BB:$ pp. 4-/.

M

synthesis of a traffic light sequence circuit

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