system level co-design of chip-package-pcb systems using

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System Level Co-design of

Chip-Package-PCB Systems Using Native Design

Databases in a Unified 3D Cockpit

James Church

SOZO R&D OfficeJune 9, 2015

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Agenda

• System Level Design Challenges

• Existing flows: Strengths and Weaknesses

• A Novel Approach to System Design and Visualization

• Commitment to Collaboration

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System-level Co-design Paradigms

System

Co-Design

Chip |Interposers

Package

| SiP | POP

PCB | FPCB | Rigi-flex

Mechanical enclosure

2.5/3D design, IO

optimization, and

visualization

IO assignment,

routability and

performance

Simulation and analysis:

Thermal, EM, RF

Electrical

mechanical

DRC, MRC rules and

electrical and physical

constraints

Support for any

combination of co-

design is key!

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Barriers to Efficient Co-design Realization

IC Flow Package FlowSpreadsheets!

Format A Format B

Walled Silo Approach

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Walled Silo Approach

• Limited inter-module data set

easy to email/transfer

• Efficient module-limited

optimization

• Established and known tools

and flows

• Limited cross functional data

exchange

• File exchange software lacks

robust automation and testing

• No built in ECO control

• Data coherency information

during frantic tapeouts

• No insight into detailed design

constraints/degrees of

freedom in adjacent modules

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Barriers to Efficient Co-design Realization

IC Flow Package Flow

Co-design

Flow

New tools!

Additive Tool Approach

Format A Format B

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Co-design 1.0 Approach

• Dedicated tools for dedicated

functions

• Large datasets reduced to

simple shapes and functions

• Abstracted view focus on

interchange points

• Additional tools, time, training

and expense

• Bigger design loop between

planning and detailed design

• Additional database

translations and design

coherency considerations

• Disconnect between detailed

design, layout, and planning

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Efficient Co-design

• Requires design abstraction and detailed implementation to be

closely coupled

• Requires optimizations to be based on real, fabric specific rules

• Shouldn’t require new user interface to manage the different parts

for similar functions

Multiple tools, multiple interfaces and multiple cockpits!

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IC

Rules

Technologies

Constraints

OpenAccess

Hierarchical System Level Approach

Package Flow PCB Flow

Single Cockpit with Concurrent

Multi-database support

IC Flow

Package

Rules

Technologies

ConstraintsPCB

Rules

Technologies

Constraints

Package

Manufacturing

PCB

Manufacturing

IC

Manufacturing

Zuken Native Database

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Single Platform to Design and Manage ICs, Packages, and PCBs

PCBSoC SiP

PCBSiP

Si-IPSoC

PCB

PKG-A

PKG-B

Support for hierarchical structures for multi-technology and multi-object allows

easy creation of system-level structures and interconnects

LSI-B

Si-Interposer

LSI-C

LSI-A

SoC/SiP/PCB Co-design

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Advanced Multi-Fabric SupportSupport for 3D Stacked Technologies

• Design any technology:

– Flip-Chip, Wire-Bond, System-in-Package, Multi-

Chip Module

– PCB/Flex-PCB

– IC/SoC

• Hierarchical database enables

– PoP/PiP/SiP

– Stacked, Adjacent, Embedded, IC

– Interposer

– Multiboard, Multipackage, Multi-IC

• Native 3D environment provides 2D and 3D

design rule checking

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Top-down Bottom-up

Chip IOPlanning

RDL RoutePKG Escape

PKG Pin Assign

PCBFloorplan

PCB-drivenPKG Pin Assign

Order IO Placement

OpenAccess

IC + Package

PCB-drivenImport Ball Map

OpenAccess Enables Both Planning

Abstraction and Detailed Co-design

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Open Standards from JEITA and IEEE for

Muti-design Netlisting

SI

PI

Post design analysis

Conceptual design

PKGLSI Board

EMI

Optimization

Timing

LVS

Design

feedback

Component

Design Rule

Project

Manage

N-Format N-Format N-Format N-Format

C-Format

R-Format

G-FormatM-Format

Geometry

Detailed

design

1. Project Manage (M-Format)

2. Netlist (N-Format)

3. Component (C-Format)

4. Design Rule (R-Format)

5. Geometry (G-Format)

6. Glossary

LPB Format

system level co-design of chip-package-pcb systems using

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