packaging and pcb/package co/design - cst · pdf filepackaging and pcb/package co/design . cst...

CST – COMPUTER SIMULATION TECHNOLOGY | www.cst.com CST – COMPUTER SIMULATION TECHNOLOGY | www.cst.com

Packaging and PCB/Package

Co/Design

CST – COMPUTER SIMULATION TECHNOLOGY | www.cst.com

Introduction

CST flow for packaging design

Simplifying complex models

Model decomposition and partitioning approach

PCB/package co-design

Conclusions

Outline


Memory interfaces have single-ended data rates in

the 1GHz-plus range and serial links are running

upwards of 10 Gb/s.

A precise design is required at the chip/package and

PCB level.

The analysis and optimization must be done in a

global context.

Physical design issues come into play as a full 3D

problem.

Introduction


Packaging Design Overview

Bond wires

Flip chip bumps or wire bonds

Transmission lines

Micro vias

PTH vias

BGA balls

Horizontal and vertical discontinuities


Package EM Simulation Workflow

Pre layout

analysis

Fast post layout

analysis

3D full wave post

layout analysis

and verification


Parameter Sweep/Optimization BGA — Micro via to PTH optimization

TDR



Pre layout

analysis

Fast post layout

analysis

3D full wave post

layout analysis

and verification


Package IBIS Model Header


Fast Post Layout Workflow Select Nets


RLCG Extraction Macro



Pre layout

analysis

Fast post layout

analysis

3D full wave post

layout analysis

and verification


3D Full Wave Analysis

output

NEXT NEXT

in


3D Full Wave Extraction R/2 R/2 L/2 L/2

G C BGA DIE


Field plots

Surface current – 10GHz

H-field (10GHz) H-field (1GHz)


PCB/Package Co/Design Overview

Memory

Int.

Antenna

SiP

PCB

RF/

Analogue Die

Digital Block

3

2

1

4

2

4

2

1

Courtesy Dr. I. Ndip, Fraunhofer Institute, Berlin Germany


Package-PCB Interface (#) Where to truncate PCB and/or package?

(#) X.Jiang, H. Shi, “Effective Die-package-PCB Co-Design methodology and its deployment in 10Gbps serial link

transceiver FPGA packages”, on IEEE Proceedings of IMS 2009


Test Structure

Model decomposition


Results — S-Parameters

... Full model

__ partitioned model

At higher frequencies

results of full model differ

from results of partitioned

models


Surface Current

10 GHz


PCB/Package Co-Design

Package PCB

PCB/package merge operation

Copy/paste

Import as sub project

SAM (System Assembly Modeling)


SAM Modeling

Product selection

Template selection for customized

settings

Solver choice

Reference model for settings


Example

Package PCB


Time and Frequency Domain Results

Return loss Insertion loss

NEXT

FEXT

Package PCB

Input

Output NEXT FEXT


Eye Diagram

Eye diagram properties


Field Plot Field well defined in isolated GND


Sim time on 4 GPU system: 14h, 37min

Board size: 313x300mm

Smallest trace distance: 0.02mm

Full Model


Effect of Model Truncation


Surface Current Full Model — 10 GHz


CST solutions has been demonstrated for package

simulation

From pre-layout to 3D full wave post layout CST offers

complete EM workflow

SAM can be used to simplify PCB/package co-design

workflow

Conclusions

packaging and pcb/package co/design - cst · pdf filepackaging and pcb/package co/design . cst...

Documents