SoC Co-Design: Co-Specification Models

Dr. Eng. Amr T. Abdel-Hamid

ELECT 1002

Spring 2009

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Co-Specification (System Model Generation): Developing system specification that describes hardware software modules and relationship between the hardware and software.

Model the (embedded) system functionality from an abstract level. No concept of hardware or software. Common environment: SystemC: based on C++.

Co-Synthesis: Automatic and semi Automatic design of hardware and software modules to meet the specification

Partitioning: Dividing the functionality of an embedded system into units

of computation Scheduling:

Assign an execution start time to each task in a set, where tasks are linked by some relations

SoC HW/SW Co-Design

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Allocation: Determining on which processing elements (PEs) some

computation will occur Select the number and type of communication links

and processing elements for the target system. Assignment (Mapping):

Choosing particular component types for the allocated computation units

Co-Simulation and Co-verification Simultaneous simulation of hardware and software

SoC HW/SW Co-Design

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SOC Design Tasks1. Model Generation (Co-Spec.)

Bus-arbitrationmodel

Specificationmodel

1

PE-assembly model

2

Time-accurateCommunication

model

3

Implementation model

4

Cycle-accurateComputation

model

5

6

SystemDesign

ComponentDesign

2. Bus-arbitration model generation (Co-Spec.)

3. Protocol refinement (Co-Synthesis)

4. RTL synthesis (Co-Synthesis)

5. IP replacement (Co-Synthesis)

6. Interconnect network generation (Co-Synthesis)

7. Co-Simulation???

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A representation of a system that can be used to describe its functionality independent of its implementation in hardware or software

Allows hardware/software partitioning to be delayed until trade-offs can be made

Typically used at a high-level in the design process Provides a simulation environment after partitioning is done,

for both hardware and software designers to use to communicate

Supports cross-fertilization (Design Modifications) between hardware and software domains

Unified HW/SW Representation

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Hardware Software Model

Uses a unified representation of the system to allow early performance analysis

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System Models: State-oriented models: Finite-state machine (FSM), Petri

net Activity-oriented models: Dataflow graph, Flowchart Structure-oriented models: Block diagram, RT netlist, Gate

netlist Data-oriented models: Entity-relationship diagram, Jackson’s

diagram Heterogeneous models: FSM/dataflow graph, State charts,

*Charts. Specification Languages:

UML SystemC SpecC SystemVerilog ESTEREL SDL

Unified HW/SW Representation

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Models and Architectures

Models are conceptual views of the system’s functionality Architectures are abstract views of the system’s

implementation

Model: a set of functional objects and rules for composing these objects

Architecture: a set of implementation components and their connections

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Example: An Elevator Controller Model

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Example: An Elevator Controller Architecture

Processor

Memory

I/O Ports

Flip-Flops

CLCI/O

System Level

(General Purpose Proc.)

Hardware (RTL) Description

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State-oriented models: Finite-state machine (FSM), Petri net, ASMs

Activity-oriented models: Dataflow graph, Flowchart

Structure-oriented models: Block diagram, RT netlist, Gate netlist

Data-oriented models: Entity-relationship diagram, Jackson’s diagram

Heterogeneous models: FSM/dataflow graph, State charts, *Charts.

System Models:

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Data Flow Diagram

W = Z * (X+Y)

support hierarchy suitable for specifying complex

transformational systems inherent data dependencies

do not express temporal behaviors or control sequencing

weak for modeling embedded systems

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Graphs contain nodes corresponding to operations in either hardware or software

Often used in high-level hardware synthesis Can easily model data flow, control steps, and concurrent

operations because of its graphical nature.

Pipeline Representation

Heterogeneous: Data Control Flow Graphs

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Reactive System continuously react to external and internal stimuli at their

environment’s speed e.g. telephones, automobiles, operating system, etc.

To describe reactive behavior: states and events are good medium

Advantage used to describe and analyze control sequences yield better to analysis and synthesis than alternative control

models due to their finite nature

Finite State Machines

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State Transition Diagrams Used to visually represent an FSM Emphasis is on identifying states and possible transitions

Circles represent States Arrows represent Transitions

Initial State

State

Transitions

01/01

01/11

S3 S2

S1S0

1-/11

01/10011/0011/10

Input/Output

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State tables

Table is another way to represent an FSM with an emphasis on exploring all Event/State combinations

Similar to the truth table Doesn’t contain the system clock when specifying its

transitions (it is implicit that transitions occur only when allowed by clock)

Unless different stated, all the transitions are occurring on the positive edge of the clock

Present State

Inputs Next State

Outputs

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FSM Example

General Machine Description: deliver package of gum after 15 cents deposited single coin slot for dimes, nickels no change

Vending Machine

FSM

N

D

Reset

Clk

OpenCoin

SensorGum

Release Mechanism

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Vending Machine Example

Present State

0¢

5¢

10¢

15¢

D

0 0 1 1 0 0 1 1 0 0 1 1 X

N

0 1 0 1 0 1 0 1 0 1 0 1 X

Inputs Next State

0¢ 5¢ 10¢ X 5¢ 10¢ 15¢ X

10¢ 15¢ 15¢ X

15¢

Output Open

0 0 0 X 0 0 0 X 0 0 0 X 1

Reset

N

N

N, D

[open]15¢

0¢

5¢

10¢

D

D

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Mealy FSM

The FSM where the outputs are used immediately

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Moore FSM

Each bit of the output is passed through a memory element.

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Mealy FSM

Output is dependent on the inputs and the current state

state 1 state 2

transition condition 1 /output 1

transition condition 2 /output 2

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Moore FSM Output is dependent only on the current state

state 1 /output 1

state 2 /output 2

transitioncondition 1

transitioncondition 2

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Moore vs. Mealy FSM

Moore and Mealy FSMs can be functionally equivalent Equivalent Mealy FSM can be derived from Moore FSM and vice

versa Mealy FSM Has Richer Description and usually requires

smaller number of states Smaller circuit area

Mealy FSM computes Outputs as soon as Inputs change Mealy FSM responds one clock cycle sooner than equivalent

Moore FSM Moore FSM has no combinational path between Inputs and

Outputs Moore FSM is more likely to have a shorter critical path

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Mealy FSM - Example

Mealy FSM that Recognizes Sequence “10”

S0 S1

0 / 0 1 / 0 1 / 0

0 / 1

Meaning of states: S0: No elements of the sequence observed S1: “1” observed

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Moore FSM - Example

Moore FSM that Recognizes Sequence “10”

S0 / 0 S1 / 0 S2 / 1

00

0

1

11

reset

Meaning of states: S0: No elements of the sequence observed S1: “1” observed S2: “0” observed

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Disadvantage Flat fashion, lots of states result in unstructured,

unrealistic, and chaotic state diagram (State Space Explosion)

Not suitable for describing concurrent system

Solution: Abstract State Machines (ASMs) Hierarchical Concurrent Finite State Machine

(HCFSM or State Charts) Hierarchical Finite State Machines with Multiple

Concurrency Models (*Charts)

Finite State Machines

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Quake Example

Types of behavior to capture: Wander randomly if don’t see or hear an enemy When see enemy -> attack When hear an enemy -> search and chase When die -> Spawn If health is low and see an enemy ->retreat

Extensions: When see power-ups during wandering -> collect them

Exactly borrowed from John Laird and Mike van Lent’s GDC tutorial

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Example FSM

States: E: enemy in sight S: sound audible D: dead

Events: E: see an enemy S: hear a sound D: die

Action performed: On each transition On each update in

some states (e.g. attack)

SpawnD

Wander~E,~S,~D

~E

D

AttackE,~D~E

E

E

D

~S

ChaseS,~E,~D

E

S

S

D

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Example FSM Problem

States: E: enemy in sight S: sound audible D: dead

Events: E: see an enemy S: hear a sound D: die

SpawnD

Wander~E,~S,~D

~E

D

AttackE,~D~E

E

E

D

~S

ChaseS,~E,~D

E

S

S

D

Problem: Can’t go directly from attack to chase. Why not?

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Better Example FSM

States: E: enemy in sight S: sound audible D: dead

Events: E: see an enemy S: hear a sound D: die

Extra state to recall whether or not heard a sound while attacking

SpawnD

Wander~E,~S,~D

~E

D

AttackE,~S,~D~E

E

E

D

~S

ChaseS,~E,~D

S

S

D

E

Attack-SE,S,~D

~E

~S

S

D

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Example FSM with Retreat

SpawnD

(-E,-S,-L)

Wander-E,-D,-S,-L

E

-SAttack-EE,-D,-S,-L

E

Chase-E,-D,S,-L

S

D

S

D

D

Retreat-EE,-D,-S,L

L

-E

Retreat-S-E,-D,S,L

Wander-L-E,-D,-S,L

Retreat-ESE,-D,S,L

Attack-ESE,-D,S,-L

E

E-E

-L

S

-S

L

-E E

L-L

-L

-L

L

D

• States:– E: enemy in sight– S: sound audible– D: dead– L: Low health

• Worst case: Each extra state variable can add 2n extra states• n = number of

existing states

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Hierarchical FSMs

What if there is no simple action for a state? Expand a state into its own FSM, which explains what to do

if in that state Some events move you around the same level in the

hierarchy, some move you up a level When entering a state, have to choose a state for it’s child

in the hierarchy Set a default, and always go to that Or, random choice Depends on the nature of the behavior

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Hierarchical FSM Example

Note: This is not a complete FSM All links between top level states

still exist Need more states for wander

StartTurn Right

Go-throughDoor

Pick-upPowerup

Wander Attack

Chase

Spawn

~E

E~S

SD

~E

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HCFSM (StateCharts)

Extension of conventional FSMs by David Harel: (1987) Hierarchy Concurrency Communication

StateCharts Highly structured and economical description language Compact Expressive Compositional Modular

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StateCharts

Classical automata not useful for complex systems

(complex graphs cannot be understood by humans).

Introduction of hierarchy StateCharts [Harel, 1987]

StateChart = the only unused combination of “flow“

or “state“ with “diagram“ or “chart“

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Introducing hierarchy

FSM will be in exactly one of the substates of S if S is active(either in A or in B or ..)

FSM will be in exactly one of the substates of S if S is active(either in A or in B or ..)

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StateCharts: Hierarchy

When a superstate is active, exactly one of its substates is active

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Definitions

• Current states of FSMs are also called active states.• States which are not composed of other states are called

basic states.• States containing other states are called super-states.• For each basic state s, the super-states containing s are

called ancestor states.• Super-states S are called OR-super-states, if exactly

one of the sub-states of S is active whenever S is active.

ancestor state of Esuperstate

substates

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OR States

•An OR-state can contain other states as its internal substates (hierarchical internal structure);• super OR-state is active, if and only if one of its immediate substates is active (exclusive or);• When the control enters a (super) OR-state, its default substate is entered and becomes active;• When the control leaves a (super) OR-state, all its substates become inactive!

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Default state mechanism

Try to hide internal structure from outside world! Default stateFilled circleindicates sub-state entered whenever super-state is entered.Not a state by itself!

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Combining history and default state mechanism

same meaning

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History mechanism

For input m, S enters the state it was in before S was left (can be A, B, C, D, or E). If S is entered for the very first time, the default mechanism applies.History and default mechanisms can be used hierarchically.

(behavior different from last slide)

km

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StateCharts: Concurrency

And Decomposition: Orthogonal product of A and D

A = {B, C}D = {E, F, G}Y = A X D

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ConcurrencyConvenient ways of describing concurrency are required.AND-super-states: FSM is in all (immediate) sub-states of a super-state; Example:

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And States

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Entering and leaving AND-super-states

Line-monitoring and key-monitoring are entered and left, when service switch is operated.

incl.

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Timers

Since time needs to be modeled in embedded systems, timers need to be modeled. In StateCharts, special edges can be used for timeouts.

If event a does not happen while the system is in the left state for 20 ms, a timeout will take place.

If event a does not happen while the system is in the left state for 20 ms, a timeout will take place.

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Using timers in answering machine

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Broadcast mechanism

Values of variables are visible to all parts of the StateChart model.New values become effective in phase 3 of the current step and are obtained by all parts of the model in the following step.

StateCharts implicitly assumes a broadcast mechanism for variables.

StateCharts is appropriate for local control systems (), but not for distributed applications for which updating variables might take some time ().

StateCharts implicitly assumes a broadcast mechanism for variables.

StateCharts is appropriate for local control systems (), but not for distributed applications for which updating variables might take some time ().

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StarCharts (*charts)

Limitation on concurrency of HCFSM StateCharts loosely defines state transitions in concurrent

FSM’s to be simultaneous Broadcast mechanism Undetermined behavior on circular dependencies

*Charts are models of computation supporting concurrency better

Loosely synchronized concurrency model Dataflow

Tightly synchronized concurrency model Discrete Event Synchronous/Reactive (SR)

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*Charts

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Architectures

Application-specific architectures Controller architecture, Datapath architecture, Finite-state machine with datapath (FSMD).

Single-purpose processor General-purpose processors

Complex instruction set computer (CISC)Reduced instruction set computer (RISC)Vector machineVery long instruction word computer (VLIW)Parallel processors

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Processor technology

Processors vary in their customization for the problem at hand

total = 0for i = 1 to N loop total += M[i]end loop

General-purpose processor

Single-purpose processor

Application-specific processor

Desired functionality

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General-purpose processors

Programmable device used in a variety of applications Also known as “microprocessor”

Features Program memory General datapath with large register file

and general ALU User benefits

Low time-to-market and NRE costs High flexibility

“Pentium” the most well-known, but there are hundreds of others

IR PC

Registerfile

GeneralALU

DatapathController

Program memory

Assembly code for:

total = 0 for i =1 to …

Control logic and

State register

Datamemory

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Single-purpose processors

Digital circuit designed to execute exactly one program a.k.a. coprocessor, accelerator or

peripheral Features

Contains only the components needed to execute a single program

No program memory Benefits

Fast Low power Small size

DatapathController

Control logic

State register

Datamemory

index

total

+

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Application-specific processors

Programmable processor optimized for a particular class of applications having common characteristics Compromise between general-purpose

and single-purpose processors Features

Program memory Optimized datapath Special functional units

Benefits Some flexibility, good performance, size

and power

IR PC

Registers

CustomALU

DatapathController

Program memory

Assembly code for:

total = 0 for i =1 to …

Control logic and

State register

Datamemory

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Controller Architecture (Mealy FSM)

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Datapath architecture

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FSMD (FSM + DATA)

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Conclusion

Different models focus on different aspects Proper model needs to represent system’s features Models are implemented in architectures Smooth transformation of models to architectures increases

productivity

Readings Assignment: D. Harel, "Statecharts: A Visual Formalism for Complex Systems", Sci. Comput.

Programming 8 (1987), 231-274. (Group: ??) Alain Girault, Bilung Lee, and Edward A. Lee, “Hierarchical Finite State Machines

with Multiple Concurrency Models”, IEEE Transactions On Computer-aided Design Of Integrated Circuits And Systems, Vol. 18, No. 6, June 1999. (Group: ??)

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References

D. Harel, "Statecharts: A Visual Formalism for Complex Systems", Sci. Comput. Programming 8 (1987), 231-274.

Alain Girault, Bilung Lee, and Edward A. Lee, “Hierarchical Finite State Machines with Multiple Concurrency Models”, IEEE Transactions On Computer-aided Design Of Integrated Circuits And Systems, Vol. 18, No. 6, June 1999.

+ many others