TDA9102C/T

H/V PROCESSOR FOR TTL V.D.U

May 1994

DIP20 (0.25)(Plastic package)

ORDER CODES : TDA9102C/T

HORIZONTAL SECTION.SYNCHRONIZATION INPUT : TTL COMPAT-IBLE, NEGATIVE EDGE TRIGGERED.SYNCHRONIZATION INDEPENDENT FROMDUTY CYCLE TIME.OSCILLATOR : FREQUENCY RANGE FROM15kHz to 100kHz.HORIZONTAL OUTPUT PULSE SHAPERAND SHIFTER.PHASE COMPARATOR BETWEEN SYN-CHRO AND OSCILLATOR (PLL1).PHASE COMPARATOR BETWEEN FLYBACKAND OSCILLATOR (PLL2). INTERNAL VOLTAGE REGULATOR.DC COMPATIBLE CONTROLS FOR PHASEAND FREQUENCY.HORIZONTAL OUTPUT DUTY CYCLE : 41%

VERTICAL SECTION.SYNCHRONIZATION INPUT : TTL COMPAT-IBLE, NEGATIVE EDGE TRIGGERED.SYNCHRONIZATION INDEPENDENT FROMDUTY CYCLE TIME.OSCILLATOR : FREQUENCY RANGE FROM30Hz to 120Hz.RAMP GENERATOR WITH VARIABLE GAINSTAGE.VERTICAL RAMP VOLTAGE REFERENCE. INTERNAL VOLTAGE REGULATOR.DC COMPATIBLE CONTROLS FOR FRE-QUENCY, AMPLITUDE AND LINEARITY

DESCRIPTION

The TDA9102C/T is a monolithic integrated circuitfor horizontal and vertical sync processing in mono-chrome and color video displays driven by inputTTL compatible signals.The TDA9102C/T is supplied in a 20 pin dual in linepackage with pin 11 connected to ground and usedfor heatsinking.

10

9

8

7

6

5

4

3

2

1

11

12

13

14

15

16

17

18

19

20

Horizontal Phase Adjust

Phase Comparator 2 Output

Horizontal Flyback Input

Horizontal Output

Horizontal Power Ground

C5

Horizontal TTL Input

Phase Comparator 1 Output

C2

R1

Substrate Ground

Vertical Frequency Preset

C13

Vertical TTL Input

Vertical Ramp Output

Vertical Amplitude Adjust

Vertical Linearity Adjust

Linearity Output

Vertical Reference Voltage

VS

9102

T-01

.EP

S

PIN CONNECTIONS

1/7

9102

T-02

.EP

S

BLOCK DIAGRAM

415

5

69

814

17

18

16

13

12

10

31

211

20

19

HO

RIZ

ON

TAL

FLY

BA

CK

INP

UT

VE

RTI

CA

LS

YN

C.

INP

UT

DC

VE

RTI

CA

LLI

NE

AR

ITY

AD

JUS

TEM

EN

T

DC

FR

EQ

UE

NC

YP

RE

SE

T

DC

VE

RTI

CA

LA

MP

LITU

DE

AD

JUS

TEM

EN

T

DC

FR

EQ

UE

NC

YA

DJU

STE

ME

NT

DC

HO

RIZ

ON

TAL

PH

AS

EA

DJU

STE

ME

NT

HO

RIZ

ON

TAL

SY

NC

.IN

PU

T

+ 5V

+ 5V

V S

V RE

F

TDA

9102

C/T

V S

VO

LTA

GE

RE

GU

LA

TO

R

VE

RT

ICA

LO

SC

ILLA

TO

R

ϕ2

PH

AS

EC

OM

PA

RA

TO

R

VE

RT

ICA

LT

TL IN

TE

RF

AC

E

LOW

SU

PP

LY

VO

LT

AG

EP

RO

TE

CT

ION

HO

RIZ

ON

TA

LO

SC

ILLA

TO

R

ϕ1

PH

AS

EC

OM

PA

RA

TO

R

HO

RIZ

ON

TA

LT

TL IN

TE

RF

AC

E

HO

R.

PU

LSE

SH

AP

ERR3

C3

C1

R2

R1

C2

R12

R18

C18

C13

C9

R8

R14

7

C5

R4

TDA9102C/T

2/7

ABSOLUTE MAXIMUM RATINGS

Symbol Parameter Value Unit

VS Supply Voltage 18 V

VSYNC Sync Input Peak Voltage + VS V

IOH Output Sinking Peak Current (Pin 7 ; t < 3µs) 2 A

I15 Output Current (Pin 15) - 10 mA

I19 Output Current (Pin 19) - 10 mA

Ptot Total power dissipation (Tamb < 70oC) 1 W

Tstg , Tj Storage and Junction Temperature - 40, + 150 oC

9102

T-0

1.T

BL

THERMAL DATA

Symbol Parameter Value Unit

Rth(j-a) Junction-ambient Thermal Resistance 80 oC/W

9102

T-02

.TB

L

ELECTRICAL CHARACTERISTICS(Tamb = 25oC, VS = 12V, refer to the test circuits, unless otherwise specified)

Symbol Parameter Test conditions Min. Typ. Max. Unit

HORIZONTAL SECTION

VS Supply Voltage Range 10.5 12 15.5 VIS Supply Current 40 70 mAV1 Voltage Reference at Pin 1 I1 = 0.5mA 3.2 3.5 3.8 VI1 Current at Pin 1 - 1 mAV2 Voltage Swing at Pin 2 3.7 4 4.3 VPP

K0 Free Running Frequency Constant fo = 1/(K0 x R1 x C2) 2.8 3.04 3.2V3 - V1 Control Voltage Range (See technical note 1) 1.6 2.5 V

I3 Peak Control Current 3 mA

K3Gain Phase Comparator φ1K3 = 2 x I3 / 360 17

µAdegree

V4 Sync Threshold Input (neg. edge) Sync high Sync low

2 80.8

VV

I4 Current at Pin 4 Input high Input low - 10

10 µAµA

T4 Input Pulse Duration T = 1/fH @ fH = 27.64kHz 1 0.9T µsV5 Monostable Threshold 5.6 6 6.4 Vt5 Internal Pulse Width (t5 = C5 x V5 /I5) C5 = 220 pF

(see technical note 2)3.6 µs

t7 Output Pulse Duration (low) - T = 1/fH fH = 27kHzfH = 70kHz

0.38T0.35T

0.41T0.39T

0.44T0.43T

µsµs

V7 sat Output Saturation Voltage I7 = 600 mA 1.2 2.5 VtD Permissible delay between output pulse

leading edge and flyback pulse leading edge

(for keeping a constant duty cycle) ; T = 1fH

See technical note 4@ fH = 27kHz

0.41 T - t FLY s

IFLY Flyback Input Current at Pin 8 Flyback On Flyback Off

0.7-1

2 mAmA

V8 Clamp voltage at Pin 8 I8 = 1mA I8 = - 1mA

0.6- 0.6

VV

I8 Current for switching low the output pulse 0.7 2 mAI9 Peak control current 0.9 mA

9102

T-03

.TB

L

TDA9102C/T

3/7

ELECTRICAL CHARACTERISTICS (continued)(Tamb = 25oC, VS = 12V, refer to the test circuits, unless otherwise specified)

Symbol Parameter Test conditions Min. Typ. Max. Unit

HORIZONTAL SECTION

K9 Phase sensitivity at Pin 9 (See technical note 3) 67.5degree

VV10 Control voltage range 0.5 4.5 V

K10 Phase control sensitivity at Pin 10 20 22.5 25degree

VHADJ Horizontal phase adjustment for V10 varying

from 0.5 to 4.5V (27.64kHz)Zero degree phase: flybackcentered on the middle of thepulse at Pin 5

- 45 + 45 degree

K1 Phase jitter constant (jitter = K1

106 . fH) 100 150 ppm

K2 Frequency drift versus supply voltage

K2 = dF . 106

dV . fH

VS = 10.5V to 15.5V 400 ppmV

VERTICAL SECTION

V12 Voltage reference at Pin 12 3.2 3.5 3.8 VI13

I12Current gain at Pin 13 I12 = 100µA

(I12 max. = 200µA) 0.94 1 1.06

V13 Typical Vertical Sawtooth Amplitude(Pin 13) for Center Frequency

To be adjusted by I12 4 VPP

tFALL Discharge time at Pin 13 C18 = 0.22 µF, V13 = 4VPP 10 22 µsfVL Maximum Vertical Frequency Vertical Sync Low

CPin 13 = 220nF, RPin 12 = 58kΩ84 Hz

fVH Minimum Vertical Frequency Vertical Sync HighCPin 13 = 220nF, RPin 12 = 58kΩ

56 Hz

K14 Synchro window constant ts = K14

fV(See technical note 6) 0.333

V14 Sync input threshold (negative edge) Sync high Sync Low

2 80.8

VV

I14 Current at Pin 14 Input high Input Low V14 = 0.8V - 10

10 µAµA

t14 Input pulse duration T = 1fV

@ fV = 64.75Hz 10 0.5T µs

V15 Average value of voltage on Pin 15 V13 = 4VPP, V16 = 2.5V 4 VII15I Output current at Pin 15 1 mAK15 Buffer gain constant at Pin 15

V15PP = K15 . V13PP

V16 = 2.5V 0.95

K16 Buffer variable gain constant at Pin 15 :

K16 = ∆V15PP

∆V16 . V13PP

2.5V < V16 < 4.5V0.5V < V16 < 2.5V

0.10.1

V -1

V -1

I16 Input bias current at Pin 16 V16 = 0.5V - 50 µAI17 Input bias current at Pin 17 V17 = 4.5V 50 µA

V18 Average voltage at Pin 18 : V18 = 2 + V18PP

2V17 = 3.5V, R18 not connected 3 V

K18 Linearity correction constant : K18 = ∆V18PP

∆V17V13PP = 4V,1.5V < V17 < 4.5V 1

V19 Voltage reference at Pin 19 (See technical note 5) 7.6 8 8.4 VI19 Current at Pin 19 2 mA 91

02T-

04.T

BL

TDA9102C/T

4/7

ELECTRICAL CHARACTERISTICS (continued)(Tamb = 25oC, VS = 12V, refer to the test circuits, unless otherwise specified)

Symbol Parameter Test conditions Min. Typ. Max. Unit

VERTICAL SECTION

K17 Frequency drift versus supply voltage K17 = dF . 106

dV . fVVS = 10.5V to 15.5V 300

ppmV

9102

T-0

5.T

BL

12

C2

R1

R2

I1

if

C1

C3

R3

3

HOR. SYNC.ϕ1HORIZONTALOSCILLATOR

V3L

V3H V3H VDC

VDCV3L

9102

T-0

3.E

PS

V (V)

t (s)

VL = 5.2V

= 6.8VVH

= 6VV

= 2VVLL

1/fvts

9102

T-0

4.E

PS

Technical note 1

fH (nom) = 26.8 kHzR1 = 6.8k ΩR2 = 56 kΩC2 = 1.8 nF

fpull-in = fH (nom) V3 − V1 / R2

V1 / R1 = fH (nom)

IfIo

(A)

where: V1 = 3.5V and V3 - V1 is the controlvoltage range.The voltage at Pin 3 is limited by two clampingdiodes at the voltage V3H and V3LWhen the PLL1 is synchronized and perfectlytuned, V3 = V1.

Remark : The value of C2 influences the horizontaloscillator free running frequency; it doesn’t effectthe relative pull-in range. If the horizontal fre-quency is changed by using R1, the pull-in rangechanges accordingly with the formula (A).

Technical note 2The internal pulse "t5", is generated by the currentgenerator "I5" charging the external capacitor"C5", according with the formula (B):

t5 = C5 . V5

I5 (B), t5 =

TH

12 is recommended.

Technical note 3K9 = 67.5 degrees/volt represents the slope of theoscillator charging period of the waveform atPin 2:

K9 = 360 x 0.75

4 degree

V

Technical note 4The second PLL can recover the storage of hori-zontal output stage maintaining a constant dutycycle till the trailing edge of the output pulse getsthe trailing edge of the flyback pulse. From thispoint on, only the leading edge of the output pulsewill be shifted covering a total phase shift of: 0.30T;overcoming this value, it will produce a notch in theoutput pulse (@ fH = 27kHz).

Technical note 5The voltage reference at Pin 19 can be used topolarize the DC operating point of the verticalbooster. This voltage corresponds to the double ofthe mean value voltage of the vertical sawtooth atPin 13.

Technical note 6

VH − VL

ts =

VH − VLL

1/fV

ts = (VH − VL)

(VH − VLL)

1fV

= K14

fV

TDA9102C/T

5/7

414

17

16

5 8 9

10

20

7

6 19

15

18

12

13

211

13

Ho

r. S

ync.

Ve

rt.

Syn

c.

Fly

. Inp

ut

7

2

6

3

5

41

TD

A81

72

Hor.

Out

Vert

.Y

oke

V 14VS

R1

0 2

2kΩ

C9

100n

F

C8

10

0 µF

R1

122k Ω

R12

10kΩ

C15

1µF

R20

150k Ω

R21

62

k ΩR

22

220k Ω

C16

220nF

C17

1.8

nF

C1

815nF

C19

2.2

µFR2

33.3

k Ω

R24

56kΩ

R25

6.8

k Ω

P4

47k Ω

P5

47k Ω

C20

22nF

R2

7 1

00kΩ

C21

0.2

2nF

R29

2.2

k ΩR

28

2.2

k Ω

R1

3.3

k ΩR

23

.3k Ω

R3

51

k Ω P1

47

k Ω R4

22

k Ω

P2

47k ΩR

539k Ω

C3

15nF

C4

15

nF

C5

15nF

R7

39

k Ω P3

47

k Ω

C1

100n

FC

2470 µ

F

C6

100nF

C7

1000 µ

FD

11N

400

1

C10

220 µ

F

C14 1

0µF

R18

1.2

k Ω

R17

2.7

kΩ

C13

47 µ

F

R15 1

.5k Ω

R1

41.5

ΩR

13

120 Ω

C12

220nF

C1

12

20

0 µF

R16

1Ω

"C"

Corr

ectio

n

R9

82 Ω 2W

IC3

VV

OI

G N D

IC1

7812

R6

5.1

k ΩR

85

.1k Ω

R26

22kΩ

R1

947k Ω

*

No

te : *

Th

e v

alu

e o

f R19 d

epen

ds

on

CR

T.

On

the m

ock

up R

19 is

su

bst

itue

dw

ith a

resi

sta

nce

+ trim

me

r fo

r ge

neri

c a

pplic

atio

ns.

Ho

r. P

ow

er

GN

D

TD

A91

02C

/TIC

2

9102

T-0

5.E

PS

APPLICATION DIAG RAM (with TDA8172)

TDA9102C/T

6/7

20 11

1 10

Ia1

L

B e

D

Z

bZ

e3

F

b1

E

PM

-DIP

20.E

PS

PACKAGE MECHANICAL DATA20 PINS - PLASTIC DIP (0.25)

DimensionsMillimeters Inches

Min. Typ. Max. Min. Typ. Max.a1 0.254 0.010B 1.39 1.65 0.055 0.065b 0.45 0.018

b1 0.25 0.010D 25.4 1.000E 8.5 0.335e 2.54 0.100

e3 22.86 0.900F 7.1 0.280i 3.93 0.155L 3.3 0.130Z 1.34 0.053

DIP

20.T

BL

Information furnished is believed to be accurate and rel iable. However, SGS-THOMSON Microelectronics assumes no responsibilityfor the consequences of use of such information nor for any infringement of patents or other rights of third parties which may resultfrom its use. No licence is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics.Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces allinformation previously supplied. SGS-THOMSON Microelectronics products are not authorized for use as critical components in lif esupport devices or systems without express written approval of SGS-THOMSON Microelectronics.

© 1994 SGS-THOMSON Microelectronics - All Rights Reserved

Purchase of I 2C Components of SGS-THOMSON Microelectronics, conveys a license under the PhilipsI2C Patent. Rights to use these components in a I 2C system, is granted provided that the system conforms to

the I 2C Standard Specifications as defined by Philips.

SGS-THOMSON Microelectronics GROUP OF COMPANIESAustralia - Brazil - China - France - Germany - Hong Kong - Italy - Japan - Korea - Malaysia - Malta - MoroccoThe Netherlands - Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A.

TDA9102C/T

7/7

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