TLCE - C2 14/10/2009

© 2009 DDC 1

14/10/2009 - 1 TLCE - C2 - © 2009 DDC

Politecnico di TorinoICT School

Telecommunication Electronics

C2 – D/A converters

» Parameters and errors» Taxonomy » Basic DAC structures» Sample circuits

TLCE - C2 14/10/2009

© 2009 DDC 2

14/10/2009 - 2 TLCE - C2 - © 2009 DDC

Lesson C2: D/A converters

• Parameters of D/A converters

• Classification of errors in D/A converters– Linear: gain and offset

– Integral and differential nonlinearity – Dynamic parameters

• DAC structures– Uniform and weighted architectures– Circuit examples

– Bipolar and multiplying circuits

• References: sect. 4.2

TLCE - C2 14/10/2009

© 2009 DDC 3

14/10/2009 - 3 TLCE - C2 - © 2009 DDC

0

S

0

1 M2

D

A

DAC transfer function

• Input variable (D) is discrete– The A(D) plot is a sequence of dots

– With constant Ad the dots are aligned

Ad

1 LSB

TLCE - C2 14/10/2009

© 2009 DDC 4

14/10/2009 - 4 TLCE - C2 - © 2009 DDC

S

0

M

D

A

Conversion characteristic

• M = 2N if high N � many dots: – the dot sequence becomes a continuous line.

0

TLCE - C2 14/10/2009

© 2009 DDC 5

14/10/2009 - 5 TLCE - C2 - © 2009 DDC

Errors in D/A converters

• Two types of errors

• Static errors– Constant input– Steady state behavior

– Appear in the A(D) diagram

• Dynamic errors– Variable input signal– Transient behavior– Appear in A(t)

TLCE - C2 14/10/2009

© 2009 DDC 6

14/10/2009 - 6 TLCE - C2 - © 2009 DDC

Static errors: two step analysis

• Which parameters define “how good” is a DAC ?

• The actual transfer function is not a straight line

• Two-step analysis:– Plot the best approximating straight line– Compare actual/ideal transfer functions in two steps

• 1: Actual transfer function � linear approximation– Nonlinearity errors

• 2: linear approximation � ideal transfer function– Linear errors: offset and gain

TLCE - C2 14/10/2009

© 2009 DDC 7

14/10/2009 - 7 TLCE - C2 - © 2009 DDC

Ideal and actual D/A characteristic

S

0D

A

actual

M0

ideal

TLCE - C2 14/10/2009

© 2009 DDC 8

14/10/2009 - 8 TLCE - C2 - © 2009 DDC

Approximation with straight line

S

0D

A

Best approximating straight line

M0

actual

TLCE - C2 14/10/2009

© 2009 DDC 9

14/10/2009 - 9 TLCE - C2 - © 2009 DDC

Ideal vs best linear approximation

S

0D

A

M0

ideal

Best approximatingstraight line

TLCE - C2 14/10/2009

© 2009 DDC 10

14/10/2009 - 10 TLCE - C2 - © 2009 DDC

Linear errors: offset and gain

• The approximation straight line does go across (0,0) and (M,S). The difference is described by:

• Offset εo : – Intercept of approximating line with A axis– Can be compensated adding a constant

• Gain error εg : – Difference among real and actual slope

– Can be compensated by gain correction

• This analysis methodology applies for any (nominally) linear transfer function

TLCE - C2 14/10/2009

© 2009 DDC 11

14/10/2009 - 11 TLCE - C2 - © 2009 DDC

Offset error

• Ideal transfer function– D = 0 ⇒⇒⇒⇒ A = 0

• Actual transfer function– Not through 0,0

– On the approximating straight line

– D = 0 ⇒⇒⇒⇒ A = Voff

• Offset error:

– εo = Voff

A

VoffD

TLCE - C2 14/10/2009

© 2009 DDC 12

14/10/2009 - 12 TLCE - C2 - © 2009 DDC

Gain error

• Ideal transfer function– A = K D

• Actual transfer function– Different slope

– For the approximating straight line

– A = K’ D

– K’ = K + ∆K

• Gain error:

– εg = ∆K/K

A εg

D

TLCE - C2 14/10/2009

© 2009 DDC 13

14/10/2009 - 13 TLCE - C2 - © 2009 DDC

Integral nonlinearity

0

S

0D

ANonlinearity band

M

maximum deviation of actual fdt from best straight line: integral nonlinearity error

Best approximatingstraight line

Actual transfer function

εinl

TLCE - C2 14/10/2009

© 2009 DDC 14

14/10/2009 - 14 TLCE - C2 - © 2009 DDC

Differential nonlinearity

0

0 D

A Actualtransfer function

AD A’D

Best linearapproximation

1 LSB

TLCE - C2 14/10/2009

© 2009 DDC 15

14/10/2009 - 15 TLCE - C2 - © 2009 DDC

Differential nonlinearity error

• Ideal transfer function: dots spaced AD (A axis) � 1 LSB (D axis)

• Actual transfer function: dots spaced A’D ≠ AD

• The difference AD - A’D = εdnl is the

differential nonlinearity

• If εdnl > 1 LSB, (slope inversion)

Non-monotonicity error

TLCE - C2 14/10/2009

© 2009 DDC 16

14/10/2009 - 16 TLCE - C2 - © 2009 DDC

Non-monotonicity error

0

S

0D

A

M

AD A’D

slope inversion

TLCE - C2 14/10/2009

© 2009 DDC 17

14/10/2009 - 17 TLCE - C2 - © 2009 DDC

Differential vs. integral nonlinearity

• Draw the conversion characteristic for a 3-bit DAC with:– εdnl = + 1/4 LSB from 000 to 011 (MSB = 0)– εdnl = - 1/4 LSB from 100 to 111 (MSB = 1)

• Draw the conversion characteristic for a 3-bit DAC with:– εdnl = + 1/4 LSB when LSB = 0 – εdnl = - 1/4 LSB when LSB = 1

• Compare the two cases– evaluate integral nonlinearity εinl

– evaluate offset and gain errors

TLCE - C2 14/10/2009

© 2009 DDC 18

14/10/2009 - 18 TLCE - C2 - © 2009 DDC

Overall view

S

0D

A

M0

non-linearityband

Best approximatingstraigth line

actual

ideal

TLCE - C2 14/10/2009

© 2009 DDC 19

14/10/2009 - 19 TLCE - C2 - © 2009 DDC

Settling time

• The D/A output takes a settling time Tsto reach the new value (within a specified error)

TLCE - C2 14/10/2009

© 2009 DDC 20

14/10/2009 - 20 TLCE - C2 - © 2009 DDC

Glitch

• In a transient the output can go to a widely wrong value (typically 0V or full-scale S).

• The spike is called GLITCH

TLCE - C2 14/10/2009

© 2009 DDC 21

14/10/2009 - 21 TLCE - C2 - © 2009 DDC

Where do glitches come from ?

• Glitches are caused by differences in switching delays of various bits.

– These delays causefaulty transient states (e.g. 1111 and 0000 when moving from 0111 to 1000).

– These states drive the output - for a very short time –towards 0V or full scale S.

• Glitches occur in transitions like x0111 � x1000– change is 1 LSB, – temporary state during the transient can be x0000 or x1111.

TLCE - C2 14/10/2009

© 2009 DDC 22

14/10/2009 - 22 TLCE - C2 - © 2009 DDC

DAC error summary

• Linear errors:

– gain: εG offset: εO

• Nonlinearity errors:

– Integral NL : εinl differential NL : εdnl

• Dynamic parameters– Settling time: tS Glitches

• Measured as – % of full scale S– Absolute value (mV, µV)

– Fraction of LSB (1/2 LSB, ¼ LSB, …)

TLCE - C2 14/10/2009

© 2009 DDC 23

14/10/2009 - 23 TLCE - C2 - © 2009 DDC

Lesson C2: D/A converters

• Parameters of D/A converters

• Classification of errors in D/A converters– linear: gain and offset

– Integral and differential nonlinearity – Dynamic parameters

• DAC structures– Uniform and weighted architectures– Circuit examples

– Bipolar and multiplying circuits

TLCE - C2 14/10/2009

© 2009 DDC 24

14/10/2009 - 24 TLCE - C2 - © 2009 DDC

D/A conversion basic circuits

• Sum of elementary quantities controlled by D

– Uniform elementary quantities (1, 1, 1, …)

– Weighted elementary quantities (1, 2, 4, …)

ELEMENTARY

QUANTITIESΣΣΣΣ

REFERENCE DIGITAL INPUT (D)

ANALOG OUTPUT (A)

TLCE - C2 14/10/2009

© 2009 DDC 25

14/10/2009 - 25 TLCE - C2 - © 2009 DDC

Uniform quantities

• Sum of elementary units with the same weight (1)

• The number of units is controlled by the digital value.

– Output = D * LSB

– Example:

13D = 1+1+1+1+1+1+1+1+1+1+1+1+1

• This is called uniform elements conversion

TLCE - C2 14/10/2009

© 2009 DDC 26

14/10/2009 - 26 TLCE - C2 - © 2009 DDC

Weighted quantities

• Sum of elementary units with the weights corresponding to power of 2 (1, 2, 4, 8, …)

• Each unit is controlled by the corresponding bit value (1/0 )

– Output = Σ 2i * Di

– Example: 13D = 1101B

– Weight 23 22 21 20

– Value 1 1 0 1

– 13D = 8*1 + 4*1 + 2*0 + 1*1

• This is called weighted elements conversion

TLCE - C2 14/10/2009

© 2009 DDC 27

14/10/2009 - 27 TLCE - C2 - © 2009 DDC

Uniform currents D/A converter

The output current Io is the sum of a variable number of identical elementary currents Ie, controlled by DN bits � M = 2N identical branches

Ie

Io

TLCE - C2 14/10/2009

© 2009 DDC 28

14/10/2009 - 28 TLCE - C2 - © 2009 DDC

Uniform voltages D/A converters

The output is a voltage Vo obtained summingelementary voltage drops on the resistor chain. Since allresistors have the samevalue, all voltage drops are the same.

The tap is selected by the digital value D

This is also called

potentiometric DAC

TLCE - C2 14/10/2009

© 2009 DDC 29

14/10/2009 - 29 TLCE - C2 - © 2009 DDC

Weighted elements converters

• Weighted elements (usually currents) are obtained from a reference (usually a voltage Vr) through a weight network, and are fed or blocked towards the adder by a bank of switches controlled by bits Ci of the digital input data D

WEIGHT

NETWORKΣΣΣΣ

Vr DIGITAL INPUT (D)

ANALOG OUTPUT (A)1

24

2N-1

1 C0

2 C1

4 C2

2N-1 CN-1

TLCE - C2 14/10/2009

© 2009 DDC 30

14/10/2009 - 30 TLCE - C2 - © 2009 DDC

Weighted currents D/A converters

2R

R

2N-1R

4R

The output current Io is the sum of a variable number of weighted elementary currents Ii (weight ratio 2), directly controlled by DN bits � N = weighted branches

Ii

Io

TLCE - C2 14/10/2009

© 2009 DDC 31

14/10/2009 - 31 TLCE - C2 - © 2009 DDC

Weighted resistor D/A converter

• Same circuit, with switches steering currents towards nodes at the same potential (GND)

– current switches

– high dynamic range for resistors (2N-1)

TLCE - C2 14/10/2009

© 2009 DDC 32

14/10/2009 - 32 TLCE - C2 - © 2009 DDC

Voltage and current switches

• Linear passive networks: reciprocity

– If input and output are exchanged, same I(V) relation

• I1 = D(V1) I2 = D(V2)

TLCE - C2 14/10/2009

© 2009 DDC 33

14/10/2009 - 33 TLCE - C2 - © 2009 DDC

Weighted elements - voltage switches

• Same network, exchange of Vr and Iu

– switches operate between nodes at different potential (Vr, GND)

– voltage switches

– again, high dynamic range for resistors (2N-1)

TLCE - C2 14/10/2009

© 2009 DDC 34

14/10/2009 - 34 TLCE - C2 - © 2009 DDC

Voltage/current switch comparison

Current switches(both nodes 0 V)

Voltage switches(nodes at Vr / 0 V)

TLCE - C2 14/10/2009

© 2009 DDC 35

14/10/2009 - 35 TLCE - C2 - © 2009 DDC

VR

R

2R R

I = VR/2R

I

I I

2I

Ladder network - 1

• Splitting a current in two equal parts

TLCE - C2 14/10/2009

© 2009 DDC 36

14/10/2009 - 36 TLCE - C2 - © 2009 DDC

VR

R

2R 2R R

R

I = VR/2R

I

I I/2

I/2

I/2

2I

Ladder network - 2

• Repeat the splitting

TLCE - C2 14/10/2009

© 2009 DDC 37

14/10/2009 - 37 TLCE - C2 - © 2009 DDC

VR

R

2R 2R 2R 2R

R R R

R

I = VR/2R Ii = I/2i

I

I I/2

I/2

I/4

I/8I/4

I/8

2I

Ladder network - 3

• Continue splitting (4 currents)

I1 I2 I3I0

TLCE - C2 14/10/2009

© 2009 DDC 38

14/10/2009 - 38 TLCE - C2 - © 2009 DDC

Benefits of ladder networks

• The ladder network is fully modular– Any number of bits

• Uses only R and 2R resistors– Same technology, same behavior (temp, aging, …)– Precise current ratio

• D/A converter with ladder network:– branch currents can be sent to ground/output summing node

with current switches

– V-output with Norton/Thevenin conversion

– Reciprocal network with V-switches feasible

TLCE - C2 14/10/2009

© 2009 DDC 39

14/10/2009 - 39 TLCE - C2 - © 2009 DDC

Ladder network with I-out and I-SW

0 ← → 1

I-Switches steer the currentbetween equipotential nodes

R

VR

R

2R 2R 2R 2R

R R RI

I I/2 I/4 I/8

2I

IO

MSB

TLCE - C2 14/10/2009

© 2009 DDC 40

14/10/2009 - 40 TLCE - C2 - © 2009 DDC

Ladder network with V-out and V-SW

R R R R

0 ← → 1

V-Switch connect a node to VR/0Voltage output

VR

2R 2R 2R 2R R

I

I I/2 I/4 I/8IOUT

MSB

TLCE - C2 14/10/2009

© 2009 DDC 41

14/10/2009 - 41 TLCE - C2 - © 2009 DDC

Ladder network - conversion example

VR

R

2R 2R 2R 2R

R R R

R

I

I I/2 I/4 I/8

2I

ITOT

MSB

00 11

ITOT = I/2 + I/8

TLCE - C2 14/10/2009

© 2009 DDC 42

14/10/2009 - 42 TLCE - C2 - © 2009 DDC

Current and voltage outputs

• Constant equivalent output resistance– The Thevenin and Norton equivalent generators have the

same relation with digital input D

Io = K D Vo = K R D

• A circuit with current output (Icc) and constant Ru can be turned into a voltage-output circuit.

TLCE - C2 14/10/2009

© 2009 DDC 43

14/10/2009 - 43 TLCE - C2 - © 2009 DDC

Ladder network with voltage output

R R R R

Switches operate between GND and VRVR

2R 2R 2R 2R R

I

I I/2 I/4 I/8VOUT

MSB

TLCE - C2 14/10/2009

© 2009 DDC 44

14/10/2009 - 44 TLCE - C2 - © 2009 DDC

Capacitive weight networks

• Use as weighted elements charge instead of current

• The weight network uses capacitorsinstead of resistors

• Precision depends on capacitance ratio

• Better suited for MOS technology

• Reduced power consumption

TLCE - C2 14/10/2009

© 2009 DDC 45

14/10/2009 - 45 TLCE - C2 - © 2009 DDC

Sources of linear errors

• Gain error– Changes in Vr

– Systematic error in the weight network

• Offset error– Leakage current of switches– Offset of Op Amp

• These errors do not depend on the value D

– A unique correction value work for all dynamic range– Can be corrected in the digital domain

TLCE - C2 14/10/2009

© 2009 DDC 46

14/10/2009 - 46 TLCE - C2 - © 2009 DDC

Branch errors

• Equivalent resistance of switches (Ron)– Modifies the total branch resistance

– Sane effects as weight resistor error (tolerance)

– Modifies the branch current– If constant --> gain error

• Leakage current of switches (Ioff)– Some out even for D = 0– If constant: offset error

TLCE - C2 14/10/2009

© 2009 DDC 47

14/10/2009 - 47 TLCE - C2 - © 2009 DDC

Errors in weighted D/A networks

• Each branch contributes to output when corresponding bit is 1

– MSB contributes over S/2, MSB-1 over S k/4, ...

• Branches have different weight– MSB weight is 1/2, MSB-1 weight is 1/4, ….

• Out_error = branch_error x branch_weight– the same % error in different branches causes different error

at the output– higher effects on MSBs

• MSBs branches must be more precise

• Affected parameter: differential nonlinearity.

TLCE - C2 14/10/2009

© 2009 DDC 48

14/10/2009 - 48 TLCE - C2 - © 2009 DDC

Errors in weighted D/A - example

• Error on MSB branch– actual contribution higher than ideal

– raised upper half of characteristic – branch error 10%: --> output error 5%

• Error on MSB - 1 branch– actual contribution lower than ideal

– lowered odd quarters (1, 3) of characteristic – branch error 10%: --> output error 2.5%

• Error on MSB - 2 branch– branch error 10%: --> output error 1.25%

– ...

TLCE - C2 14/10/2009

© 2009 DDC 49

14/10/2009 - 49 TLCE - C2 - © 2009 DDC

Errors in weight network: MSB, MSB-1

D

A

S

S/2

11..1011.. 100..00..0

0

εnla

error on MSB (+)

D

A

S

S/2

11..100..0

0

εnla

error on MSB – 1 (-)

εnlaεnla

TLCE - C2 14/10/2009

© 2009 DDC 50

14/10/2009 - 50 TLCE - C2 - © 2009 DDC

Errors in uniform D/A networks

• Out_error = branch_error x branch_weight– each branch has the same weight (1 LSB)

– the same % error in any branch causes the same output error

– intrinsically monotonic output» sum of elements with the same sign

• All branches can have same precision

• Errors of all branches sum at the output

• Critical parameter: integral nonlinearity

TLCE - C2 14/10/2009

© 2009 DDC 51

14/10/2009 - 51 TLCE - C2 - © 2009 DDC

Uniform elements D/A: example

• Potentiometric converter with systematic error in the resistor chain

– +∆R in the upper half, - ∆R in the lower half– high integral nonlinearity

D

A

S

S/2

11..110..000..0

0

The voltage divider isunbalanced; the midnode is at a voltagelower than S/2.

Intermediate nodeshave proportionalerrors.

TLCE - C2 14/10/2009

© 2009 DDC 52

14/10/2009 - 52 TLCE - C2 - © 2009 DDC

Error summary

• Gain error– changes of reference voltage Vr

– systematic errors in the weight network

• Offset error – Op Amp offsets

– Leakage current of switches

• Nonlinear errors– random errors in the weight network (NLD)– systematic error in the uniform network (NLI)

TLCE - C2 14/10/2009

© 2009 DDC 53

14/10/2009 - 53 TLCE - C2 - © 2009 DDC

Mixed D/A converters

• Weighted networks – simple (Order N)

– need high precision on MSBs branches

• Uniform networks – intrinsically monotone

– complex (Order 2N)

• Mixed structures:– use uniform branches for MSBs– use weighted branches for LSBs– benefits of both structures: simple, no need for high precision

• Split weighted � uniform decoding– Keep benefits of uniform networks, with reduced complexity

TLCE - C2 14/10/2009

© 2009 DDC 54

14/10/2009 - 54 TLCE - C2 - © 2009 DDC

Example of mixed D/A converter

• 2 MSBs: linear DAC– 3 resistors + 3 SW

• 4 LSBs: weighted DAC– Weighted R or ladder network

16R

Uniform elements(2 MSBs)

Weighted elements(4 LSBs)

TLCE - C2 14/10/2009

© 2009 DDC 55

14/10/2009 - 55 TLCE - C2 - © 2009 DDC

Example: mixed DAC 5linear + 5coded

TLCE - C2 14/10/2009

© 2009 DDC 56

14/10/2009 - 56 TLCE - C2 - © 2009 DDC

Example of split 5 + 4 + 1 DAC

16R

TLCE - C2 14/10/2009

© 2009 DDC 57

14/10/2009 - 57 TLCE - C2 - © 2009 DDC

Indirect D/A converters

• Use an intermediate quantity (e.g. time) – From numeric value D to a time T1 (pulse width)

– Signal average is proportional to D

TLCE - C2 14/10/2009

© 2009 DDC 58

14/10/2009 - 58 TLCE - C2 - © 2009 DDC

Bipolar D/A converters - 1

• Sign inversion of reference voltage VR

Possible jump in (0 ,0)

TLCE - C2 14/10/2009

© 2009 DDC 59

14/10/2009 - 59 TLCE - C2 - © 2009 DDC

Bipolar D/A converters – 2

• Translation of a unipolar characteristic

No jump in (0,0)

TLCE - C2 14/10/2009

© 2009 DDC 60

14/10/2009 - 60 TLCE - C2 - © 2009 DDC

Multiplying D/A converters

• Multiplying DAC allow for VR variations:– Io = K D VR

• Applications:– Variable gain amplifiers (VGA)

– Bipolar DAC (with VR inversion)– Ratiometric ADC (next lesson)

TLCE - C2 14/10/2009

© 2009 DDC 61

14/10/2009 - 61 TLCE - C2 - © 2009 DDC

Gain control with a DAC

• The DAC id used as feedback (or input) transconductance.

• The D/A must allow VR sign inversion: Io = K D VR

TLCE - C2 14/10/2009

© 2009 DDC 62

14/10/2009 - 62 TLCE - C2 - © 2009 DDC

D/A for telecom applications

• Direct (in-band) signal generation

• Significant parameters:

– linearity

– full power bandwidth

– Spurious Free Dynamic Range (SFDR)

TLCE - C2 14/10/2009

© 2009 DDC 63

14/10/2009 - 63 TLCE - C2 - © 2009 DDC

Lesson C2 – final test

• How can we correct offset and gain errors of a DAC?

• Can we correct nonlinearity errors?

• Define non-monotonicity error.

• Which circuits can be used to reduce glitches?

• Which is the main problem of weighted resistors DAC circuits?

• Which are the benefits of ladder networks?

• Explain the difference between voltage and current switches.

• Can we build a voltage-output DAC using a ladder network with current switches?

• Draw the block diagram of a 4+4 mixed DAC.