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High Performance Non-PlanarTri-gate Transistor Architecture

Dr. Gerald MarcykDirector Components ResearchLogic Technology Development

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What Are We Announcing?

• Invention of a novel tri-gate fully depleted transistor with industry leading performance

− Research targeted for 2nd half of the decade

• A three dimensional extension of the TeraHertz architecture

− Highest reported drive current for non-planar devices − Depleted substrate improves Ioff leakage

• Improved manufacturability over proposed double gate structures

− Uses 300mm equipment and existing lithography capabilities

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Why is this Important?• Transistor research breakthroughs will allow us to

continue Moore’s Law through end of decade

• IC Industry is making transition from Planar to Non-Planar Transistors

• This development has potential to enable products with higher performance that use less power

• Intel transistors lead industry performance in both research and manufacturing

• Intel’s $4B investment in R&D continues on track: delivering a new process technology every 2 years

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Moore’s LawA new technology every 2 years

Process NameProcess Name P856P856 P858P858 Px60Px60 P1262P1262 P1264P1264 P1266P1266 P1268P1268

11stst ProductionProduction 19971997 19991999 20012001 20032003 20052005 20072007 20092009

LithographyLithography .25.25µµm m .18.18µµmm .13.13µµmm 90nm90nm 65nm65nm 45nm45nm 32nm32nm

Gate LengthGate Length .20.20µµm m .13.13µµm m <70nm <70nm <50nm<50nm <35nm <35nm <25nm<25nm <18nm<18nm

Wafer Size (mm)Wafer Size (mm) 200200 200 200/300200 200/300 300300 300300 300300 300300

Manufacturing

Development

ResearchCopy Exactly!

Pathfinding

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Accelerated Scaling of Planar Transistors

70nm Length(Production2001)

30nm Prototype (Production in 2005)

20nm Prototype(Production in 2007)

25 nm

15nm

15nm Prototype15nm Prototype(Production in 2009)(Production in 2009)

50nm Length(Production in 2003)

130nm Node

65nm Node

45nm Node

90nm Node

32nm Node

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Silicon devices are Nanotechnology

50nm50nm 100nm100nm

Transistor for Transistor for 90nm process90nm process

Source: IntelSource: Intel

Influenza virusInfluenza virusSource: CDCSource: CDC

25 nm

15nm15nm Research15nm ResearchTransistorTransistor

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Transistor Gate Length Scaling

0.01

0.1

1

10

1970 1980 1990 2000 2010 2020

Micron

0.01

0.1

1

10

3.0um

.18um.25um

.35um.5um

.8um1.0um

1.5um2.0um

.13um90nm

50nm

Gate Length

Typical Feature

Size

Transistor Gate Length is Smallest Feature on the Device

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1.E-14

1.E-12

1.E-10

1.E-08

1.E-06

1.E-04

10 100 1000Transistor Physical Lg (nm)

Ioff

(A/u

m)

Production data

Research data in literature

Intel’s 15nmtransistor(2001)

Intel’s 30nmtransistor ( 2000)

( )

( )

Planar Transistor Problem:Smaller Devices have Higher Leakage

We need novel device structures to meet this challenge

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Intel’s TeraHertz Transistor:Lower Ioff Leakage

Raised Raised Source/Source/DrainDrain

< 30nm Silicon< 30nm Silicon OxideOxide

GateGate HighHigh--k k GateGate

DielectricDielectric

Fully Depleted Substrate: Subthreshold Leakage is Approaching Theoretical Minimum

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A Switch to Non-Planar CMOS Transistors

• Planar TeraHertz Transistor Improves Leakage− Control of Nano-thick Silicon Layer becomes the

Manufacturing Issue

• Three Dimensional Devices ( Non-Planar) have been Proposed by Researchers− Dual Gate, FinFET, etc.− Complex Fabrication processes− Measured Device Performance has been

Disappointing

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New Tri-Gate Transistor Structure

Gate Oxide

Oxide Substrate

SourceDrain

Gate

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Buried Oxide

Gat

e 2 G

ate 3

Gate 1Gate

Silicon Substrate

SiO2SiO2

Tri-Gate Planar CMOS

Tri-gate Transistor works inThree Dimensions

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0 20 40 60 80Device Gate Length, Lg (nm)

Silic

on B

ody

Thic

knes

s (n

m)

Single-Gate

Double-

Tri-Gate

0 20 40 60 80

Single- Gate

Tri-Gate

0 20 40 60 80

-

01020304050

0 20 40 60 80

Double-Gate-60

(

Tri-Gate’s Geometry Advantage

Tri-gate is Fully Depleted Without Unusual Lithography Patterning orSOI Thickness Control Issues.

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Multi-Channel Tri-gate Devices:Even More Drive Current

SourcesDrains

Gate

Gate Multiple Drains

Multiple Sources

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Conclusions

• High-Performance Tri-Gate Fully-Depleted CMOS with 60nm physical gate length has been Demonstrated

• Tri-gate Fully-Depleted CMOS exhibits lower leakage than standard planar CMOS

− Similar to Planar TeraHertz Transistor

• Unique Tri-Gate Geometry is more Manufacturablethan Fully-Depleted Planar and Double Gate structures.

• Tri-gate with Spacer-Defined Fins has Potential to deliver 20% Higher Total Current per unit Layout Area than Standard CMOS

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Additional details of this Tri-gate transistor technology will be presented at the International Solid

State Device and Materials Conference in Nagoya Japan on Sept 17, 2002

For further information on Intel's silicon technology, please visit the Silicon Showcase at

www.intel.com/research/silicon

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BACK – UP MATERIAL

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New Tri-gate Transistor Structure

WSiLg

HSi

Gate OxideCurrent

Improved ManufacturabilityWidth = Height = Gate Length

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Double Gate FinFET Transistor

WSi

Lg

HSi

Gate OxidesCurrent

Major Problem: Fin Width must be Narrower than Gate LengthLithography becomes the Key Limiter

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New materials Extend Performance of 90nm Planar Transistors

GateGateSilicideSilicideaddedadded

ChannelChannelStrainedStrainedsiliconsilicon

ChangesChangesmademade

FutureFutureoptionsoptions

HighHigh--kkgategate

dielectricdielectric

TransistorTransistor

NewNewtransistortransistorstructurestructure

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90 nm Generation Transistor

50nm

Silicide Layer

Silicon Gate Electrode

1.2 nm SiO2Gate Oxide

Strained Silicon

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Strained Silicon Transistors

Normal Silicon Lattice Strained Silicon Lattice

Current Flow

Normal electron

flow

Faster electron

flow