The digital system The digital system design and Verilogdesign and Verilog

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► IntroductionIntroduction►Description styleDescription style►ModelingModeling►Example and simulationExample and simulation►ConclusionConclusion

Advance in VerilogAdvance in Verilog

►Easy to design directly for complex Easy to design directly for complex systemssystems

►Model description by VerilogModel description by Verilog Easy to modifyEasy to modify Enable automatic synthesisEnable automatic synthesis

►Allow architectural tradeoffs with short Allow architectural tradeoffs with short turnaroundturnaround

►Reduce time to design captureReduce time to design capture►Short the design verification loopShort the design verification loop

The characteristic of VerilogThe characteristic of Verilog

► Have high-level language constructs to Have high-level language constructs to describe the functionality and connectivity of describe the functionality and connectivity of the circuitthe circuit

► Can describe a design at some level of Can describe a design at some level of abstraction: behavioral, RTL, Gate-level, abstraction: behavioral, RTL, Gate-level, SwitchSwitch

► Can describe functionality as well as timingCan describe functionality as well as timing► Can be used to document the complete Can be used to document the complete

system design tasks: testing, simulationsystem design tasks: testing, simulation► Comprehensive and easy to learnComprehensive and easy to learn

The convenient of VerilogThe convenient of Verilog

► Hardware description languageHardware description language► Mixed level modelingMixed level modeling

BehavioralBehavioral► AlgorithmicAlgorithmic► Register transferRegister transfer

StructuralStructural► GateGate► SwitchSwitch

► Single language for design and simulationSingle language for design and simulation► Built-in primitives and logic functionsBuilt-in primitives and logic functions► User-defined primitivesUser-defined primitives► Built-in data typesBuilt-in data types► High-level programming constructsHigh-level programming constructs

Concept Design

HDL Simulation

Concept O.K.?

Synthesis & Test

Gate-level simulation

ImplementationO.K?

Traditional VLSI Design FlowTraditional VLSI Design Flow

System Specification

Functional/Architecture

Design

LogicSynthesis

CircuitDesign

Functionalsimulation

Logicsimulation

Circuit analysis

Behaviorrepresentation

HDLdescription

gate-levelrepresentation

Switch-levelrepresentation

Hierarchy description styleHierarchy description style

► Direct instantiation and connection of Direct instantiation and connection of models from a separate calling modelmodels from a separate calling model Form the structural hierarchy of a designForm the structural hierarchy of a design

► A model may be declared anywhere in a A model may be declared anywhere in a design relative to where it is calleddesign relative to where it is called

► Signals in the higher “calling” model are Signals in the higher “calling” model are connected to signals in the lower “called” connected to signals in the lower “called” model by either:model by either: Named associationNamed association Positional associationPositional association

Lexical conventionsLexical conventions

► Verilog is a free-format language – like CVerilog is a free-format language – like C► White space (blank, tab, newline) can be used White space (blank, tab, newline) can be used

freelyfreely► Verilog is a Verilog is a case-sensitivecase-sensitive language language► IdentifiersIdentifiers

User-provided names for Verilog objects in the descriptionsUser-provided names for Verilog objects in the descriptions Legal characters are “a-z”, “A-Z”, “0-9”, “Legal characters are “a-z”, “A-Z”, “0-9”, “__” and “$”” and “$”

► First character has to be a letter or an “_”First character has to be a letter or an “_” Example: Count,Example: Count, _ _R2D2, five$R2D2, five$

► KeywordsKeywords Predefined identifiers to define the language constructsPredefined identifiers to define the language constructs All keywords are used as identifiersAll keywords are used as identifiers Cannot be used as identifiersCannot be used as identifiers Example: Example: initial, assign, moduleinitial, assign, module

Lexical conventionsLexical conventions

► Comments: two formsComments: two forms/*First form: can/*First form: can

extend over manyextend over manyline*/line*/

//second form: ends at the end of this line//second form: ends at the end of this line► StringsStrings

Enclosed in double quotes and must be specified in one Enclosed in double quotes and must be specified in one lineline

► ““sequence of characters”sequence of characters” Accept C-liked escape characterAccept C-liked escape character

► \n = newline\n = newline► \t = tab\t = tab► \\ = backslash\\ = backslash► \” = quote mark (“)\” = quote mark (“)► %% = % sign%% = % sign

Register typesRegister types

► Reg: any size, unsignedReg: any size, unsigned► Integer: 32-bit signed (2’s complement)Integer: 32-bit signed (2’s complement)► Time: 64-bit unsignedTime: 64-bit unsigned► Real, realtime: 64-bit real numberReal, realtime: 64-bit real number

Defaults to an initial value of 0Defaults to an initial value of 0► Example:Example:

reg CNT;reg CNT;reg [31:0] SAT;reg [31:0] SAT;integer A,B,C; //32-bitinteger A,B,C; //32-bitreal SWING;real SWING;realtime CURR_TIME;realtime CURR_TIME;time EVENT;time EVENT;

parameters typesparameters types

► Is a ConstantIs a Constant► Example:Example:

parameter LINE_LENGTH = 132,ZLL_X_S = parameter LINE_LENGTH = 132,ZLL_X_S = 16’b016’b0

parameter BIT = 1, BYTE = 8, PI = 3.14;parameter BIT = 1, BYTE = 8, PI = 3.14;

parameter SROBE_DELAY = (BYTE+BIT)/2parameter SROBE_DELAY = (BYTE+BIT)/2parameter TQ_FILE = “/home/fds/test/add.tq”;parameter TQ_FILE = “/home/fds/test/add.tq”;

► Common usageCommon usage Specify delays and widthsSpecify delays and widths

Gates modelGates model► The following gates are built-in types in the simulatorThe following gates are built-in types in the simulator► And, nand, nor, or, xor, xnorAnd, nand, nor, or, xor, xnor

First terminal is output, followed by inputsFirst terminal is output, followed by inputsand a1 (out1, in1, in2);and a1 (out1, in1, in2);nand a2 (out2, in21, in22, in23, in24);nand a2 (out2, in21, in22, in23, in24);

► buf, notbuf, not One or more outputs first, followed by one input One or more outputs first, followed by one input

not N1 (OUT1, INA, CTRLA);not N1 (OUT1, INA, CTRLA);buf B1 (BO1, BIN);buf B1 (BO1, BIN);

► bufif0, bufif1, notif0, notif1: three-state driversbufif0, bufif1, notif0, notif1: three-state drivers Output terminal first, then input, then controlOutput terminal first, then input, then control

bufif1 BF1 (OUTA, INA, CTRLA);bufif1 BF1 (OUTA, INA, CTRLA);► Pullup, pulldownPullup, pulldown

Put 1 or 0 on all terminalsPut 1 or 0 on all terminalspullup PUP(PWRA, PWRB, PWRC);pullup PUP(PWRA, PWRB, PWRC);

► Instance names are optionalInstance names are optionalex: not (QBAR, Q)ex: not (QBAR, Q)

Data-flow modelData-flow model► Models behavior of combinational logicModels behavior of combinational logic► Example:Example:

wire [3:0] Z, PRESET, CLEAR;wire [3:0] Z, PRESET, CLEAR;assign Z = PRESET & CLEAR;assign Z = PRESET & CLEAR;

wire COUNT, CINwire COUNT, CINwire [3:0] SUM,A,B;wire [3:0] SUM,A,B;assign {COUT, SUM} = A+B+CINassign {COUT, SUM} = A+B+CIN

► Left-hand side (target) expression can be a:Left-hand side (target) expression can be a: Single net (ex: Z)Single net (ex: Z) Part-select (ex:SUM[2:0])Part-select (ex:SUM[2:0]) Bit-select (ex: Z[1])Bit-select (ex: Z[1]) Concatenation of both (ex: {COUT, SUM[3:0]})Concatenation of both (ex: {COUT, SUM[3:0]})

► Expression on right-hand side is evaluated whenever any Expression on right-hand side is evaluated whenever any operand value changesoperand value changes

Behavioral modelBehavioral model

► Procedural blocks:Procedural blocks: Initial block: executes only onceInitial block: executes only once Always block: executes in a loopAlways block: executes in a loop

► Block execution is triggered based on user-specified Block execution is triggered based on user-specified conditionsconditions Always @ (posedge clk)…Always @ (posedge clk)…

► All procedural blocks are automatically activated at All procedural blocks are automatically activated at time 0time 0

► All procedural blocks are executed concurrentlyAll procedural blocks are executed concurrently► Reg. is the main data type that is manipulated Reg. is the main data type that is manipulated

within a procedural blockwithin a procedural block It holds its value until assigned a new valueIt holds its value until assigned a new value

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► IntroductionIntroduction►Description styleDescription style►ModelingModeling►Example and simulationExample and simulation►ConclusionConclusion

B A R

BAR (50): 1024

20

Apple (40): 1024

24

A slot machine (拉霸 )

Watermelon (30): 1024

35

Banana (25): 1024

40

Lemon (20): 1024

50

Orange (15): 1024

65

Guava (10): 1024

100

Cherry (5): 1024

190

Strawberry (2): 1024

500

• Nine different type of patterns• Win if three patterns are the same• Different probability and indemnity between patterns

Game control

Coin : Money will you gambleStart : Start the gameReturn : Money you winSum : Money in the machine

temp=outData[7] ^ outData[9]; outData={outData[8:0],temp};

Random number generator

temp=outData[5] ^ outData[8]; outData={outData[8:0],temp};

temp=outData[3] ^ outData[6]; outData={outData[8:0],temp};

parameter[3:0] BAR=4'b0001, apple=4'b0010, watermelon=4'b0011, banana=4'b0100, lemon=4'b0101, orange=4'b0110, guava=4'b0111, cherry=4'b1000, strawberry=4'b1001;

if(inData<=20) outPattern=BAR;else if(inData<=44) outPattern=apple;else if(inData<=79) outPattern=watermelon;else if(inData<=119) outPattern=banana;else if(inData<=169) outPattern=lemon;else if(inData<=234) outPattern=orange;else if(inData<=334) outPattern=guava;else if(inData<=524) outPattern=cherry;else if(inData<=1024) outPattern=strawberry;

• Define the pattern into binary code

• Define the output pattern

4'b0001: return={1'b0,coin[6:0],5'b00000} //return=coin multiply 50 +{2'b00,coin[6:0],4'b0000} +{5'b00000,coin[6:0],1'b0}; 4'b0010:return={1'b0,coin[6:0],5'b00000} //return=coin multiply 40 +{3'b000,coin[6:0],3'b000} +{5'b00000,coin[6:0],1'b0}; 4'b0011:return={1'b0,coin[6:0],5'b00000} //return=coin multiply 30 -{5'b00000,coin[6:0],1'b0}; 4'b0100:return={2'b00,coin[6:0],4'b0000} //return=coin multiply 25 +{3'b000,coin[6:0],3'b000} +{6'b000000,coin[6:0]}; 4'b0101:return={2'b00,coin[6:0],4'b0000} //return=coin multiply 20 +{4'b0000,coin[6:0],2'b00}; 4'b0110:return={2'b00,coin[6:0],4'b0000} //return=coin multiply 15 -{6'b000000,coin[6:0]}; 4'b0111:return={3'b000,coin[6:0],3'b000} //return=coin multiply 10 +{5'b00000,coin[6:0],1'b0}; 4'b1000:return={4'b0000,coin[6:0],2'b00} //return=coin multiply 5 +{6'b000000,coin[6:0]}; 4'b1001:return={5'b00000,coin[6:0],1'b0}; //return=coin multiply 2

Use shift register to replace the multiplier

A*50=A*32+A*16+A*2

Vending machine• Seven kind of thing in vending machine• Four type of coin can use : 1, 5, 10, 50• Only can buy one goods at the same time

Vendor control

Coin : Money you put in Button : What to buyAmount : Money you haveRefund : Money to refund

while(coin>=50) begin coin=coin-50; out50=out50+1; end while(coin>=10) begin coin=coin-10; out10=out10+1; end while(coin>=5) begin coin=coin-5; out5=out5+1; end while(coin>=1) begin coin=coin-1; out1=out1+1; end amount=0; end

Refund the money

counter1=counter1+in1;counter5=counter5+in5;counter10=counter10+in10;counter50=counter50+in50;amount=amount+in1+in5*5+in10*10+in50*50;

Put in coin

ConclusionConclusion

►Easy to design directly for complex Easy to design directly for complex systemssystems

►Comprehensive and easy to learnComprehensive and easy to learn►Allow architectural tradeoffs with short Allow architectural tradeoffs with short

turnaroundturnaround

Thank you