the enabling interconnect technology for cost … enabling interconnect technology for cost...
TRANSCRIPT
The Enabling Interconnect
Technology for Cost Effective
2.nD Package
Charlie Lu, John Y. Xie
Packaging Technology R&D, Altera Corp.
2015. Sep. 03 Rev. 1
Outline
Starting from the origin
Application, architecture, chip-to-package
interconnect
2.nD 2.5D 2.5D-
2.1D ViB FCrdlBGA
Summary
Purpose of Packaging From simple to complex
1950 1960 1970 1980 1990 2000 2010 2020
Applications of Packaging Technology From simple to diversified
Low-end application
High-end application
1950 1960 1970 1980 1990 2000 2010 2020
Data center
Picture source: Internet
1950 1960 1970 1980 1990 2000 2010
Applications of Packaging Technology From simple to diversified
High-end application
Mid-range application
Low-end application
1950 1960 1970 1980 1990 2000 2010
Conventional Chip-to-Package Interconnect
Technology
Wire Bonding (WB)
Tape Automatic Bonding (TAB)
Flip ChipBonding (TAB)
Mixed technologies
Applications vs. Package Architecture Cost, performance, integration
SSF & cost driven
Performance driven
Heterogeneous integration
Cost-effective
Heterogeneous integration
3D
2D
2.nD
Conceptual Definition of 2.nD
Defined mainly by cost, performance, and
integration density
3D 2D Conventional 2D
WLP
3D-IC
2.nD
3D-IC
3D 2D 3D-IC
Advantage Electrical performance
Heterogeneous integration
Higher wafer yield
Challenge Design / EDA
Test-ability
Thermal
KGD
2.nD
Micron
HBM as one camp of 2.5D/3D
memory Features 8 channel, 2channel/die and
128-Bit/channel
Total 1024Gb/s memory BW
DDR like memory interface Double data rate architecture with burst 2
and burst 4 support
JTAG, MBIST, IEEE 1500 ports for direct access and connectivity tests
HBM Features DRAM 2, 4, 8 stacks on interposer
Base die interface with controller die through silicon interposer
Interconnect at 55um BP
13
3D-IC to 2.5D-IC
3D 2D
2.5D Si interposer w/TSV
Glass interposer w/TGV
3D-IC
Advantage Electrical performance
Higher wafer yield
Heterogeneous integration
What is its chip-to-package interconnect? …….. TSV + FCB
2.5D FCBGA
Si 1 Si 2
Substrate
Si interposer
3D 2D
2.5D Si interposer w/TSV
Glass interposer w/TGV
3D-IC 2.5D- Embedded TxV-less interposer
2.5D to 2.5D-
Substrate
Si 2 Si 1
2.5D FCBGA 2.5D- FCBGA
Si 1 Si 2
Substrate
Si interposer
EMIB:
Embedded Multi-die Interconnect Bridge
Announced during 9/11/2014 Intel IDF
INTEL IDF14
EMIB
Package Cross Sections
3D 2D
2.5D Si interposer w/TSV
Glass interposer w/TGV
2.5-D Embedded TxV-less interposer
2.1D Thin film on
organic substrate
3D-IC
2.5D- to 2.1D
Ref.: Shinko, iMAPS 2013
2.1D Thin film on
organic substrate
“Fan-out” packages
WLFO / PLFO
3D 2D
2.5D Si interposer w/TSV
Glass interposer w/TGV
2.5-D Embedded TxV-less interposer
3D-IC
Colorful “Fan-out” Package
All the packages are fan-out packages (except WLP),
“fan-out” has been abused
Dry process
(Wafer Fab-like)
Wet process
(PCB-like)
Dry process
(Wafer Fab-like)
“Wafer-level FO” / “Panel-level FO” packages is confusing
3D 2D
2.5D Si interposer w/TSV
Glass interposer w/TGV
2.5-D Embedded TxV-less interposer
3D-IC
Colorful “Fan-out” Package
eWLB
Infineon eWLB
f) Re-distribution
g) Ball apply +
Singulation
Metal plate Carrier tape
Die placement
Compression molding
Metal plate separation
Laminate carrier tape on metal plate
Carrier tape peel-off
Re-configured “wafer”
Ref.: M. Brunnbauer, ECTC 2006
eWLB = embedded Wafer Level Ball-grid-array
Die-first process
Infineon eWLB
Re-configured “wafer”
Ref.: M. Brunnbauer, ECTC 2006
Die-first process What is its chip-to-package
interconnect?
Wire-bonding
Flip-chip-bonding
Tape-automatic-bonding
Via-interconnect
Via-interconnect BGA (ViB)
Multi-chip ViB by Wafer Fab-like Process
Die-first process
3D 2D
2.5D Si interposer w/TSV
Glass interposer w/TGV
2.5-D Embedded TxV-less interposer
3D-IC
ViB Package:
From Dry Process to Wet Process
PCB-like
process
ViB Wafer Fab-like
Die-first
Panel 1st layer circuit
carrier
Die attachment
Lamination
Remove carrier
&
Build-up substrate
process
Laser via + SAP + SM
Ball mount /
Singulation
ViB Package by PCB-like Process
Die-middle process
3D 2D
2.5D Si interposer w/TSV
Glass interposer w/TGV
2.5-D Embedded TxV-less interposer
3D-IC
ViB Package: Various Combinations
ViB PCB-like
Die-first
Die-middle
ViB Wafer Fab-like
Die-first
2~3um line/space
2~3 layers RDLs
5~10um line/space
2~3 layers RDLs
Higher assembly yield?
Higher routing density?
Die-last and Higher Routing Density
RDL
Die Die
FCB/Encapsulation De-carrier/Ball mount/
Singulation
Substrate Ball mount/
Singulation
Package Named by Substrate Material
Laminate (organic) FCPBGA
Ceramic FCCBGA
Tape FCTBGA
Die-last
How to Name The New Package
RDL
Die
FCB/Encapsulation De-carrier/Ball mount/
Singulation
Die
RDL FCrdlBGA
Die-last
FCrdlBGA: SLIMTM from Amkor Technology
SLIM: Silicon-Less Integrated Module
Source.: Amkor, customer presentation 2015
FCrdlBGA: SWIFTTM from Amkor Technology
SWIF: Silicon Wafer Integrated Fan-out Technology
Source.: Amkor, customer presentation 2015
Chip-to-Package Interconnect of FCrdlBGA
Source.: Amkor, customer presentation 2015
What is its chip-to-package interconnect? …….. FCB
3D 2D
2.5D Si interposer w/TSV
Glass interposer w/TGV
2.5-D Embedded TxV-less interposer
3D-IC
ViB Package to FCrdlBGA
ViB Wafer Fab-like/PCB-like
Die-first/Die-middle
2~10um line/space
2~3 layers RDLs
FCrdlBGA Wafer Fab-like
Die-last
2~3um line/space
3~4 layers RDLs
3D 2D
2.5D Si interposer w/TSV
Glass interposer w/TGV
2.5-D Embedded TxV-less interposer
3D-IC
Extension of ViB and FCrdlBGA
ViB FCrdlBGA
37
FC Substrate
2.nD SiP Platform
Format
Process tech.
(Routing Density)
Chip-to-PKG
interconnect
Si placement
sequence
Wafer shape Panel shape
PCB-like OSAT RDL Damascene
Die first/Die middle
Via-interconnect
Die last
FCB/TSV+FCB
FC Substrate Non
Yes
Package Extended
ViB/FCrdlBGA 2.1D/2.5D
Hybrid
Hundred of 2.nD
Configuration and Process
Combinations
ViB/FCrdlBGA
Summary
Enabling Tech. for 2.nD
Process tech.
(Routing Density)
Chip-to-PKG
interconnect
Si placement
sequence
PCB-like OSAT RDL Damascene
Die first/Die middle
Via-interconnect
Die last
FCB/TSV+FCB
Hundred of 2.nD
Configuration and Process
Combinations
Summary
Innovation!