the ieee 1149.4 std for mixed-signal test
DESCRIPTION
The IEEE 1149.4 std for mixed-signal test. J. M. Martins Ferreira FEUP / DEEC - Rua Dr. Roberto Frias 4200-537 Porto - PORTUGAL Tel. 351 225 081 748 / Fax: 351 225 081 443 ([email protected] / http://www.fe.up.pt/~jmf). The IEEE 1149.4 standard for mixed signal test. - PowerPoint PPT PresentationTRANSCRIPT
Leonardo da Vinci ALLEGRO© J. M. Martins Ferreira - University of Porto (FEUP / DEEC)
1
The IEEE 1149.4 std for mixed-signal testJ. M. Martins Ferreira
FEUP / DEEC - Rua Dr. Roberto Frias
4200-537 Porto - PORTUGAL
Tel. 351 225 081 748 / Fax: 351 225 081 443
([email protected] / http://www.fe.up.pt/~jmf)
Leonardo da Vinci ALLEGRO© J. M. Martins Ferreira - University of Porto (FEUP / DEEC)
2
The IEEE 1149.4 standard for mixed signal test
BST infrastructure (except the BST register)
TBIC
ABM
DBM
(AB1, AB2)
AT1
AT2
TDI
TMS
TCK
TDO
• The 1149.4 std defines an extension to 1149.1, to which it adds:– An analog test port (ATAP)
with two pins (AT1, AT2)– An internal analog test bus
(AB1, AB2)– A test bus interface circuit
(TBIC)– The analog boundary
modules (ABM)
Leonardo da Vinci ALLEGRO© J. M. Martins Ferreira - University of Porto (FEUP / DEEC)
3
IEEE 1149.4: The TBIC and the ABMs• Interconnect and parametric
tests can be carried out through the ABMs
• Analog test signals may be routed from / to the analog pins to / from the ATAP through the TBIC and the ABMs
• The TBIC and the ABM comprise a switching structure and a control structure
BST infrastructure (except the BST register)
TBIC
ABM
DBM
(AB1, AB2)
AT1
AT2
TDI
TMS
TCK
TDO
Leonardo da Vinci ALLEGRO© J. M. Martins Ferreira - University of Porto (FEUP / DEEC)
4
The test bus interface circuit (TBIC)• The TBIC defines the interconnections
between the ATAP (AT1 and AT2) and the internal analog test bus (at least two lines, AB1 and AB2)
• The TBIC comprises a switching structure and a control structure
BST infrastructure (except the BST register)
TBIC
ABM
DBM
(AB1, AB2)
AT1
AT2
TDI
TMS
TCK
TDO
Leonardo da Vinci ALLEGRO© J. M. Martins Ferreira - University of Porto (FEUP / DEEC)
5
TBIC: The switching structure
AT1
AT2
AB1 AB2
VH
VL
VTH
Vclamp
S1
S3
S2
S4 S9 S10
S8 S7 S5 S6
BST infrastructure (except the BST register)
TBIC
ABM
DBM
(AB1, AB2)
AT1
AT2
TDI
TMS
TCK
TDO
Leonardo da Vinci ALLEGRO© J. M. Martins Ferreira - University of Porto (FEUP / DEEC)
6
TBIC: Switching structure patterns
AT1
AT2
AB1 AB2
VH
VL
VTH
Vclamp
S1
S3
S2
S4 S9 S10
S8 S7S5 S6
Main testing conditions
Leonardo da Vinci ALLEGRO© J. M. Martins Ferreira - University of Porto (FEUP / DEEC)
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Switching assignments for defined instructions (TBIC)
AT1
AT2
AB1 AB2
VH
VL
VTH
Vclamp
S1
S3
S2
S4 S9 S10
S8 S7S5 S6
AT1
AT2
AB1 AB2
VH
VL
VTH
Vclamp
S1
S3
S2
S4 S9 S10
S8 S7S5 S6
Leonardo da Vinci ALLEGRO© J. M. Martins Ferreira - University of Porto (FEUP / DEEC)
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TBIC: Control structure
BST infrastructure (except the BST register)
TBIC
ABM
DBM
(AB1, AB2)
AT1
AT2
TDI
TMS
TCK
TDO
Serial input
mux
C/S
L
Parallel input
Parallel output
Serial output
Parallel input
Serial input
Serial output
Parallel input
Parallel input
Parallel input
S1 S2 S10
Control logic
Parallel output
Mode
Inputs available to the user VTH VTH
AT1 AT2 Switching structure comparators
Switching structure
Parallel output
Parallel output
Parallel output
Leonardo da Vinci ALLEGRO© J. M. Martins Ferreira - University of Porto (FEUP / DEEC)
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The analog boundary modules (ABM)• The ABMs in the analog pins
extend the test functions made available by the DBMs
• All test operations combine digital (via TAP) and analog test “vectors” (via ATAP)
• Each ABM comprises a switching structure and a control structure
BST infrastructure (except the BST register)
TBIC
ABM
DBM
(AB1, AB2)
AT1
AT2
TDI
TMS
TCK
TDO
Leonardo da Vinci ALLEGRO© J. M. Martins Ferreira - University of Porto (FEUP / DEEC)
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ABMs: Switching structure
SH SL SG
SB1 SB2
Analog pin
AB2
AB1 VH VL VG VTH
SD
Internal analog block
BST infrastructure (except the BST register)
TBIC
ABM
DBM
(AB1, AB2)
AT1
AT2
TDI
TMS
TCK
TDO
Leonardo da Vinci ALLEGRO© J. M. Martins Ferreira - University of Porto (FEUP / DEEC)
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ABMs: Switching structure patterns (1)
SH SL SG
SB1 SB2
Analog pin
AB2
AB1 VH VL VG VTH
SD
Internal analog block
Main testing conditions for analog
measurements
Leonardo da Vinci ALLEGRO© J. M. Martins Ferreira - University of Porto (FEUP / DEEC)
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ABMs: Switching structure patterns (2)
SH SL SG
SB1 SB2
Analog pin
AB2
AB1 VH VL VG VTH
SD
Internal analog block
Normal mission mode; pin connected
to core only.
Leonardo da Vinci ALLEGRO© J. M. Martins Ferreira - University of Porto (FEUP / DEEC)
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ABMs: Switching pattern requirements
SH SL SG
SB1 SB2
Analog pin
AB2
AB1 VH VL VG VTH
SD
Internal analog block
SH SL SG
SB1 SB2
Analog pin
AB2
AB1 VH VL VG VTH
SD
Internal analog block
Leonardo da Vinci ALLEGRO© J. M. Martins Ferreira - University of Porto (FEUP / DEEC)
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BST infrastructure (except the BST register)
TBIC
ABM
DBM
(AB1, AB2)
AT1
AT2
TDI
TMS
TCK
TDO
Serial input
mux
C/S
L
Parallel input
Parallel output
Serial output
Parallel input
Serial input
Serial output
Parallel input
Parallel input
Parallel input
SD SH SB2
Control logic
Parallel output
Mode
Inputs available to the user
VTH
Pin
Switching structure comparator
Switching structure
Parallel output
Parallel output
Parallel output
ABMs: Control structure
Leonardo da Vinci ALLEGRO© J. M. Martins Ferreira - University of Porto (FEUP / DEEC)
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The 1149.4 register structure• The 1149.4
register structure is entirely digital and identical to the corresponding 1149.1 structure
User registers
Identification register
Reg. BP
Decoder
Instruction reg.
Data mux
Data / instruction mux
TAP contr.
TDI
/TRST
TMS
TCK
TDO
BST register
TBIC cells
ABM cells
DBM (BST cells in 1149.1)
Leonardo da Vinci ALLEGRO© J. M. Martins Ferreira - University of Porto (FEUP / DEEC)
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The PROBE instruction
• The IEEE 1149.4 std defines a fourth mandatory instruction called PROBE:– The selected data register is the BS register– One or both of the ATAP pins connect to the
corresponding AB1/AB2 internal test bus lines– Analog pins connect to the core and to AB1/AB2
as defined by the ABM 4-bit control word– Each DBM operates in transparent mode
Leonardo da Vinci ALLEGRO© J. M. Martins Ferreira - University of Porto (FEUP / DEEC)
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Analog test operations• Principle of operation:
– The analog signal is applied to AT1 and the analog response is observed in AT2
– With AT1 connected to AB1, the analog signal may be routed to the internal circuitry or to an analog output pin
– Analog responses from the internal circuitry or from an analog input pin are routed to AB2, and observed in AT2
BST infrastructure (except the BST register)
TBIC
ABM
DBM
(AB1, AB2)
AT1
AT2
TDI
TMS
TCK
TDO
Leonardo da Vinci ALLEGRO© J. M. Martins Ferreira - University of Porto (FEUP / DEEC)
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SH SL SG
SB1 SB2 Analog pin
AB2 AB1
VH VL VG VTH
SD
AT1
AT2
AB1 AB2
VH
VL
VTH
Vclamp
S1
S3
S2
S4 S9 S10
S8 S7S5 S6
Observability of analog (input / output) pins• The signal present at any
analog (input / output) pin may be observed at AT2, with (or without) the core connected to the pin
BST infrastructure (except the BST register)
ABM
DBM
AT1
AT2
TDI
TMS
TCK
TDO
ABM
DBM
TBIC
(AB1, AB2)
Leonardo da Vinci ALLEGRO© J. M. Martins Ferreira - University of Porto (FEUP / DEEC)
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SH SL SG
SB1 SB2 Analog pin
AB2 AB1
VH VL VG VTH
SD
AT1
AT2
AB1 AB2
VH
VL
VTH
Vclamp
S1
S3
S2
S4 S9 S10
S8 S7S5 S6
Controllability of analog (input / output) pins• The signal present at any
analog (input / output) pin may be driven from AT1, regardless of the signal present at the analog input
BST infrastructure (except the BST register)
ABM
DBM
AT1
AT2
TDI
TMS
TCK
TDO
ABM
DBM
TBIC
(AB1, AB2)
Leonardo da Vinci ALLEGRO© J. M. Martins Ferreira - University of Porto (FEUP / DEEC)
20
SH SL SG
SB1 SB2 Analog pin
AB2 AB1
VH VL VG VTH
SD
AT1
AT2
AB1 AB2
VH
VL
VTH
Vclamp
S1
S3
S2
S4 S9 S10
S8 S7S5 S6
Impedance measurement between pin and ground
BST infrastructure (except the BST register)
TBIC
ABM
DBM
(AB1, AB2)
AT1
AT2
TDI
TMS
TCK
TDO
IT
VVT
ZD = VT / IT if:
• ZV >> ZS6 + ZSB2
• ZV + ZS6 + ZSB2 >> ZD
ZD
Leonardo da Vinci ALLEGRO© J. M. Martins Ferreira - University of Porto (FEUP / DEEC)
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Interconnect testing with 1149.4
SH SL SG
SB1 SB2 Analog output
AB2
AB1 VH VL VG VTH
SD
Internal analog block
SH SL SG
SB1 SB2
Analog input
AB2
AB1 VH VL VG VTH
SD
Internal analog block
SH SL SG
SB1 SB2 Analog output
AB2
AB1 VH VL VG VTH
SD
Internal analog block
SH SL SG
SB1 SB2
Analog input
AB2
AB1 VH VL VG VTH
SD
Internal analog block
VH
VL
?
DBM
TDO
ABM
DBM
(AB1, AB2)
DBM
TDO
ABM
DBM
(AB1, AB2)
DBM
TDO
ABM
DBM
(AB1, AB2)
DBM
TDO
ABM
DBM
(AB1, AB2)
VH
VL
?
Leonardo da Vinci ALLEGRO© J. M. Martins Ferreira - University of Porto (FEUP / DEEC)
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Functional description of a basic “1149.4 component”• The core circuitry is
restricted to– A voltage follower– A logic inverter
• The required 1149.4 infrastructure should only support the mandatory instructions
BST infrastructure (except the BST register)
ABM
DBM (AB1, AB2)
AT1
AT2
TDI
TMS
TCK
TDO
ABM
DBM
TBIC
Leonardo da Vinci ALLEGRO© J. M. Martins Ferreira - University of Porto (FEUP / DEEC)
23
Summary description of the 1149.4 infrastructure• Instruction codes (8-bit):
– EXTEST: $00– SAMPLE / PRELOAD: $02– PROBE: $01– BYPASS: $FF
• Boundary scan register (TDI-TDO, 14-bit):– TBIC (4-bit), ABM analog input (4-bit), ABM
analog output (4-bit), DBM digital input (1-bit), DBM digital output (1-bit)
Leonardo da Vinci ALLEGRO© J. M. Martins Ferreira - University of Porto (FEUP / DEEC)
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Implementation details
• The digital test infrastructure and core logic was implemented by Dr. Gustavo Alves in an EPM7128 Altera PLD (2,500 usable gates, 128 macrocells, 84 pin PLCC)
• All remaining blocks are implemented using discrete components (ADG452 + MAX4512 analog switches, LM311 comparators, TL081 OpAmp)
Leonardo da Vinci ALLEGRO© J. M. Martins Ferreira - University of Porto (FEUP / DEEC)
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“1149.4 component”: the digital test infrastructure
<Doc> <RevCode>
Carta "wire-wrapping" 1149.4 - Parte digital
A4
1 1Monday, May 28, 2001
Title
Size Document Number Rev
Date: Sheet of
VCC
VCC
VCC
VCC
VCC
C
R8
10K
12345
C
R9
10K
12345
C19
68n
C20
68n
JP14
HEADER 8X2
1 23 45 67 89 1011 1213 1415 16
C21
68n
JP13
HEADER 5X2
1 23 45 67 89 10
C22
68n
C24
68n
C25
68n
TP12/A 1
TP11/A 1
U6
1149_4
74
80
81
61 706968676564
63 605857565554
3637
52515049484645444140
73
831
2
14
2362
71
3 43 13 26 38 53 66 78
42
79
82 7 19 32 47 59 72
84
A
TDI
TMS
IN_PIN_COMP 1SD1SH1SC1SG
1SB11SB2
OUT_PIN_COMP 2SD2SH2SC2SG
2SB12SB2
AT1_COMPAT2_COMP
S10S9S8S7S6S5S4S3S2S1
/A
GCLK1GLCRn
OE2_GCLK2
TDI#
TMS#TCK#
TDO#
VCCI
NTVC
CINT
VCCI
OVC
CIO
VCCI
OVC
CIO
VCCI
OVC
CIO
GND
INT
TDO
GND
INT
GND
IOG
NDIO
GND
IOG
NDIO
GND
IOG
NDIO
OE1
TP9A 1
TP10A 1
C
R6
10K
123456
C
R7
10K
123456
C18
68n
C
R1
1K
12345
C23
68n
S1
ABM2_DATA
S2
ABM1_DATA
TBIC_DATA1
ABM2_SG
S3
TBIC_DATA2
ABM2_SDABM2_SH
ABM2_SB1
S4
ABM2_SC
ABM1_SG
ABM1_SB2
ABM1_SHABM1_SC
ABM1_SB1
S10S9
ABM2_SB2
S6
S8S7
S5
ABM1_SD
THE JP14 CONNECTOR ALLOWS THEUSER TO CONTROL THE 1149.4INFRASTRUCTURE USING A PC AND THE"TAPPER" WINDOWS 9X APPLICATION.FOR THE PIN MAPPING BETWEEN THECONNECTOR AND THE PC'S PARALLELPORT, SEE FILE "TAPCABLE.TXT".
THE JP13 CONNECTOR ALLOWS THEUSER TO PROGRAM THEEPM7128SLC84-10 PLD USING THEALTERA MAX+PLUS II SOFTWARE ANDTHE "BYTEBLASTER" PARALLELDOWNLOAD CABLE.
Leonardo da Vinci ALLEGRO© J. M. Martins Ferreira - University of Porto (FEUP / DEEC)
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Altera’s design environment (Max+plus II Baseline)
Leonardo da Vinci ALLEGRO© J. M. Martins Ferreira - University of Porto (FEUP / DEEC)
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Example description (ABM)
Leonardo da Vinci ALLEGRO© J. M. Martins Ferreira - University of Porto (FEUP / DEEC)
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Serial input
mux
Parallel input
Parallel output
Serial output
D_latch
DATA
clkDR
uptDR
ABM: the control structureTITLE " ABM control register ";
SUBDESIGN ABM_CR( TDI, TCK, en_clkDR, shift, en_uptDR, pin_comp : INPUT; TDO, D, C, B1, B2 : OUTPUT;)(...)
IF ( !en_clkDR ) THEN DATA = DATA ; CONTROL = CONTROL ; BUS1 = BUS1 ; BUS2 = BUS2 ; ELSIF ( !shift ) THEN DATA = pin_comp;
% Capture % CONTROL = GND; BUS1 = GND; BUS2 = GND; ELSE DATA = TDI; % Shift % CONTROL = DATA; BUS1 = CONTROL; BUS2 = BUS1; END IF;
TDO = BUS2;
IF ( !en_uptDR ) THEN D_LATCH = D_LATCH ; C_LATCH = C_LATCH ; B1_LATCH = B1_LATCH ; B2_LATCH = B2_LATCH ; ELSE D_LATCH = DATA;
% SHIFT -> LATCH -- update %
C_LATCH = CONTROL ; B1_LATCH = BUS1 ; B2_LATCH = BUS2 ; END IF;
D = D_LATCH.q ; C = C_LATCH.q ; B1 = B1_LATCH.q ; B2 = B2_LATCH.q ;
END;
Parallel input
Serial input
Serial output
Parallel input
Parallel input
Parallel input
SD SH SB2
Control logic
Parallel output
Mode
Inputs available to the user
VTH
Pin
Switching structure comparator
Parallel output
Parallel output
Parallel output
Data Control Bus1 Bus2
Leonardo da Vinci ALLEGRO© J. M. Martins Ferreira - University of Porto (FEUP / DEEC)
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ABM: the switching structure decoder
BEGIN TABLE M1, M2, D, C, B1, B2 => SD, SH, SC, SG, SB1, SB2 ;
1,1,0,0,0,0 => 0,0,0,0,0,0 ; % p0 - Completely isolated (CD state) % 1,1,0,0,0,1 => 0,0,0,0,0,1 ; % p1 - Monitored by AB2 % 1,1,0,0,1,0 => 0,0,0,0,1,0 ; % p2 - Connected to AB1 % 1,1,0,0,1,1 => 0,0,0,0,1,1 ; % p3 - Connected to AB1; monitored by AB2 %(...) 1,1,1,1,1,1 => 0,1,0,0,1,1 ; % p15 - Connected to VH and AB1; monitored by AB2 % 0,1,0,0,0,0 => 1,0,0,0,0,0 ; % p16 - Connected to core; isolated from all test circuits % 0,1,0,0,0,1 => 1,0,0,0,0,1 ; % p17 - Connected to core; monitored by AB2 % 0,1,0,0,1,0 => 1,0,0,0,1,0 ; % p18 - Connected to core and AB1 % 0,1,0,0,1,1 => 1,0,0,0,1,1 ; % p19 - Connected to core and AB1; monitored by AB2 % 0,1,1,X,X,X => 1,0,0,0,0,0 ; % p16 - Clause 6 - page 74 % 0,1,X,1,X,X => 1,0,0,0,0,0 ; % p16 - Clause 6 - page 74 % 0,0,X,X,X,X => 1,0,0,0,0,0 ; % p16 - Clause 4 - page 74 % 1,0,X,X,X,X => 0,0,0,0,0,0 ; % p0 - Clause 3 - page 74 %
END TABLE;
Parallel input
Serial input
Serial output
Parallel input
Parallel input
Parallel input
SD SH SB2
Control logic
Parallel output
Mode
Inputs available to the user
VTH
Pin
Switching structure comparator
Switching structure
Parallel output
Parallel output
Parallel output
D C B1 B2 M1,M2
Leonardo da Vinci ALLEGRO© J. M. Martins Ferreira - University of Porto (FEUP / DEEC)
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“1149.4 component”: the TBIC switching structure
<Doc> <RevCode>
Carta "wire-wrapping" 1149.4 - Estrutura de comutação do TBIC
A4
1 1Monday, May 28, 2001
Title
Size Document Number Rev
Date: Sheet of
VSS VSSVDD VDD
VSS
VDD
VSS
VDD
VSS VSS
VDD
VCC
VCC
VCC
VCC
VCC
VCC
VDD
VDD
VSS
C168n
C268n
+ -
U1
LM311
2 37
56
41
8
S1A
ADG202A
4 13521
3
12VS
S
VDD
GND
DIN
S
VL
S1D
ADG202A
4
13
5
78
6DIN
S
S1B
ADG202A
4
13
5
1516
14DIN
S
S1C
ADG202A
4
13
5
109
11DIN
S
+-
U2
LM311
237
56
41
8
S2C
ADG202A
4 135
10 911
D INS
S3B
ADG202A
4
13
5
1516
14DIN
S
TP1AT1 1
TP21
S2B
ADG202A
4 135
15 1614
D INS S2D
ADG202A
4 135
7 86
D INS
+ C15100u
+ C16100u
+ C17100u
C668n
C568n
C368n
C468n
R2
22K
S3A
ADG202A
4 135
21
3
12
VSS
VDD
GND
DIN
S
VL
R3
22K
JR1
CONN
PW
R 4-
R
1234
1234
S2A
ADG202A4
135
2 1312
VSS
VDDGND
D INSVL
U6LM7805C/TO
1 3
2
IN OUT
GND
TP3AT2 1
TP41
AB2AB1
S6S7S8S5
S10
S4S3
S2 S9
TBIC_DATA1
S1
TBIC_DATA2
S1: MAX4512CPE - PINO 12 DEVE DEIXAR-SE DESLIGADOS2,3: ADG452BN
Leonardo da Vinci ALLEGRO© J. M. Martins Ferreira - University of Porto (FEUP / DEEC)
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“1149.4 component”: the ABMs switching structure
<Doc> <RevCode>
Carta "wire-wrapping" 1149.4 - Estrutura de comutação dos ABMs; "Core" analógico
A4
1 1Monday, May 28, 2001
Title
Size Document Number Rev
Date: Sheet of
VDD VDD
VSS
VDD
VSS
VDD
VSS
VDD
VSS VSS
VSS
VDD
VDD
VSS
VCC VCC
VCC
VCC
VCC
VCC
VDD VSS VDD VSS
-
+
U4
TL0813
26
7 14 5 C13
68n
C1468n
S6D
ADG202A
4
13
5
78
6DIN
S
S6AADG202A
4
135
2 13 12
VSS
VDDGND
D INS VL
+
-
U5
LM311
2
37
5641
8
S6CADG202A
4 135
10 911
D INS
S7BADG202A
4 135
15 1614
D INS
S6BADG202A
4 135
15 1614
D INS
S7AADG202A
4
135
2 13 12
VSS
VDDGND
D INS VL
C868n
C768n
S5BADG202A
4 135
15 1614
D INSS5A
ADG202A4
135
2 13 12
VSS
VDDGND
D INS VL
TP51
TP6
ANALOG_IN
1 C968n
C1068n
R410K
TP71
TP8
ANALOG_OUT
1
+
-
U3
LM311
2
37
5641
8
S4AADG202A
4
135
2 13 12
VSS
VDDGND
D INS VL
C1268n
C1168nS4C
ADG202A
4 135
10 911
D INSS4B
ADG202A
4 135
15 1614
D INS
R510K
S4D
ADG202A
4
13
5
78
6DIN
S
ABM1_SD ABM2_SD
ABM1_DATA
ABM2_SB1
ABM2_SH
ABM2_SB2
ABM2_SL
ABM2_DATA
ABM2_SG
ABM1_SB2
AB2
ABM1_SB1AB1
ABM1_SH ABM1_SGABM1_SL
S4,6: MAX4512CPE - PINO 12 DEVE DEIXAR-SE DESLIGADOS5,7: ADG452BN
Leonardo da Vinci ALLEGRO© J. M. Martins Ferreira - University of Porto (FEUP / DEEC)
32
An “1149.4 component”: wire wrapping prototype
Leonardo da Vinci ALLEGRO© J. M. Martins Ferreira - University of Porto (FEUP / DEEC)
33
An “1149.4 component”: printed circuit board
Notes:
1) The ABM comparator inputs in this board differ from the standard (VTH is connected to the + input).
2) VG / VTH may be applied externally (internal value of VG is 0 V)
Selection of VTH (internal / external)
Selection of VG (internal / external)
Leonardo da Vinci ALLEGRO© J. M. Martins Ferreira - University of Porto (FEUP / DEEC)
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Proposed experiments: observability + controllability• Two experiments will be demonstrated
using the wire-wrapping “1149.4 component”:– The waveform at the analog output pin will be
observed at AT2, when the analog input is driven by a sine wave
– The waveform at the analog output pin will be driven from AT1 (a square wave), instead of the sine wave coming from the internal circuitry
Leonardo da Vinci ALLEGRO© J. M. Martins Ferreira - University of Porto (FEUP / DEEC)
35
Observing an analog input / output pin at AT2• PROBE is the current
instruction, the input ABM connects the pin to the core, the output ABM connectsthe pin to the coreand to AB2, AB2 is connected to AT2
BST infrastructure (except the BST register)
ABM
DBM (AB1, AB2)
AT1
AT2
TDI
TMS
TCK
TDO
ABM
DBM
TBIC
Leonardo da Vinci ALLEGRO© J. M. Martins Ferreira - University of Porto (FEUP / DEEC)
36
Observability test code segment• Recommendation:
Write the JTAGer testsegment enablingthe observability of the analog output as shown at right
AN_IN
AN_OUT
AT1
AT2
AN_IN
AN_OUT
AT1
AT2
Leonardo da Vinci ALLEGRO© J. M. Martins Ferreira - University of Porto (FEUP / DEEC)
37
Observability test code (demo component)
! Observability demo using the 1149.4 component
start:seltap0;rst;state irshift;ld cnt,8d;
! IR has 8 bitsnshfcp 40h,80h,C0h;
! Instr. S/P and infra-structure checkjerr tap-error;
! Abort test in case of TAP errorstate drshift;ld cnt,14d;
! 4 TBIC + 2x4 ABMs + 1 DBM + 1 DBMnshf 2020h;
! 0001(TBIC)- 0000(ABMin)- 0001(ABMout)- 00(DBMs)state irshift;ld cnt,8d;nshf 80h;
! Instr. PROBEtms1;
! Update-IRend:
halt; ! Stop here if everything is OKtap-error:
halt; ! Stop here if the TAP is faulty
<< Breakpoint
Before the
breakpoint
After the breakpoin
t
Leonardo da Vinci ALLEGRO© J. M. Martins Ferreira - University of Porto (FEUP / DEEC)
38
Controlling an analog output pin from AT1• EXTEST is the current instruction, the
input ABM disconnects the pin from the core,the output ABM disconnects the pin from the coreand connects it to AB1, AB1 connects to AT1
BST infrastructure (except the BST register)
ABM
DBM (AB1, AB2)
AT1
AT2
TDI
TMS
TCK
TDO
ABM
DBM
TBIC
Leonardo da Vinci ALLEGRO© J. M. Martins Ferreira - University of Porto (FEUP / DEEC)
39
Controllability test code segment• Recommendation:
Write the JTAGer testsegment enablingthe controllability (plus observability) of the analog output as shown at right
AN_IN
AN_OUT
AT1
AT2
AN_IN
AN_OUT
AT1
AT2
Leonardo da Vinci ALLEGRO© J. M. Martins Ferreira - University of Porto (FEUP / DEEC)
40
The SCAN STA400 (1149.4 analog test access device)• Features (from the data sheet):
– Compliant to IEEE 1149.1 and 1149.4– Analog mux / demux either dual 2:1
or single 4:1– Samples up to 9 analog test points– Includes CLAMP and HIGHZ instructions– TRST input– Input range from -0,5 V to +6,5 V
Leonardo da Vinci ALLEGRO© J. M. Martins Ferreira - University of Porto (FEUP / DEEC)
41
SCAN STA400:Operating modes
Leonardo da Vinci ALLEGRO© J. M. Martins Ferreira - University of Porto (FEUP / DEEC)
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SCAN STA400:Functional information• CE/CEI distinguish between
the two main operating modes (analog sample, mux / demux)
Leonardo da Vinci ALLEGRO© J. M. Martins Ferreira - University of Porto (FEUP / DEEC)
43
SCAN STA400:Template to determine the BSR contents1- Instruction
2- ABMs: switches, switching pattern, control word
3- TBIC: switches, switching pattern, control word
Leonardo da Vinci ALLEGRO© J. M. Martins Ferreira - University of Porto (FEUP / DEEC)
44
Demonstration board #1: Stand-alone STA400
A
AT1
The built-in current source is adjustable
JTAGer-compatible TAP connections
ATAP connections
+12 V / GND power supply
SCANSTA400 analog I/O pins
Notes:
1) The internal 7805 generates the +5 V power supply
2) The operating mode is selected via a set of built-in jumpers
0 CEI
1 CE 0 C1 0 C0 0 M
is 0, is 1
Leonardo da Vinci ALLEGRO© J. M. Martins Ferreira - University of Porto (FEUP / DEEC)
45
Demonstration board #2: STA400 and BCT8244• The STA400 and
the BCT8244 arein the same chain
• The BCT8244 is able to control theSTA400
• Parametric andfunctional tests are possible
input output
demux mux
SN74BCT8244
DIP Sw itc hes
1 / 2 S TA 4 0 0
1 / 2 S TA 4 0 0
A 0 A 2
A 1
A 2 3A 0 1
A 3
Demonstration board
A T2
A T1
TDO
TDI
A djus tab le c urrent s ourc e
HI
Us er proto ty p ing area
Leonardo da Vinci ALLEGRO© J. M. Martins Ferreira - University of Porto (FEUP / DEEC)
46
Schematic diagram
Leonardo da Vinci ALLEGRO© J. M. Martins Ferreira - University of Porto (FEUP / DEEC)
47
Demonstration board #2Adjustable current source
DIP switches that control the BCT8244 octal outputs
SN74BCT8244 BST octal (TI SCOPE family)
National Semiconductor SCANSTA400 Connectors and
space available for add-on boards
Leonardo da Vinci ALLEGRO© J. M. Martins Ferreira - University of Porto (FEUP / DEEC)
48
Add-on boards
X1
Carta de demons traç ão 1
X3
X4A 3
R, C, e tc .
A 2
X5
R, C, e tc .
A 1
A 0
X2
(pas s a-baix o)
C 2
R 1
R 2
(pas s a-a lto)
R 1
X4
C 1
A 0
X1
R 2 -
+
C 2
X2
-
+
A 1
X3
X5
C 1
Carta de demons traç ão 2
A 2
A 3
X6
Leonardo da Vinci ALLEGRO© J. M. Martins Ferreira - University of Porto (FEUP / DEEC)
49
Experiment #1: Control A01 via the BCT8244 scan octal
STA400 BCT8244
TDI
C0 1Y1
A0
A1A01
s: sine
p: pulse DIP switch
TDO
s/p
Leonardo da Vinci ALLEGRO© J. M. Martins Ferreira - University of Porto (FEUP / DEEC)
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Experiment #2: Functional test (observe A0 at AT2)
STA400 BCT8244
TDI
A0
A1A01
s: sine
p: pulse DIP switch
TDO
s/p
AT2
Leonardo da Vinci ALLEGRO© J. M. Martins Ferreira - University of Porto (FEUP / DEEC)
51
Experiment #3: Parametric testing (R=?)
STA400 BCT8244
TDI
A1A01
DIP switch
TDO
AT2 (read V)AT1 (drive I)
A0
R=?