the microprocessor is no more general purpose
DESCRIPTION
The Microprocessor is no more General Purpose. Design Gap. Problems with Fine Grained Approach FPGAs. Area in-efficient Percentage of chip area for wiring far too high Too slow Unavoidable critical paths too long Routing and Placement is very complex. Problems with Fine Grained FPGAs. - PowerPoint PPT PresentationTRANSCRIPT
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The Microprocessor is no more General Purpose
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Design Gap
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Problems with Fine Grained Approach FPGAs
• Area in-efficient– Percentage of chip area for wiring far too high
• Too slow– Unavoidable critical paths too long
• Routing and Placement is very complex
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Problems with Fine Grained FPGAs
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Coarse Grained Reconfigurable computing
• Uses reconfigurable arrays with path-widths greater than 1 bit
• More area-efficient• Massive reduction in configuration memory
and configuration time• Drastic reduction in complexity of Placement
& Routing
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Coarse Grained ArchitecturesClassification
• Mesh-based• Linear Arrays based• Cross-bar based
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Mesh Based Architectures
• Arranges PEs in a 2-D array• Encourages nearest neighbor links between
adjacent PEs • Eg. KressArray, Matrix, RAW, CHESS
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Matrix – Mesh based Architecture
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Matrix – Mesh Based Architecture
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Architectures based on Linear Arrays
• Aimed at mapping pipelines on linear arrays• If pipeline has forks longer lines spanning
whole or part of the array are used• Eg. RaPiD, PipeRench
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PipeRench – Linear Array based architecture
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PipeRench – Linear Array Based Architecture
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Cross-bar based Architectures
• Communication Network is easy to route• Uses restricted cross-bars with hierarchical
interconnect to save area• Eg. PADDI-1, PADDI-2, Pleiades
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PADDI-2 – Cross-bar based architecture
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PADDI-2 Cross-bar based Architecture
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Coarse Grained Architectures
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EGRA
• Architectural template to enable design space exploration
• Execute expressions as opposed to operations• Supports heterogeneous cells and various
memory interfaces
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EGRA
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Evolution of fine grained and coarse grained architectures
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EGRA – at Cell Level
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Architectural Exploration
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Architectural exploration
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EGRA vs CGRA vs FPGA
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EGRA – at array level
• Organized as a mesh of cells of three types– RACs– Memories– Multipliers
• Cells are connected using both nearest neighbor and horizontal-vertical buses
• Each cell has a I/O interface, context memory and core
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Control Unit
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EGRA Operation
• DMA mode– Used to transfer data in bursts to EGRA– To program cells and to read/write from
scratchpad memories• Execution mode– Control unit orchestrates data flow between cells
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EGRA – at array level
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Experimental Results
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Experimental Results
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Experimental Results
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EGRA Memory Interface
• Data register at the output of computational cells
• Memory cells can be scattered around in the array
• A scratchpad memory outside reconfigurable mesh
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Architectural exploration - Area
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Architectural exploration - Delay
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MORA
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The reconfigurable Cell
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Operating modes of RC
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Interconnection Topology
• Hierarchical– Level 1 used within 4x4 quadrant to provide
nearest neighbor connectivity– Interleaved Horizontal and Vertical connectivity of
length two– Each RC can receive data from at most two other
RCs and send data to at-most four other RCs– Data and control across quadrants is guaranteed
over Level 2 interconnection
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Interconnection Topology
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Computational Strategies
•Temporal computational load balancing•Spatial computational load balancing