THIN FILM ENCAPSULATED SIGE ACCELEROMETER FOR MEMS ABOVE IC INTEGRATION

L. Wen1, B.Guo2, L. Haspeslagh2, S. Severi2, A. Witvrouw2, R. Puers1

1ESAT-MICAS, K.U.Leuven, Kasteelpark Arenberg 10, Leuven B-3001, Belgium 2IMEC, Kapeldreef 75, Leuven B-3001, Belgium

ABSTRACT

This paper presents the design, fabrication and characterization of a thin film encapsulated SiGe accelerometer, in an attempt to demonstrate the feasibility of fabricating SiGe MEMS inertial sensors above standard CMOS with thin film wafer level permanent packaging. The capacitive in-plane inertial sensor features comb fingers and shock stoppers with minimum lateral gap of 500nm. The thickness of the structural layer is 4µm, which is processed on a wafer with silicon oxide protected metal layer, to mimic the top metal of standard CMOS. Both dynamic and angular electrical characterizations of the sensor are performed. The performance of the senor has been compared with commercialized accelerometer.

KEYWORDS

Thin film encapsulation; SiGe; MEMS above IC; Capacitive accelerometer

INTRODUCTION

MEMS-CMOS integration solutions have been researched intensively [1, 2]. Among them, MEMS above IC solution offers many advantages [3], such as foundry independency, minimum parasitics, capability of offering large interconnection array without bonding step, etc. SiGe MEMS above IC technology has been investigated and implemented with retrospect to its proper electrical and mechanical behavior, which is comparable to that of silicon [4-6]. Capacitive inertial sensors can benefit from the MEMS above IC technology as demonstrated using the poly-SiGe low thermal budget technology [7].

For inertial MEMS devices, the wafer level packaging issue is another important concern [8]. The temporary wafer level packaging can prevent the fragile MEMS from harsh environment during wafer dicing and die handling or wire bonding steps, if needed [9]. And the permanent packaging can also offer the proper working conditions for the MEMS devices, such as inertial sensors and resonators. In this paper, we discuss the design and characterization of a SiGe capacitive accelerometer demonstrator with thin film SiGe wafer level permanent packaging. The performances of the DUT (Device Under Test) are presented with dynamic and angular electrical characterizations. The comparison of the dynamic testing results between the DUT and the commercial accelerometer are also presented.

DESIGN AND FABRICATION

The designed comb based capacitive accelerometer

features 54 sensing fingers attached to the proof mass. There is a lateral overlap of 100 µm between the sensing fingers on the proof mass and the stationary ones, while the thickness of the fingers is 4µm, and the gap between the fingers 1 µm. (Fig. 1). The thickness of the structural layer is 4 µm, and the resonance frequency is 26.91 kHz the sensor has a differential sensing mechanism consisting of two stationary combs that face the moving comb. Additionally, at the end of the seismic mass, two groups of comb drive actuators are located, to serve as the electrostatic self-testing. Four stoppers are added to protect the seismic mass against adverse or severe shocks. The minimum lateral separation of this design is 500nm, while the free standing gap beneath the structural layer is 3 µm.

Figure 1: Schematic view of the designed SiGe accelerometer with supporting pillars for the thin film encapsulation.

The designed accelerometers are processed on top of

a protection layer (Fig. 2). A single metal layer is buried underneath the protection layer, to mimic the standard CMOS top metal [10]. The whole MEMS fabrication process should be able to prevent the buried metal layer from any thermal, chemical and mechanical damages. Via trenches are made to provide the electrical contact from the metal layer to the surface of the SiC protection layer. And from there, the electrode layer can be deposited. After patterning the electrode layer, sacrificial oxide can be deposited, and anchor holes are defined, followed by the deposition and definition of the SiGe structural layer. Then, the sacrificial layer between the MEMS device and the package is defined by Si-oxide filling and CMP. Anchors are etched and filled with the 10 μm thick SiGe cap layer. In this cap, release holes are etched, and a micro-crystalline SiGe (μc-SiGe) cover is formed. All

sacrificial oxide inside the cavity is then removed by vapor HF (vHF) through the local micro-channels in the μc-SiGe covers. These micro-channels, with a dimension significantly smaller than 100nm, are formed during the non conformal μc-SiGe PECVD deposition. The micro-channels prevent AlCu sealing material deposition inside the cavity during the sealing process. This achievement could be otherwise obtained only with extreme high aspect ratio release holes. The presence of the covers does not change the vHF Si-oxide etch rate. To support large packages for subsequent plastic molding, there are 18×18μm2 SiGe pillars with a spacing ranging from 80μm - 150μm [11].

Figure 2: Cross-section view of the SiGe MEMS above IC technology with the thin film encapsulation.

Fabrication results are shown in Fig. 3. The packaging of the device is stripped away intentionally to give an optical view of the device inside of the package (Fig. 3 a). From Fig. 2 (b), the releasing holes and the free standing gap between the structural layer and the substrate can be clearly observed. The sealing of the release holes leaves no metal deposition on the structural layer underneath.

Figure 3: Top SEM View of the fabricated DUT with the opened wafer level encapsulation (a). Cross-section SEM view of the Cap-DUT-Wafer stack (b).

DEVICE CHARACTERIZATIONS Dynamic tests

The fabricated devices are diced and characterized electrostatically at first, with the probe station and the HP4194A impedance/gain-phase analyzer. Both DC

voltage sweeps and frequency sweeps have been implemented to electrostatically characterize the functioning devices. It should be highlighted that this demonstrator is to prove the feasibility of the SiGe MEMS above IC technology and to improve its performance. It should pave the way for all similar applications. The use of the silicon wafer with a top metal layer is an ideal solution for this demonstration purpose. But for the dynamic testing, the signal from the DUT should be conditioned by an interfacing integrated circuit. Wire bonding is still used for this prototyping characterization. The DUT is wire bonded to the MS3110 capacitive readout chip and encapsulated in a DIL package for further tests. The dynamic tests are performed on a vibration test setup (Fig 4), consisting of a TIRAvib TBS 6000-mp shaker, a PCB Piezotronics 353B33 piezoelectric feedback accelerometer, a PCB Piezotronics 353B02 piezoelectric reference accelerometer and a data acquisition system.

Figure 4: Schematic view of the testing setup for the fabricated SiGe MEMS above IC accelerometers.

Before the DUT can be used on the dynamic test setup, the sensor chip should be conditioned to obtain a suitable sensing range and sensitivity. MS 3110 Evaluation Board is used for that purpose (Fig 5 a). After the sensor chip conditioning step, the DUT can be mounted to the shaker head with a dedicated power condition board (Fig 5 a).

(a) (b) Figure 5: Schematic view of the testing setup for the fabricated SiGe MEMS above IC accelerometers.

Electrode Anchor

Sensing finger

CAP Release hole

b

DUT

CAP

Pillar

a

Three major sets of dynamic tests have been

conducted, including sinusoidal actuation tests with 1g, 1.5g and 2g accelerations, at different frequency points, ranging from 10Hz to 1 kHz. Both the time domain (Fig 6) and the frequency domain (Fig 7) responses have been acquired, allowing a comparison between the DUT and the reference accelerometer. Fig. 6 shows the DUT and the PCB Piezotronics 353B02 piezoelectric reference accelerometer has comparable time domain responses. From the frequency domain response (Fig. 7), without filtering, the DUT shows a comparable signal to noise ratio compared to the reference accelerometer.

(a)

(b) Figure 6: Time domain responses of the DUT and the reference accelerometer with sinusoidal actuation at 80Hz (a) and 500Hz (b).

Figure 7: Frequency domain responses of the DUT and the reference accelerometer with 2g sinusoidal actuation at 500Hz. Angular tests

The DUT shows also a sensitivity to rotation around the axis parallel to the horizontal ground. The angular test has been implemented by using a rotational holder (Fig 8), to determine the response of the DUT to the projected portion of the gravitation to its main sensing axis. The DUT with the interfacing sensor chip are mounted to the DIP (Dual In Line Package) socket, which is electrically connected to the evaluation board for the signal conditioning of the sensor chip. The whole system is then mounted onto the rotational holder with mechanical clamps. By rotating the board around the rotational holder axis, the angular response of the DUT can be recorded.

Figure 8: Picture of the mounting mechanism of the DUT on the angular testing setup

The test results show that the DUT can respond to the

360° rotation around the axis perpendicular to the gravity direction, with the average sensitivity of 0.55 mV/10° (Fig 9).

Figure 9: Polar diagram of the DUT’s angular response with 360° rotation.

CONCLUSIONS

A SiGe MEMS capacitive accelerometer with thin film encapsulation for above IC applications has been fabricated with minimum lateral separation of 500nm and free standing gap of 3 µm. The wafer level permanent packaging has been achieved together with the definition of the device inside, with a signal sacrificial material releasing step. The DUT has been characterized electro-statically and dynamically. The performance of the DUT is characterized and compared with PCB Piezotronics 353B02 piezoelectric reference accelerometer. The vibration test results show that the thin film encapsulation prototyping DUT performs comparably to the commercial counter part, although wire bonding technique is still used for this prototyping. The DUT also shows a rotational response with respect to the gravity. These functionality tests demonstrate the feasibility of fabricating inertial MEMS devices above IC with thin film encapsulation with a thermal budget under 450 °C. This work paves the way to the 3D stacking of IC, inertial sensor and permanent packaging at one time, for related sensor applications.

REFERENCES [1] Takeuchi, H. Wung, A. Xin Sun Howe, R.T. Tsu-Jae

King “Thermal budget limits of quarter-micrometer foundry CMOS for post-processing MEMS devices”, Electron Devices, IEEE Transactions page(s): 2081 - 2086 , Volume: 52 Issue: 9, Sept. 2005.

[2] Huamao Lin, Walton, A.J. Dunare, C.C. Stevenson, J. Gundlach, A.M. Smith, S. Bunting, A.S. “Test Structures for the Characterization of MEMS and CMOS Integration Technology”, Semiconductor Manufacturing, IEEE Transaction, page(s): 140 - 147 , Volume: 21 Issue: 2, May 2008

[3] R. Modlinski, A. Witvrouw, A.Verbist, R. Puers and I. De Wolf, Mechanical characterization of poly-SiGe layers for CMOS–MEMS integrated application, J. Micromech. Microeng. 20 (2010) 015014

[4] L. Haspeslagh et al. “A Highly reliable CMOS integrated 11MPixel SiGe-based micro-mirror arrays for high-end industrial applications”, IEDM, San Francisco, CA, 2008, pp.655.

[5] S. Severi et al, “CMOS-integrated poly-SiGe cantilevers with read/write system for probe storage device”, TRANSDUCERS, Denver, 2009, pp. 2409.

[6] A. Schreurle et al., “A 10 μm thick poly-SiGe gyroscope processed above 0.35 μm CMOS”, IEEE MEMS, Golden, Colorado, 2007, pp. 39.

[7] L. Wen, L. Haspeslagh, J. Decoster, A. Witvrouw, R. Puers, Design and Characterization of a CMOS Compatible Poly-SiGe Low-g Capacitive Accelerometer, Proceedings of Eurosensors XXIV, 2010, Linz, Austria, 2010.

[8] Felton, L.E., Hablutzel, N., Webster, W.A., Harney, K.P., Chip Scale Packaging of a MEMS Accelerometer, Proceedings of 54th Electronic Components and Technology Conference, page(s): 869 - 873 Vol.1, June 1-4 2004.

[9] Wen L., Wouters K., Puers R., "SU-8 Thermo-Compressive Packaging for Post-CMOS Poly-SiGe MEMS." in Proceedings of Eurosensors XXIII, 2009, Lausanne, Switzerland, 2009.

[10] B. Guo, L. Wen et al., Above-IC generic poly-SiGe thin film wafer level packaging and MEM device technology: application to accelerometers." in Proceedings of 24th IEEE Conference on Micro Electro Mechanical Systems (MEMS 2011), Cancun, Mexico, 2011.

[11] P. Gonzalez et al., Design and characterization of thin SiGe membranes for MEMS packaging at wafer level, Proc.SAFE, Veldhoven, The Netherlands, 2008, pp. 548.

CONTACT * L.G.Wen, tel: 32-16-321716; wenlianggong@aol.com