timing analysis and optimization implications of bimodal cd distribution in double patterning...

Timing Analysis and Optimization Implications of Bimodal CD Distribution

in Double Patterning Lithography

Kwangok Jeong and Andrew B. Kahng

VLSI CAD LABORATORYUC San Diego

http://vlsicad.ucsd.edu/

Research supported by STARC

ASP-DAC Session 5B, January 21, 2009

http://vlsicad.ucsd.edu/

VLSI CAD LABORATORY, UCSD <2/15>

Motivation

Single exposure lithography All shapes printed by one exposure Adjacent identical features have same mean CD (critical

dimension), and spatially correlated CD variations Double patterning lithography (DPL)

Shapes are decomposed and printed in two exposures Adjacent features can have different mean CD, and

uncorrelated CD variations

New set of ‘bimodal’ challenges for timing analysis and optimization


DPL Approaches

Print lines

Misalignment No CD difference between two adjacent lines

CD control is key factor

Print edges

Exposure difference No CD difference between two adjacent lines

Overlay control is key factor

CD variationw/o misalignment

1st Exp./Etch 2nd Etch

1st Exp./Etch

CD variationw/ misalignment

2nd Etch1st Exp. & Etch

Poly

Hardmask

Final patterns

Resist

2nd Exp.

1st Exp. 2nd Exp.

1st Exp. 2nd Exp.1st Exp.

Final patterns

Poly

2nd Exp.

Resist

CD variationw/o misalignment

CD variationw/ misalignment


Bimodal CD Distribution

Two CD distributions and Two different colorings Two different timings

This Research Assess potential impact of bimodal CD distribution on

timing analysis and guardbanding Cell delay and power, path delay, clock skew, path timing slack

Seek potential solutions to minimize the impact of bimodal CD distribution

M12-type cell M21-type cell

Gates from CD group1Gates from CD group2


Impact on Path Delay Variation

Simulation results Mean and sigma of a long

inverter chain (16 stages)over all process corners (Min and Max combinations)

Alternately-colored paths smaller path delay variation 6.0

8.0

10.0

12.0

14.0

16.0

18.0

M1-M1-… M1-M2-… M2-M1-… M2-M2-…

Sig

ma

/ Mea

n (%

)

Path configurations

0n 1n 2n

3n 4n 5n

6n

16-stage

2-types 2-types 2-types 2-types

Covariance worsens path delay variation

Simulation setup 45nm PTM, Typical corner (TT), 1.0V, 25 °C 16 stages of 45nm INVX4 (Nangate Open Cell Library)

Each cell can have two different colorings Each color (Mask 1 or 2) can have two different process results

(Min or Max)


Impact on Timing Slack (Analysis)

Timing slack calculation Timing slack: Timing slack variation:

Clock skew Especially, clock skew from uncorrelated launching and

capturing clock paths are the major source of timing slack variation.

Example

pathdatacyclepathclockslack TTTT __

pathdatapathclockTTT TTpathdatapathclockslack __

222 ,cov2__

Large correlation is better for timing slack

Data (10 2 = 8~12ns)

Clock (10 2 = 8~12ns)

Worst slack = 5 5 = 0ns

Worst slack = min(clock) – max(data) = 8 12 = 4ns

Worst slack = 15 15 = 0ns

(a) Worst slack in DPLSmall delay variation

but large negative slack

(b) Worst slack in single exp.Large delay variation

but zero slack

Data (10 – 5 = 5ns)

Clock (10 – 5 = 5ns)

Data (10 + 5 = 15ns)

Clock (10 + 5 = 15ns)

BC

WC


Impact on Timing Slack (Simulation Setup) Testcase

AES from Opencores, Nangate 45nm library, PTM 45nm Extracted critical path

Clock launch: 14 stages

Clock capture: 14 stages

Data path: 30 stages

• Exhaustive tests (4 x 254) not feasible, so we fix the data path coloring.

Case Launch Capture1 M12+M12… M12+M12…

2 M21+M21… M21+M21…

3 M12+M12… M21+M21…

4 M21+M21… M12+M12…

5 M12+M21… M12+M21…

　M1 M2

Mean 3s Mean 3s

CD Mean

Uni-modal

50.00 2.00 - -

0nmPooled 50.00 2.00 - -

Bimodal 50.00 2.00 50.00 2.00

1nmPooled 50.00 2.50 - -

Bimodal 49.50 2.00 50.50 2.00

2nmPooled 50.00 3.61 - -

Bimodal 49.00 2.00 51.00 2.00

3nmPooled 50.00 4.92 - -

Bimodal 48.50 2.00 51.50 2.00

4nmPooled 50.00 6.32 - -

Bimodal 48.00 2.00 52.00 2.00

5nmPooled 50.00 7.76 - -

Bimodal 47.50 2.00 52.50 2.00

6nmPooled 50.00 9.22 - -

Bimodal 47.00 2.00 53.00 2.00


Impact on Timing Slack (Simulation Results)

Clock skew Even for the zero mean

difference case, clock skew exists and increases with mean difference

Pooled unimodal can not distinguish this clock skew

Timing slack Originally zero slack turns

out to have significant negative slack

Pooled unimodal shows very pessimistic slack

Timing slack (s) for MAX-MAX combination

-3.00E-10

-2.50E-10

-2.00E-10

-1.50E-10

-1.00E-10

-5.00E-11

0.00E+00

5.00E-11

1.00E-10

0nm 1nm 2nm 3nm 4nm 5nm 6nm

Mean difference (nm)

Sla

ck (

s)

Unimodal (Pooled)

Bimodal (case1)

Bimodal (case2)

Bimodal (case3)

Bimodal (case4)

Bimodal (case5)0.00E+00

1.00E-11

2.00E-11

3.00E-11

4.00E-11

5.00E-11

6.00E-11

0nm 1nm 2nm 3nm 4nm 5nm 6nm

Mean difference (nm)

Clo

ck s

kew

(s)

Launch (G12+G12...), Capture (G12+G12...)





22ps

53ps

Cases 1, 2, 5


Possible Solutions for Timing Optimization Self-compensation

Alternative coloring of timing paths reduce variation Same coloring sequence for clock network reduce clock skew But: restricted coloring can increase coloring conflicts

Solutions for coloring conflicts Candidate1: large sized cells to prevent conflicts between cells

Candidate2: Placement legalization after coloring (like UCSD *Corr)

2dpb Resmin

(a) Conflict (b) No conflict

2dpb Resmin

dpb

dpb: distance from poly center

to cell boundary

Resmin: minimum resolution

(a) Original placement (b) Alternative coloring

Coloring-fixed cells

Logical connection

Coloring conflict

(c) Conflict Removal

> Resmin


Self-Compensation Is Not Enough Self-compensation in path coloring reduces delay

variation, but bimodal CD impact is still significant

CD Mean Diff

Rise delay (ps)

Path1 Path2

0n 646.7 646.7

2n 615.4 671.3

4n 587.0 705.0

6n 550.4 736.1

CD Mean Diff

Rise delay (ps)

Path1 Path2

0n 646.7 646.7

2n 630.0 656.4

4n 614.5 674.8

6n 604.6 679.4Better, but can still have timing violations

After self-compensation

path1

path2

Two 9-stage timing paths

path1

path2

Each stage-FO4 model-50um wire

140nm

70nm

70nm


BEOL Compensation of Measured FEOL CD

UCSD: “Design-Aware Process Adaptation” FEOL metrology intentional BEOL CD biasing

DPL allows wire segments in different masks to change CD independently

Color interconnects differently for different CD groups F-factor = (in)flexibility factor for interconnect coloring, e.g., F=1,

All wire segments connected to CD_group1 gates must be in INT_MASK1 All wire segments connected to CD_group2 gates must be in INT_MASK2

path1

path2

path1

path2


Compensation with BEOL Biasing Small CD gates thick interconnect (large cap.) Large CD gates thin interconnect (small cap.) Example for F=0.8 (80% of interconnects colored according to the gate CD groups)

CD Mean Diff

Rise delay (ps)

InterconnectModel

Path1 Path2

Nominal (nm)

Width Space

0n 646.7 646.7 0.07 0.07

2n 630.0 656.4 0.07 0.07

4n 614.5 674.8 0.07 0.07

6n 604.6 679.4 0.07 0.07

CD Mean Diff

Rise delay (ps)

InterconnectModel (biasing)

Path1 Path2

INT1 (80%)

INT2(20%)

Space

Width Width

0n 646.7 646.7 0.07 0.07 0.07

2n 618.2 646.7 0.071 0.063 0.073

4n 601.6 646.7 0.072 0.058 0.075

6n 585.1 652.3 0.075 0.053 0.076

meet timing Change metal/ILD thickness?


Conclusions

Analytical and empirical assessments of DPL potential impact on timing analysis error and design guardband

Traditional ‘unimodal’ analysis may not be viable for DPL

Our analysis: 20% or greater change in timing

Self-compensation strategies, along with BEOL biasing, can reduce impact of bimodal CD variation

Work at UCSD: “Design-Aware Process Adaptation”

Ongoing work: more accurate, efficient and practical solutions to ‘bimodal-awareness’ challenges in timing analysis and circuit optimization

BACKUP


Impact on Cell Delay and Power Monte Carlo simulations : #10K

DPL1: (2n-1)-th gate is group1 and 2n-th gate is group2 DPL2: 2n-th gate is group1 and (2n-1)-th gate is group2 Unimodal: CD distribution covers CDgroup1 CDgroup2

Unimodal representation is too pessimistic Characteristics of DPL1 and DPL2 are very different!

Delay (mean)

4.65E-11

4.70E-11

4.75E-11

4.80E-11

4.85E-11

4.90E-11

4.95E-11

5.00E-11

DPL1 DPL2 DPL1 DPL2

Bimodal Unimodal Bimodal Unimodal

Delay (sigma)

0

5E-13

1E-12

1.5E-12

2E-12

2.5E-12

DPL1 DPL2 DPL1 DPL2


Leakage (mean)

0.00E+00

1.00E-08

2.00E-08

3.00E-08

4.00E-08

5.00E-08

DPL1 DPL2 DPL1 DPL2


Leakage (sigma)

0.00E+00

5.00E-07

1.00E-06

1.50E-06

2.00E-06

DPL1 DPL2 DPL1 DPL2


risefall

risefall

Input 1Input 0

Input 1Input 0605954 61

Bimodalgroup1

Bimodalgroup2

Worst CDBest CD

Unimodal

56 64 66

nmσnmMean

nmσnm, Mean

nmσnm, Mean

uniuni

GG

GG

63 ,60

53 61

53 59

22

11

2n


Impact on Design Guardband

Comparison of required design guardband

Unimodal approximation: conservative but easy Lead to over-design But can use conventional flow

Bimodal-aware: realistic but complex method New bimodal-aware timing analysis and new timing-driven

design optimizations are required

0.00E+00

5.00E-12

1.00E-11

1.50E-11

2.00E-11

2.50E-11

3.00E-11

1 nm 2 nm 3 nm 4 nm 5 nm 6 nm

De

lay

(s)

Mean Difference

Worst case: Large CD groupBest case: Large CD groupWorst case: Small CD groupBest case: Small CD groupWorst case: Pooled CDBest case: Pooled CD

Timing guardbandfor large CD group

Timing guardbandfor small CD group

Timing guardbandfor pooled-unimodal

timing analysis and optimization implications of bimodal cd distribution in double patterning...

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