tms320c50 architecture - professor murugan pallikonda …€¦ · · 2014-06-26comparison between...

7/7/2013 TIFAC CORE IN NETWORK

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TMS320C50TMS320C50ArchitectureArchitecture

OVERVIEW OF DSP

PROCESSORS


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PROCESSORS

BY

Dr. M.Pallikonda Rajasekaran,

Professor/ECE


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Short history of DSPs

• 1960

• DSP hardware using discrete components

• 1970

• Monolithic components for DSP subsystems


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• 1979

• Intel 2920 DSP

• (40 pin DIP)(EPROM,A/D,D/A,RAM)(1200bps modem)

• 1982

• Texas Instruments TMS32010

Input / Output

Serial ports

Computer

Engine

Inside a DSP?


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Serial ports

Timers

Host ports

External ports

Link portsProgram Data

Memory Memory

I/O

connects

to

outside

world

INSIDE A DSP ENGINE?


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Why DSP?

- Flexible to change Signal ProcessingOperations through a change in Software,whereas hardwired machines are difficult toReconfigure.

- High Speed Parallel Processing enables it


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- High Speed Parallel Processing enables it

to Real World Processing.

- Multi-Function Instruction like MAC etc,.

- Multiple data paths

- Flexible addressing modes

Stored

Program

and

Data

Program

Control

ALUInput

Output

Von Neumann Architecture

MEMORY ARCHITECTURE


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ALU

Program

Control

Input

Output

Stored

ProgramStored

Data

Von Neumann Architecture

Harvard Architecture

• Conventional microprocessors

use:

• Von Neumann architecture

• -program and data all in a single

memory

• -Address and data buses are

shared between instruction and

data fetches.

-simple

-effective

BUT

performance problems:


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performance problems:

-fetch for next instruction collides with data fetch/store

-Buses may be idle during instruction decode

CPU/ALU

MemoryAddre

ss

Data

• Most DSP chips use Harvard architecture

• -separate memory space(s) for program and data

• -separate data and program buses

CPU/ALUProgram

Memory

P Address


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Data

Memory

#2

MemoryInstr.

Data

Memory

#1

D1

AddressD1 Data

D2 Address D2 Data

Comparison between DSP &

GP processor• GP µP optimized for:

• -Multi task operations

• -handling huge OS

• -handling various

DSPs optimized for:

-special digital processing

-real time processing


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• -handling various

programs

• -Multiple I/O management

• -transporting large size of

data

-small code size

-single program

-limited number of I/O

-low power

DSP LEADING MANUFACTURERS

TEXAS INSTRUMENTS (TI)


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TEXAS INSTRUMENTS (TI)

ANALOG DEVICES (ADSP)

MOTOROLA


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TMS320C320 DSP Family

TMS320C6000

C62X,C64X,C67X DSPs

DSP TEXAS

INSTRUMENTS FAMILY


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TMS320C2000

C24X,C28X DSPs

Control

Optimized

TMS320C5000

C54X,C55X DSPs

C62X,C64X,C67X DSPs

Power

Efficient

High

PerformanceOMAP

C55X+ARM

www.ti.com

TMS320C2000 PLATFORM ROADMAP


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TMS320C2000 family offers various DSP processors for motor control. Based on the specific requirements, the user can choose the particular device for the speed control of Induction Motor/Brush less motor/ Switch Reluctance motor. In this platform varieties of DSP Processors are available in 3 categories.

TMS320C2000 DSP Platform


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categories.

• TMS320F240

• TMS320F2407

• TMS320F2812.

Targeted for Industrial Automation, Automatic Control Application, UPS, Motor Control, etc.

TMS320F240 TMS320F2407A TMS320F2812

16 Bit Fixed point 16 Bit Fixed point 32 Bit Fixed point

20 MIPS 40 MIPS 150 MIPS

544 x 16 Bit RAM 2.5k x 16 Bit RAM 18k x 16 Bit RAM

3 Timers 4 Timers 7 Timers


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SPI & SCI Serial

ports

SPI, SCI & CAN

Serial ports

SPI, SCI & CAN

Serial ports

12 PWM Channels 16 PWM Channels 16 PWM Channels

16 Channel ADC @

6 microsec

conversion time

16 Channel ADC

@ 0.5 micro sec

conversion time

16 Channel ADC @

200 ns conversion

time



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This has got 3 series of DSP Processor family.

� TMS320C62XX � 32 Bit Fixed Point DSP

TMS320C6000 DSP Platform


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� TMS320C64XX � 32 Bit Fixed Point DSP

� TMS320C67XX � 32 Bit Floating Point DSP

Development Tools

�CODE COMPOSER STUDIO

It includes


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�Assembler

�Linker

�Simulator

�C/C++ compiler

�Debugger

�Blackfin processors

�Tiger SHARC processors

ANALOG DEVICES

FAMILY


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�Tiger SHARC processors

�SHARC DSPs

�ADSP-21xx

�Mixed signal DSPs

www.analog.com/dsp

NOMENCLATURE OF DSP

PROCESSORS

• TMS 320 C 25 GB LTMX-Expt. Device C-CMOS

TMP-Prototype Device E-CMOS EPROM

TMS-Qualified Device

PACKAGE TYPE TEMPERATURE


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PACKAGE TYPE TEMPERATURE

GB-Ceramic L -0° -70°

N-Plastic DIP H -0° -50°

FN-Plastic Leaded S - -55° -100°

FD-Ceramic Leadless M - -55° - 125°

A - -40° -85°

TMS320C5x Family Features

• Fabrication using CMOS integrated-circuit technology

• Architectural design is based on the ’C25

• Advanced Harvard architecture

• A CPU with application-specific hardware


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• A CPU with application-specific hardware logic

• On-chip peripherals

• On-chip memory

• Highly specialized instruction set

TMS320C50 PROCESSORTMS320C50 PROCESSOR

TMS320C50PQ57


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TMS320C50PQ57

16 X 16 Multiplier

CPU

16-bit T-Reg 1,2

32-bit P-register

16-bit T-Reg0

TMS320C50

I/O Ports

64K X 16

D/P RAM

B0

512 X 16

D. RAM

B1

512 X 16

D. RAM

B2

32 X 16

D/P RAM

9K X 16

P. ROM

2K X 16

Software

Waitstates

A(15-0)

D(15-0)

16-bit Barrel

Shifter (L or R)


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32-bit P-register

11 Shadow Registers

32-bit ALU

32-bit Accumulator and Buffer

ShiftL( 0 – 7 )

8 Auxiliary Registers

8 Level H/W Stack

3 Status Registers

Block repeat/Circular Buffer

ShiftL(0, 1, 4, -6)

BitSet, Clear

Test, Toggle

PLU

Timer

Serial Port

Sync

Shifter (L or R)

16-bit ∗∗∗∗ 16-bit hardware multiplier with a 32-bit

product capability

32-bit arithmetic logic unit (ALU)

PLU-Executes IIy only logical operation –without

affecting Accumulator

Central Arithmetic Logic Unit (CALU )


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affecting Accumulator

32-bit accumulator (ACC)

32-bit accumulator buffer (ACCB)

0- to 16-bit left and right data barrel-shifters

TMS320C50 Multiplier/Accumulator

32

T Register (16)

Multiplier (16 X 16)

P Register (32)

MUX

Program Bus

Data Bus16

1616

1616

3232Right/Left

Shifter

(0-16)

32

MUX

1632


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Left Shifter (0,1,4,-6)

Arithmetic Logic Unit (ALU)

Accumulator Register (32)

32

32

32

32

MUX

32

Left Shifter (0 – 7)

Accumulator Buffer (32)

16

32

(0-16)

Data

0000

Program

0000

EEPROM

(48KW)

C50 MEMORY MAPPING

INTERNAL

RAM (32KW)

7FFF


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FFFFFFFF

EXTERNAL

RAM (16KW)

C000BFFF

EXTERNAL

RAM

(32KW)

7FFF8000

TMS320C50 DATA MEMORYTMS320C50 DATA MEMORY


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•Total memory = 0000h – FFFFh (64KW)

•Total no. pages = 200h

•Every page contains 80h locations

•Page 0 = 0h * 80h = 0000 to 007F

•Page 1 = 1h * 80h = 0080 to 00FF

• . . . . . . .

TMS320C50 DATA MEMORYTMS320C50 DATA MEMORY


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• . . . . . . .

• . . . . . . .

• . . . . . . .

•

•Page 100 = 100h * 80h = 8000 to 807F

•Page 1FF = 1FFh * 80h = FF80 to FFFF

Direct addressing-ADD 9h

Indirect addressing

Immediate addressing-Rpt # 99

Addressing ModesAddressing Modes


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Immediate addressing-Rpt # 99

Dedicated-register addressing

Memory-mapped register addressing

Circular addressing

Dedicated-register addressing

• BLDD BMAR,DAT 100

BLDD-Block Move from Data memory to

Data memory


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Data memory

• BMAR-Block move Address Register

• BMAR-200h-Predefined

• Data in Address 200h is copied to data

memory location 100h

Memory-mapped register addressing

• LMMR, CBCR #800h

• Data in CBCR is loaded to the location


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• Data in CBCR is loaded to the location

800H

• CBCR-Circular buffer control Register

Circular addressing

• CBSR-1

• CBSR-2

• CBER-1


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• CBER-1

• CBER-2

• CBCR

• Used for convolution, correlation & FIR Filter

ASSEMBLEY LANGUAGE PROGRAMS

Linear convloution.text

.mmregs

START:

LDP #0002H

LAR 3,#8200H ;y(n) starting

LAR 4,#0007 ;N1+N2-1

LAR 1,#8100H ; x(n) data array with N1-1 trailing zeros

LOP: MAR *,1

LACC *+

SACL 050H ;starting of the scope of multiplication

LAR 2 ,#0153H ; end of the array, to be multiplied with

input :

h(n) - program memory

c100 - 1

c101 - 3

c102 - 1

c103 - 3

c104 - 0

c105 - 0

c106 - 0

c107 - 0

x(n) - data memory


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LAR 2 ,#0153H ; end of the array, to be multiplied with

h(n) {150+N1-1}

MAR *,2

ZAP

RPT #0003 ;N1-1 times so that N1 times

MACD 0C100H,*-

APAC ;to accmulate the final product sample

MAR *,3

SACL *+

MAR *,4

BANZ LOP ,*-

H: B H

x(n) - data memory

8100 - 0

8101 - 1

8102 - 2

8103 - 1

output:

y(n) - data memory

8200 - 1

8201 - 5

8202 - 8

8203 - 8

8204 - 7

8205 - 3

8206 - 0

•Basic text editor :This can be a very simple application such as

windows notepad.It is used for entering DSP

programs

•Assembler/ Compiler :Used to convert the user editor based files into a

machine readable format

•Conversion :Converts assembled and linked DSP code into a

Basic software tools for dsp design


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•Conversion :Converts assembled and linked DSP code into a

Utilities DSP chip executable format (.hex, .bin, .asc etc)

•Down loader :It is used to transfer the DSP executable format

into the DSP development board

•Debugger :Enables software to be tested for the particular

DSP device; the debug environment may be in

the form of a simulator or emulator

Compiler

Optimizer

C

C++Low

SourceEfficiency Effort

80 – 100%

Software


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Hand

Optimize

ASM 100% High

Text

Assembler

optimizer

Linker Debugger

Link.cmd

Assembler

Software Tools


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Compiler

optimizer

Text

editor

.c

Linker DebuggerAssembler

.out.asm .obj

.c - c source file

.asm - assembly source file

.obj - object file

.out - executable file

.cmd - linker command file

DSP choosing considerations

• Arithmetic formats

• Data width

• Speed


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• Speed

• Memory organization

• Ease of development

• Multiprocessor support

• Power consumption management

• Cost

• Fixed point

• -difficult programming

• -low cost

• -limited dynamic

Floating point

-more flexible

-easier to program

-more expensive


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• -range & precision -higher power

consumption

Data widths are

-32 bit

-16 bit

-24 bit

-20 bit

Cost considerations

-chip size

-pin number


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-pin number

-external memory

Memory organization

-On and Off-chip memory size

Development tools:

-software tools

assemblers

linkers

simulators

debuggers

compilers


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-hardware tools

development boards

emulators

Cost:

• Least expensive DSPs have

-fewer features

-less on chip Memory

-lower performance

• Chipset price depends on:


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• Chipset price depends on:

-Packaging

-Quantity

MAC using GPP

1

2

11

12

3

X

11

24

9

∑ 44

R0

R1

R2

Clr A ;Clear Accumulator A


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2

3


Clr B ; Clear Accumulator B

Loop Mov *R0, Y0 ; Move data from memory location 1 to register Y0

Mov *R1,X0 ; Move data from memory location 2 to register X0

Mpy X0,Y0,A ;X0*Y0 ->A

Add A,B ;A + B -> B

Inc R0 ;R0 + 1 -> R0

Inc R1 ;R1 + 1 -> R1

Dec N ;Dec N (initially equals to 3)

Tst N ;Test for the value

Jnz Loop ;Different than zero loop again

Mov B,*R2 ;Move result to memory

MAC using DSP

• Harvard Architecture allows multiple

memory reads11

12

3 11 R2


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Rep N ; Rep N times the next instruction

MAC *(R0)+, *(R1)+, A ; Fetch the two memory locations pointed by R0 and R1, multiply

them together and add the result to A, the final result is stored back

in A

Mov A, *R2 ; Move result to memory

1

2

3

X 24

9

∑ 44


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•.mmregs

•.text

•Start:

LACC #2345H

LAR AR1,#8000H

LAR AR2,#0fffH

Loop:


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Loop:

MAR *,AR1

SACL *+,AR2

BANZ Loop,*-

HERE:B HERE

.end


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TI – 5000 SERIES

TMS320C50

1. MICRO 50 ST

2. MICRO 50 LC


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2. MICRO 50 LC

3. MICRO 50 EB

TMS320VC5416

1. MICRO 5416

2. MICRO 5416 AT

TMS 320C50 STARTER KIT


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TMS 320C50 TRAINER KIT


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C50

PROCESSOR

EXTERNAL

DATA

MEMORY

MONITOR

EEPROM

TIMER &

SERIAL

LOGIC

TIMER

PORT

CONNECTOR

BU

S E

XPA

ND

ER

BU

S E

XPA

ND

ER

AnalogAnalog

OutputOutput

SERIAL

PORT

C50 TRAINER KITC50 TRAINER KIT


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(MICRO 50LC)(MICRO 50LC)

PROCESSOR

EXTERNAL

PROGRAM

MEMORYHIGH

SPEED

ADC

HIGH

SPEED

DAC

BATTERY

BACKUP

RESET

LOGIC

BU

S E

XPA

ND

ER

BU

S E

XPA

ND

ER

AnalogAnalog

InputInput

TMS320C50 KIT WITH FUNCTION GENERATOR


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TMS 320C50 PROFESSIONAL TRAINER KIT


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TMS 320VC5416 TRAINER KIT


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TMS320VC5416 ADVANCED TRAINER KIT


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TI – 6000 SERIES

TMS320C33

1. MICRO 33


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1. MICRO 33

TMS320C6713

1. MICRO 6713 AT

TMS 320C33 TRAINER KIT


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TMS320C6713 TRAINER KIT


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MICRO-6713

TI – 2000 SERIES

TMS320F240

1. MICRO 240


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TMS320F2407

1. MICRO 2407

2. MICRO 2407 EB

TMS 320F240 TRAINER KIT


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TMS 320F2407 TRAINER KIT


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IPM UNIT


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TMS 320F240 BASED MOTOR CONTROL


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ANALOG DEVICES SERIES

ADSP 2181

1. EZ KIT 81

2. MICRO 81 AD

3. MICRO 81 AT


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3. MICRO 81 AT

ADSP 2189

1. MICRO 89 ST

2. MICRO 89 AT

ADSP 2191

1. MICRO 91

ADSP 2181 ADVANCED TRAINER KIT


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ADSP 2181 TRAINER KIT


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ADSP 2181 TRAINER KIT


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THANK YOUTHANK YOU


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THANK YOUTHANK YOU

tms320c50 architecture - professor murugan pallikonda …€¦ · · 2014-06-26comparison between...

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