tools - logiblox - chapter 5 slide 1 fpga tools course the logiblox gui and the core generator...

Tools - LogiBLOX - Chapter 5 slide 1

FPGA Tools Course

The LogiBLOX GUI and the Core Generator

LogiBLOX L

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Objectives

• Understand the advantages of using LogiBLOX and Core Generator components

• Understand how to incorporate a LogiBLOX component or Core into a design

• Learn the capabilities of the LogiBLOX components


Outline

• About the LogiBLOX GUI• About the Core Generator• Summary


Why is LogiBLOX important?

• The LogiBLOX GUI is used for creating high-level components

• LogiBLOX contains templates of VARIABLE SIZE• Each templates has different options that enable the user

to customize device utilization• The GUI disables selections that are incompatible with

your design selections• LogiBLOX components are entered into a schematic or

HDL code just like a macro• Functional simulation is possible without implementation


How to use LogiBLOX in HDL code

• Instantiation of some LogiBLOX components is often essential to synthesis users, since most synthesis tools cannot optimize for FPGA architectural features (e.g. RAM).

• To instantiate a LogiBlox function:

– Use the LogiBLOX GUI to create the custom component

– Cut and paste the VHDL entity (.vhi) or Verilog component declaration (.vei) the LogiBLOX GUI creates


Creating a LogiBLOX Component

• Invoke the LogiBLOX GUI– On PC, use the command Start -> Programs -> Xilinx -> LogiBLOX

• The Module Selector appears

Specify Module type

Setup LogiBLOX to specifyOutput file directoryDesign Entry and Simulation toolsPart typeOutput Files for simulation


After selecting a Module...

• Name the component• Specify a bus width• Select the desired ports• Choose a Style and

Operation• Choose a loading value• For example, an

asynchronous reset for a 4-bit counter will require an Async Val of “0000”


Module Types

• Clock Dividers• Comparators• Data Registers• Inputs/Outputs• Memories• Shift Registers• Simple Gates• Tristate Buffers

• Adders• Subtracters• Counters• Constants• Pads• Multiplexers• Decoders


Counters

• Choosing a style will determine the resources used for the component

• For example, choosing the Maximum Speed style for an XC4000 device tells the software to use the Carry Logic resources to generate the fastest implementation style

• The Counter styles include binary, Johnson, LFSR, or One-Hot encoded counters


Memories

• The Memories component creates custom sized RAM, ROM, or dual-port RAM

• This component will create the input decoder and output multiplexer when necessary

• Specify the necessary bus width and memory depth to customize the size

• Use a memory file to initialize a memory (for example, tenths.mem)


Multiplexers

• The Multiplexer component can have up to eight input busses

• This component can be optimized for area and speed

• The Mux component can utilize tristate buffers by selecting the Wired-AND Style when an XC4000 device has been selected


Outline

• About the LogiBLOX GUI

• About the Core Generator• Summary


Why is the Core Generator important?

• The Core Generator reduces design turn around time, since the components are pre-verified and only require that components be instantiated into a design.

• Predictable performance and functionality reduces verification and compile times, while reducing design risk.

• The Core Generator supports VHDL, Verilog and schematic design entry methodologies.


Core Generator

• The Core Generator is a graphical interactive tool for creating large, high-level modules

• The Core Generator currently supports XC4000E/EX/XL/XV and SPARTAN FPGAs. Limited support for Virtex is also available.

• All components are verified. Most allow some customization.

• All Cores are entered into a design through direct instantiation, so no optimization occurs.

• Most components are pre-placed so performance can be reproduced.


CORE Generator Library

• LogiCOREs and Alliance COREs are high-level functions that can be used in many applications

• LogiCOREs are supported by Xilinx

• LogiCOREs can be created with the Core Generator for immediate implementation

• Alliance COREs can be obtained by contacting the appropriate Alliance CORE Partner

• Contact information for each Alliance CORE Partner is provided in the associated data sheet

• Alliance COREs are made and supported by Xilinx’s Alliance CORE Partners


LogiCORE Application Areas• Basic Elements

– Multiplexers and Parallel to Serial Converters

• DSP Functions– These range from small building blocks such as

Time Skew Buffers to larger system-level functions such as FIR filters and Correlators

• Math Functions– Accumulators, Adders, Subtracters,

Complementers, Multipliers, Integrators, and Square Root generators

• Memories– Pipelined Delay Elements, Single and Dual Port

Rams, ROMs, and Synchronous FIFOs

• PCI– Master and Slave Interfaces, and PCI Bridge


Alliance CORE Application Areas• Base-Level Functions

– Processor Peripherals

* Such as DMA Controllers and Programmable Interrupt Controllers

– Processor Products

* Such as RISC CPU Cores

– UARTs

• Communication and Networking– ATM

– Forward Error Correction

* Such as Reed-Solomon Encoders/ Decoders

– T1 framers

• Standard Bus Interfaces– PCMCIA and USB


Outline

• About the LogiBLOX GUI• About the Core Generator

• Summary


Summary

• LogiBLOX components are especially useful for creating custom size and function components– Arithmetic functions can use the Carry Logic resources

– The Memories component will create the necessary decoder and multiplexer necessary for large RAMs, ROMs, and FIFOs

• The Core Generator enables the creation of a large range of high-level LogiCOREs

• AllianceCORE Partners have created a broad selection of large system-level functions


For More Information...

• Try using the On-Line Help menu for each component. Most questions about each component can be answered here with little effort.

• Consult the LogiBLOX Users Guide on the M1 Documentation CD-ROM.• Refer to the LogiCORE PCI Data Book or the CORE Solutions Data Book.• Check the CORELINX area of http://www.xilinx.com/products for the latest

information about unreleased Cores.


Questions

• Arithmetic functions can use what special resource to improve performance and density?

• What advantage is there in using a LogiBLOX Ram rather than a Ram from the Xilinx Unified Library?

• AllianceCOREs are created, tested, sold, and supported by Xilinx’s AllianceCORE partners. (True/False)

tools - logiblox - chapter 5 slide 1 fpga tools course the logiblox gui and the core generator...

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