trends and challenges in vlsi technology scaling towards 100nm · 2002. 1. 8. · • vlsi...
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Stefan Rusu 9/2001 ©2001 Intel Corp. Page 1
Trends and Challenges in VLSI Trends and Challenges in VLSI Technology Scaling Towards 100nmTechnology Scaling Towards 100nm
Stefan RusuStefan RusuIntel CorporationIntel [email protected]@intel.com
September 2001September 2001
Stefan Rusu 9/2001 ©2001 Intel Corp. Page 2
AgendaAgenda
•• VLSI Technology TrendsVLSI Technology Trends–– Frequency and power trendsFrequency and power trends
•• Scaling ChallengesScaling Challenges–– Transistor scalingTransistor scaling–– Interconnect scalingInterconnect scaling–– Capacitive and inductive couplingCapacitive and inductive coupling–– LeakageLeakage
•• SummarySummary
Stefan Rusu 9/2001 ©2001 Intel Corp. Page 3
Process Technology EvolutionProcess Technology Evolution
19611961First Planar Integrated Circuit First Planar Integrated Circuit
Two transistorsTwo transistors
20012001PentiumPentium 4 Processor4 Processor42 million transistors42 million transistors
Stefan Rusu 9/2001 ©2001 Intel Corp. Page 4
Moore�s Law Moore�s Law -- 19651965
ElectronicsElectronics, April 1965, April 1965
Stefan Rusu 9/2001 ©2001 Intel Corp. Page 5
Moore�s Law Moore�s Law -- TodayToday
•• Number of transistors per integrated circuit Number of transistors per integrated circuit doubles every two yearsdoubles every two years
Stefan Rusu 9/2001 ©2001 Intel Corp. Page 6
SIA Technology RoadmapSIA Technology Roadmap
Characteristic 1999 2001 2004 2008
Process Technology [nm] 180 130 90 60
Logic Transistors [mil] 23.8 47.6 135 539
Across-chip Clock Speed [MHz] 1200 1600 2000 2655
Die area [sq. mm] 340 340 390 468
Wiring Levels 6 7 8 9
Stefan Rusu 9/2001 ©2001 Intel Corp. Page 7
ITRS 2000 Update Review – December 2000
ITRS Roadmap Acceleration ContinuesITRS Roadmap Acceleration Continues
1994
19971998/1999
500
350
250
180
130100
70
50
35
25
Year of Production
Feat
ure
Size
(nm
)
95 97 99 01 04 07 10 13 16
2000
Stefan Rusu 9/2001 ©2001 Intel Corp. Page 8
Processor Frequency TrendProcessor Frequency Trend
•• Frequency doubles each generationFrequency doubles each generation•• Number of gates per clock reduces by 25%Number of gates per clock reduces by 25%
386486
Pentium
Pentium Pro
Pentium II
10
100
1,000
10,000
1987
1989
1991
1993
1995
1997
1999
2001
2003
2005
Freq
uenc
y [M
Hz]
1
10
100
Gat
e D
elay
s / C
lock
Intel Processors FrequencyGate delays/Clock
Pentium III
Pentium 4
Stefan Rusu 9/2001 ©2001 Intel Corp. Page 9
Processor Core Vs. Bus ClockProcessor Core Vs. Bus Clock
Bus frequency is not keeping up with the processor core
0
500
1000
1500
2000
2500
386
486-
33
486D
X2
486D
X4
P-10
0
P-15
0
P-20
0
PII-3
00
PII-4
00
PIII-
600
PIII-
700
PIII-
800
PIII-
1G
P4-1
.5G
P4-2
.0G
Processor
Clo
ck F
requ
ency
(MH
z) Core ClkBus Clk
Stefan Rusu 9/2001 ©2001 Intel Corp. Page 10
Processor Power TrendProcessor Power Trend
•• Lead processor power increases every generationLead processor power increases every generation•• Compactions provide higher performance at lower powerCompactions provide higher performance at lower power
386 386
486 486
Pentium
Pentium
MMX
Pentium Pro
Pentium II
1
10
100
1.5µµµµ 1µµµµ 0.8µµµµ 0.6µµµµ 0.35µµµµ 0.25µµµµ 0.18µµµµ 0.13µµµµ
Pow
er (W
atts
) Pentium III
Pentium 4
Stefan Rusu 9/2001 ©2001 Intel Corp. Page 11
Power Density TrendPower Density Trend
•• Assumptions: 15mm die, 1.5x frequency increase per generationAssumptions: 15mm die, 1.5x frequency increase per generation
0
50
100
150
200
250
0.25µµµµ 0.18µµµµ 0.13µµµµ 0.1µµµµ
Wat
ts
0
25
50
75
100
Pow
er D
ensi
ty (W
/cm
2 )Leakage Pwr
Active PwrPower Density
Stefan Rusu 9/2001 ©2001 Intel Corp. Page 12
Voltage ScalingVoltage Scaling
0.1
1
10
1991 1993 1995 1997 1999 2001 2003 2005 2007Year
Supp
ly V
olta
ge [V
]
~0.7X Scaling~0.85X Scaling
Stefan Rusu 9/2001 ©2001 Intel Corp. Page 13
Transistor Physical Gate Length Transistor Physical Gate Length
Source: Robert Chau, 6/2001
0.18um0.13um
90nm65nm
45nm
0.25um0.35um
0.5um
130nm
0.2um
70nm
50nm
30nm20nm
0.01
0.1
1
1991 1993 1995 1997 1999 2001 2003 2005 2007 2009
Year
Mic
ron
Technology Node
Transistor Physical Gate Length
Stefan Rusu 9/2001 ©2001 Intel Corp. Page 14
0.130.13µµm Process Technologym Process Technology
70nm Lgate NMOS transistor 70nm Lgate NMOS transistor –– in production todayin production todaySource: S. Tyagi, et.al., IEDM 2000
Stefan Rusu 9/2001 ©2001 Intel Corp. Page 15
Transistor Physical Gate Length Transistor Physical Gate Length
Source: Robert Chau, 6/2001
0.18um0.13um
90nm65nm
45nm
0.25um0.35um
0.5um
130nm
0.2um
70nm
50nm
30nm20nm
0.01
0.1
1
1991 1993 1995 1997 1999 2001 2003 2005 2007 2009
Year
Mic
ron
Technology Node
Transistor Physical Gate Length
Stefan Rusu 9/2001 ©2001 Intel Corp. Page 16
30nm Physical Gate Length 30nm Physical Gate Length TransistorTransistor
Source: R. Chau, et.al., IEDM 2000
For the 65nm technology node For the 65nm technology node –– production 2005production 2005
Stefan Rusu 9/2001 ©2001 Intel Corp. Page 17
Transistor Physical Gate Length Transistor Physical Gate Length
Source: R. Chau, 6/2001
0.18um0.13um
90nm65nm
45nm
0.25um0.35um
0.5um
130nm
0.2um
70nm
50nm
30nm20nm
0.01
0.1
1
1991 1993 1995 1997 1999 2001 2003 2005 2007 2009
Year
Mic
ron
Technology Node
Transistor Physical Gate Length
Stefan Rusu 9/2001 ©2001 Intel Corp. Page 18
Research Transistor with 20nm Research Transistor with 20nm Physical Gate LengthPhysical Gate Length
Source: R. Chau, et.al., SNW 2001
For the 45nm technology node For the 45nm technology node –– research phaseresearch phase
Stefan Rusu 9/2001 ©2001 Intel Corp. Page 19
Oxide Thickness ScalingOxide Thickness Scaling
Source: T. Ghani, VLSI Symposium, 2000
0
1
2
3
4
5
0.25 0.18 0.13 0.1 0.07
Technology Generation [um]
Oxi
de T
hick
ness
[nm
]
TOX (Electrical)
Equivalent OxideThickness (Physical)
Stefan Rusu 9/2001 ©2001 Intel Corp. Page 20
AtomsAtoms--Thin Gate OxideThin Gate Oxide
Source: R. Chau, et.al., IEDM 2000
Stefan Rusu 9/2001 ©2001 Intel Corp. Page 21
Moore�s Law + 300mm Wafers = Moore�s Law + 300mm Wafers = 4x advantage4x advantage
•• Moore’s Law:Moore’s Law:–– From 0.18µm to 0.13µm = From 0.18µm to 0.13µm =
2x output2x output
•• 300mm Wafers:300mm Wafers:–– From 200mm to 300mm = From 200mm to 300mm =
2x output2x output
•• Combined output Combined output advantage:advantage:–– 4x output4x output
Stefan Rusu 9/2001 ©2001 Intel Corp. Page 22
0.130.13µµµµµµµµm Production Rampm Production Ramp
•• Six factories readying Six factories readying 0.130.13µµµµµµµµm productionm production–– Plan to spend $7.5B on Plan to spend $7.5B on
capital in 2001capital in 2001•• Yields and volume Yields and volume
exceeding expectationsexceeding expectations–– 0.130.13µµµµµµµµm products have m products have
been shipping since Maybeen shipping since May
Stefan Rusu 9/2001 ©2001 Intel Corp. Page 23
Lithography ChallengesLithography Challenges
0.01
0.1
1
1989 1991 1993 1995 1997 1999 2001 2003 2005 2007
Year
Mic
ron
Lithography Wavelength
Silicon Feature Size
Stefan Rusu 9/2001 ©2001 Intel Corp. Page 24
Extreme Ultraviolet LithographyExtreme Ultraviolet Lithography•• EUV lithography uses extremely short wavelength light EUV lithography uses extremely short wavelength light
(20x shorter than today�s lithography processes)(20x shorter than today�s lithography processes)–– Visible light Visible light –– 400 to 700 nm400 to 700 nm–– DUV lithography DUV lithography –– 193 and 248 nm193 and 248 nm–– EUV lithography EUV lithography –– 13 nm13 nm
•• Will be used first in 2005 for critical lithography steps to Will be used first in 2005 for critical lithography steps to produce 70 nm patternsproduce 70 nm patterns
World�s First 6-inch EUV ETS Mask
Stefan Rusu 9/2001 ©2001 Intel Corp. Page 25
SRAM Cell Size ScalingSRAM Cell Size Scaling
•• SRAM cell size will continue to scale ~0.5x per generationSRAM cell size will continue to scale ~0.5x per generation
44
21
10.65.6
2.105
101520253035404550
SRA
M C
ell S
ize
[sq.
um]
0.5 0.35 0.25 0.18 0.13
Technology Generation [um]
Stefan Rusu 9/2001 ©2001 Intel Corp. Page 26
Exploit Memory Power EfficiencyExploit Memory Power Efficiency
•• Static memory has 10X lower active power densityStatic memory has 10X lower active power density•• Lower leakage than logicLower leakage than logic•• Integrated L2 provides higher bandwidth and lower latencyIntegrated L2 provides higher bandwidth and lower latency
1
10
100
0.25µ 0.18µ 0.13µ 0.1µ
Power Density (W/cm2)
1
10
100
0.25µ 0.18µ 0.13µ 0.1µ
Power Density (W/cm2)
Memory
Logic
Stefan Rusu 9/2001 ©2001 Intel Corp. Page 27
Example: PentiumExample: Pentium®® III Processor EvolutionIII Processor Evolution
•• 0.180.18µµm technologym technology•• 256KB L2256KB L2•• 28 million transistors28 million transistors•• 106 mm² die size106 mm² die size
•• 0.130.13µµm technologym technology•• 512KB L2512KB L2•• 44 million transistors44 million transistors•• 80 mm² die size80 mm² die size
Stefan Rusu 9/2001 ©2001 Intel Corp. Page 28
Bit Line Delay ScalingBit Line Delay Scaling
• Bit line swing limited by parameter mismatch & differential noise• Cell stability degrades with Vt lowering• Reducing number of rows per bitline approaching limit
0
0.2
0.4
0.6
0.8
1.0
1.2
0.25 0.18 0.13 0.10Technology generation [µµµµm]
Nor
mal
ized
del
ay
Logic circuit delayBit line delay (15% swing scaling)Bit line delay (constant swing)
Stefan Rusu 9/2001 ©2001 Intel Corp. Page 29
Within-Die Fluctuations
Systematic
Die-to-Die Fluctuations
Random Placement of Dopant Atoms
Lens AberrationsResist Thickness
Random
Process FluctuationsProcess Fluctuations
Source: K. Bowman, et.al., ISSCC�2001
Stefan Rusu 9/2001 ©2001 Intel Corp. Page 30
0.180.18µµm Al Interconnectm Al Interconnect
Metal 5Metal 5
Metal 4Metal 4Metal 3Metal 3Metal 2Metal 2Metal 1Metal 1
Metal 6Metal 6
TransistorsTransistors
Stefan Rusu 9/2001 ©2001 Intel Corp. Page 31
Wires Are Not Scaling Well Wires Are Not Scaling Well
0
5
10
15
20
25
30
35
40
45
0.65 0.5 0.35 0.25 0.18 0.13 0.1
Process Generation [um]
Del
ay [p
s]
Gate Al wires + SiO2 Cu wires + lowKGate + Al wires Gate + Cu wires
Source: SIA NTRS projection
Stefan Rusu 9/2001 ©2001 Intel Corp. Page 32
0.130.13µµm Cu Interconnectm Cu Interconnect
TransistorsTransistorsMetal 1Metal 1Metal 2Metal 2Metal 3Metal 3
Metal 4Metal 4
Metal 5Metal 5
Metal 6Metal 6
Source: S. Tyagi, et.al., IEDM 2000
Stefan Rusu 9/2001 ©2001 Intel Corp. Page 33
Metal LayersMetal Layers
0
1
2
3
4
5
6
7Nu
mbe
r of M
etal
Lay
ers
1.5 1 0.8 0.6 0.35 0.25 0.18 0.13
Technology Generation [um]
Stefan Rusu 9/2001 ©2001 Intel Corp. Page 34
Metal Aspect RatiosMetal Aspect Ratios
0
0.5
1
1.5
2A
vera
ge A
spec
t Rat
io
1.5 1 0.8 0.6 0.35 0.25 0.18 0.13
Technology Generation [um]
Stefan Rusu 9/2001 ©2001 Intel Corp. Page 35
Interconnect RC Delay vs. PitchInterconnect RC Delay vs. Pitch
•• 40% lower RC delay by using Cu + FSG ILD40% lower RC delay by using Cu + FSG ILDSource: S. Tyagi, et.al., IEDM 2000
Stefan Rusu 9/2001 ©2001 Intel Corp. Page 36
Routing a 70nm ProcessorRouting a 70nm Processor
M1
M3
M4
M5
M6
M7
M8
M9
M2
Super-Fat WiringTop 2 layers
Global routing
Fat Wiring2 metal layers
Cluster-level routing
Semi-Global Wiring2 metal layers
Unit-level routing
Local Wiring3 metal layers
Block-level routing
25m
m
Stefan Rusu 9/2001 ©2001 Intel Corp. Page 37
Noise SourcesNoise Sources•• Capacitive CouplingCapacitive Coupling
–– Due to electric fieldDue to electric field–– “Near” field effect“Near” field effect–– Measures resistance Measures resistance
to a voltage changeto a voltage change•• Inductive CouplingInductive Coupling
–– Due to magnetic fieldDue to magnetic field–– “Far” field effect“Far” field effect–– Measures resistance Measures resistance
to a current changeto a current change–– Frequency dependentFrequency dependent
Stefan Rusu 9/2001 ©2001 Intel Corp. Page 38
Inductive NoiseInductive Noise
•• Inductance of VLSI metal lines is becoming Inductance of VLSI metal lines is becoming important at operating frequencies above 1GHzimportant at operating frequencies above 1GHz
Impe
danc
e (O
hms/
cm)
1E+00
1E+01
1E+02
1E+03
1E+04
1E+08 1E+09 1E+10 1E+11
Frequency (Hz)
R
ωL
Impe
danc
e(O
hms/
cm)
1E-02
1E-01
1E+00
1E+01
1E+02
1E+06 1E+07 1E+8 1E+9
Frequency (Hz)
R
ωL
PCB (FR4) Signal TracePCB (FR4) Signal Trace VLSI Metal LineVLSI Metal Line
Stefan Rusu 9/2001 ©2001 Intel Corp. Page 39
Effects of Capacitive CouplingEffects of Capacitive Coupling•• Capacitive coupling can translate into a Capacitive coupling can translate into a
noise problem noise problem
•• or a delay problemor a delay problem
VictimVictim
AggressorAggressor
VictimVictim
AggressorAggressor
Stefan Rusu 9/2001 ©2001 Intel Corp. Page 40
Worst Case Input PatternsWorst Case Input Patterns
victimvictim nearnearnearnear farfarfarfar
CC--onlyonly !! Near attackers couple mostly Near attackers couple mostly by capacitanceby capacitance
!! Far attackers couple mostly Far attackers couple mostly by inductanceby inductance
!! Lenz’s law Lenz’s law -- a change in a change in current will generate an current will generate an opposingopposing current which current which resists the changeresists the change
!! WorstWorst--case switching pattern case switching pattern when near and far attackers when near and far attackers switch antiswitch anti--phasephase
LL--onlyonly
C & L cancelC & L cancel
C & L additiveC & L additive
Stefan Rusu 9/2001 ©2001 Intel Corp. Page 41
Inductive Noise Impact on DelayInductive Noise Impact on Delay
!! Capacitive noise effect on Capacitive noise effect on delay is modeled by delay is modeled by coupling coefficientcoupling coefficient
!! Inductive noise affects Inductive noise affects delay toodelay too
!! Inductive noise can also Inductive noise can also decrease delaydecrease delay
RLC delay w/ far-attackers switching down
00 0.50.5 11 1.51.5 22Coupling CoefficientCoupling Coefficient
RC ONLY delay
RLC delay w/ far-attackers switching up
Del
ayD
elay
Stefan Rusu 9/2001 ©2001 Intel Corp. Page 42
0.10.1
1.01.0
10.010.0
11 1010 100100Frequency [GHz]Frequency [GHz]
Skin
dep
th [
Skin
dep
th [ µµ µµµµ µµ
m]
m]
Cu [µµµµm]Al [µµµµm]
0.8µµµµm
0.65µµµµm
2.6µµµµm
2.1µµµµm0.26µµµµm
0.21µµµµm
Skin Effect in VLSI CircuitsSkin Effect in VLSI Circuits
•• Edge frequency is 5Edge frequency is 5--9x the clock frequency9x the clock frequency
Stefan Rusu 9/2001 ©2001 Intel Corp. Page 43
SubSub--Threshold LeakageThreshold Leakage
•• SubSub--threshold leakage increases for lower threshold leakage increases for lower channel lengths and lower Vchannel lengths and lower VTT�s�s
Stefan Rusu 9/2001 ©2001 Intel Corp. Page 44
Estimated Power of a 15mm ProcessorEstimated Power of a 15mm Processor
0.25µµµµm, 2V
0% 0% 0% 0% 1% 1% 1% 2% 3%
10203040506070
30 40 50 60 70 80 90 100
110
Temp (C)
Pow
er (W
atts
)
LeakageActive
0.18µµµµm, 1.4V
0% 0% 1% 1% 2% 3% 5% 7% 9%
10203040506070
30 40 50 60 70 80 90 100
110
Temp (C)
Pow
er (W
atts
)
LeakageActive
0.13µµµµm, 1V
1% 2% 3% 5% 8% 11% 15% 20%26%
10203040506070
30 40 50 60 70 80 90 100
110
Temp (C)
Pow
er (W
atts
)
LeakageActive
0.1µµµµm, 0.7V
6% 9% 14% 19%26%
33%41% 49% 56%
1020304050
6070
30 40 50 60 70 80 90 100
110
Temp (C)
Pow
er (W
atts
)
LeakageActive
Stefan Rusu 9/2001 ©2001 Intel Corp. Page 45
Leakage ImpactLeakage Impact
11
1010
100100
1,0001,000
10,00010,000
3030 4040 5050 6060 7070 8080 9090 100100 110110
Temp (C)Temp (C)
Ioff
(na/
Ioff
(na/
µµ µµµµ µµ m)
m)
0.10µµµµm0.13µµµµm0.18µµµµm0.25µµµµm
•• Design issues: Design issues: –– Dynamic circuits may failDynamic circuits may fail–– Design workarounds needed to guarantee burnDesign workarounds needed to guarantee burn--in functionalityin functionality
•• Test issues:Test issues:–– IDDQ testing may become ineffectiveIDDQ testing may become ineffective–– ThermalThermal--runaway problems, especially at burnrunaway problems, especially at burn--inin
Stefan Rusu 9/2001 ©2001 Intel Corp. Page 46
ConclusionConclusion•• We still have not found a fundamental We still have not found a fundamental
barrier to extending Moore’s lawbarrier to extending Moore’s law•• The challenges are Power and EfficiencyThe challenges are Power and Efficiency
–– Focus on dissipation, delivery, densityFocus on dissipation, delivery, density•• VLSI technology scaling is expected to VLSI technology scaling is expected to
continue for the next decadecontinue for the next decade